From 69c73cfc4ef9fbf2d2beebc1c213892604a86ff6 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Sun, 7 Mar 2021 11:40:02 -0500 Subject: [PATCH] target/riscv: vector floating-point square-root instruction Backports d9e4ce72a5a0f7c404156d40d3252d4d6a9d6a36 --- qemu/header_gen.py | 3 ++ qemu/riscv32.h | 3 ++ qemu/riscv64.h | 3 ++ qemu/target/riscv/helper.h | 4 ++ qemu/target/riscv/insn32.decode | 3 ++ qemu/target/riscv/insn_trans/trans_rvv.inc.c | 44 ++++++++++++++++++++ qemu/target/riscv/vector_helper.c | 43 +++++++++++++++++++ 7 files changed, 103 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index c18991fd..c2eab7e6 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7091,6 +7091,9 @@ riscv_symbols = ( 'helper_vfwmsac_vf_w', 'helper_vfwnmsac_vf_h', 'helper_vfwnmsac_vf_w', + 'helper_vfsqrt_v_h', + 'helper_vfsqrt_v_w', + 'helper_vfsqrt_v_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 7ddddc5e..902367a2 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4527,6 +4527,9 @@ #define helper_vfwmsac_vf_w helper_vfwmsac_vf_w_riscv32 #define helper_vfwnmsac_vf_h helper_vfwnmsac_vf_h_riscv32 #define helper_vfwnmsac_vf_w helper_vfwnmsac_vf_w_riscv32 +#define helper_vfsqrt_v_h helper_vfsqrt_v_h_riscv32 +#define helper_vfsqrt_v_w helper_vfsqrt_v_w_riscv32 +#define helper_vfsqrt_v_d helper_vfsqrt_v_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 3c97ef56..ab297261 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4527,6 +4527,9 @@ #define helper_vfwmsac_vf_w helper_vfwmsac_vf_w_riscv64 #define helper_vfwnmsac_vf_h helper_vfwnmsac_vf_h_riscv64 #define helper_vfwnmsac_vf_w helper_vfwnmsac_vf_w_riscv64 +#define helper_vfsqrt_v_h helper_vfsqrt_v_h_riscv64 +#define helper_vfsqrt_v_w helper_vfsqrt_v_w_riscv64 +#define helper_vfsqrt_v_d helper_vfsqrt_v_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index 312c58e2..420de83c 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -926,3 +926,7 @@ DEF_HELPER_6(vfwmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_5(vfsqrt_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfsqrt_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfsqrt_v_d, void, ptr, ptr, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index c9d50783..0d58c4c5 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -45,6 +45,7 @@ &shift shamt rs1 rd &atomic aq rl rs2 rs1 rd &rmrr vm rd rs1 rs2 +&rmr vm rd rs2 &rwdvm vm wd rd rs1 rs2 &r2nfvm vm rd rs1 nf &rnfvm vm rd rs1 rs2 nf @@ -68,6 +69,7 @@ @r2_rm ....... ..... ..... ... ..... ....... %rs1 %rm %rd @r2 ....... ..... ..... ... ..... ....... %rs1 %rd @r2_nfvm ... ... vm:1 ..... ..... ... ..... ....... &r2nfvm %nf %rs1 %rd +@r2_vm ...... vm:1 ..... ..... ... ..... ....... &rmr %rs2 %rd @r_nfvm ... ... vm:1 ..... ..... ... ..... ....... &rnfvm %nf %rs2 %rs1 %rd @r_vm ...... vm:1 ..... ..... ... ..... ....... &rmrr %rs2 %rs1 %rd @r_vm_1 ...... . ..... ..... ... ..... ....... &rmrr vm=1 %rs2 %rs1 %rd @@ -489,6 +491,7 @@ vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm +vfsqrt_v 100011 . ..... 00000 001 ..... 1010111 @r2_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index d78e2285..bce868a9 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2121,3 +2121,47 @@ GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf) GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf) GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf) GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) + +/* Vector Floating-Point Square-Root Instruction */ + +/* + * If the current SEW does not correspond to a supported IEEE floating-point + * type, an illegal instruction exception is raised + */ +static bool opfv_check(DisasContext *s, arg_rmr *a) +{ + return (vext_check_isa_ill(s) && + vext_check_overlap_mask(s, a->rd, a->vm, false) && + vext_check_reg(s, a->rd, false) && + vext_check_reg(s, a->rs2, false) && + (s->sew != 0)); +} + +#define GEN_OPFV_TRANS(NAME, CHECK) \ +static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ +{ \ + TCGContext *tcg_ctx = s->uc->tcg_ctx; \ + if (CHECK(s, a)) { \ + uint32_t data = 0; \ + static gen_helper_gvec_3_ptr * const fns[3] = { \ + gen_helper_##NAME##_h, \ + gen_helper_##NAME##_w, \ + gen_helper_##NAME##_d, \ + }; \ + TCGLabel *over = gen_new_label(tcg_ctx); \ + gen_set_rm(s, 7); \ + tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_EQ, tcg_ctx->cpu_vl_risc, 0, over); \ + \ + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); \ + data = FIELD_DP32(data, VDATA, VM, a->vm); \ + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ + tcg_gen_gvec_3_ptr(tcg_ctx, vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ + vreg_ofs(s, a->rs2), tcg_ctx->cpu_env, 0, \ + s->vlen / 8, data, fns[s->sew - 1]); \ + gen_set_label(tcg_ctx, over); \ + return true; \ + } \ + return false; \ +} + +GEN_OPFV_TRANS(vfsqrt_v, opfv_check) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index d3165e07..674dd158 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -3775,3 +3775,46 @@ RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16) RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32) GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4, clearl) GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8, clearq) + +/* Vector Floating-Point Square-Root Instruction */ +/* (TD, T2, TX2) */ +#define OP_UU_H uint16_t, uint16_t, uint16_t +#define OP_UU_W uint32_t, uint32_t, uint32_t +#define OP_UU_D uint64_t, uint64_t, uint64_t + +#define OPFVV1(NAME, TD, T2, TX2, HD, HS2, OP) \ +static void do_##NAME(void *vd, void *vs2, int i, \ + CPURISCVState *env) \ +{ \ + TX2 s2 = *((T2 *)vs2 + HS2(i)); \ + *((TD *)vd + HD(i)) = OP(s2, &env->fp_status); \ +} + +#define GEN_VEXT_V_ENV(NAME, ESZ, DSZ, CLEAR_FN) \ +void HELPER(NAME)(void *vd, void *v0, void *vs2, \ + CPURISCVState *env, uint32_t desc) \ +{ \ + uint32_t vlmax = vext_maxsz(desc) / ESZ; \ + uint32_t mlen = vext_mlen(desc); \ + uint32_t vm = vext_vm(desc); \ + uint32_t vl = env->vl; \ + uint32_t i; \ + \ + if (vl == 0) { \ + return; \ + } \ + for (i = 0; i < vl; i++) { \ + if (!vm && !vext_elem_mask(v0, mlen, i)) { \ + continue; \ + } \ + do_##NAME(vd, vs2, i, env); \ + } \ + CLEAR_FN(vd, vl, vl * DSZ, vlmax * DSZ); \ +} + +RVVCALL(OPFVV1, vfsqrt_v_h, OP_UU_H, H2, H2, float16_sqrt) +RVVCALL(OPFVV1, vfsqrt_v_w, OP_UU_W, H4, H4, float32_sqrt) +RVVCALL(OPFVV1, vfsqrt_v_d, OP_UU_D, H8, H8, float64_sqrt) +GEN_VEXT_V_ENV(vfsqrt_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfsqrt_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfsqrt_v_d, 8, 8, clearq)