From 6aabd67ef8d4f779538223f1d72a45eb70412f2b Mon Sep 17 00:00:00 2001 From: Alistair Francis Date: Sun, 22 Mar 2020 01:32:07 -0400 Subject: [PATCH] target/riscv: Set VS bits in mideleg for Hyp extension Backports commit 713d8363deb3774db14fb88a9fcd99687dcef114 from qemu --- qemu/target/riscv/csr.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/qemu/target/riscv/csr.c b/qemu/target/riscv/csr.c index ee96ff85..b48c6258 100644 --- a/qemu/target/riscv/csr.c +++ b/qemu/target/riscv/csr.c @@ -448,6 +448,9 @@ static int read_mideleg(CPURISCVState *env, int csrno, target_ulong *val) static int write_mideleg(CPURISCVState *env, int csrno, target_ulong val) { env->mideleg = (env->mideleg & ~delegable_ints) | (val & delegable_ints); + if (riscv_has_ext(env, RVH)) { + env->mideleg |= VS_MODE_INTERRUPTS; + } return 0; }