diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 9f070e58..7ff46af9 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -5546,6 +5546,7 @@ riscv_symbols = (
     'riscv_cpu_set_fflags',
     'riscv_cpu_set_mode',
     'riscv_cpu_tlb_fill',
+    'riscv_cpu_unassigned_access',
     'riscv_cpu_update_mip',
     'riscv_csrrw',
     'riscv_csrrw_debug',
diff --git a/qemu/riscv32.h b/qemu/riscv32.h
index 00529ccd..e4bdf456 100644
--- a/qemu/riscv32.h
+++ b/qemu/riscv32.h
@@ -3453,6 +3453,7 @@
 #define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv32
 #define riscv_cpu_set_mode riscv_cpu_set_mode_riscv32
 #define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv32
+#define riscv_cpu_unassigned_access riscv_cpu_unassigned_access_riscv32
 #define riscv_cpu_update_mip riscv_cpu_update_mip_riscv32
 #define riscv_csrrw riscv_csrrw_riscv32
 #define riscv_csrrw_debug riscv_csrrw_debug_riscv32
diff --git a/qemu/riscv64.h b/qemu/riscv64.h
index 4b3c3759..7bb8d91d 100644
--- a/qemu/riscv64.h
+++ b/qemu/riscv64.h
@@ -3453,6 +3453,7 @@
 #define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv64
 #define riscv_cpu_set_mode riscv_cpu_set_mode_riscv64
 #define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv64
+#define riscv_cpu_unassigned_access riscv_cpu_unassigned_access_riscv64
 #define riscv_cpu_update_mip riscv_cpu_update_mip_riscv64
 #define riscv_csrrw riscv_csrrw_riscv64
 #define riscv_csrrw_debug riscv_csrrw_debug_riscv64
diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c
index 2ce88330..ce548f94 100644
--- a/qemu/target/riscv/cpu.c
+++ b/qemu/target/riscv/cpu.c
@@ -356,6 +356,7 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
     //cc->gdb_stop_before_watchpoint = true;
     //cc->disas_set_info = riscv_cpu_disas_set_info;
 #ifndef CONFIG_USER_ONLY
+    cc->do_unassigned_access = riscv_cpu_unassigned_access;
     cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
     cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
 #endif
diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index 345bfcdf..49d781d1 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -249,6 +249,8 @@ void  riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
                         MMUAccessType access_type, int mmu_idx,
                         bool probe, uintptr_t retaddr);
+void riscv_cpu_unassigned_access(CPUState *cpu, hwaddr addr, bool is_write,
+                                 bool is_exec, int unused, unsigned size);
 char *riscv_isa_string(RISCVCPU *cpu);
 void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf);
 
diff --git a/qemu/target/riscv/cpu_helper.c b/qemu/target/riscv/cpu_helper.c
index acdc12f7..8f0283e7 100644
--- a/qemu/target/riscv/cpu_helper.c
+++ b/qemu/target/riscv/cpu_helper.c
@@ -357,6 +357,22 @@ hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
     return phys_addr;
 }
 
+void riscv_cpu_unassigned_access(CPUState *cs, hwaddr addr, bool is_write,
+                                 bool is_exec, int unused, unsigned size)
+{
+    RISCVCPU *cpu = RISCV_CPU(cs->uc, cs);
+    CPURISCVState *env = &cpu->env;
+
+    if (is_write) {
+        cs->exception_index = RISCV_EXCP_STORE_AMO_ACCESS_FAULT;
+    } else {
+        cs->exception_index = RISCV_EXCP_LOAD_ACCESS_FAULT;
+    }
+
+    env->badaddr = addr;
+    riscv_raise_exception(&cpu->env, cs->exception_index, GETPC());
+}
+
 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
                                    MMUAccessType access_type, int mmu_idx,
                                    uintptr_t retaddr)