From 6d070f13465d6cef99ec6c2ec4817e64a3add53a Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Mon, 18 Nov 2019 23:22:55 -0500 Subject: [PATCH] target/mips: Clean up handling of CP0 register 20 Clean up handling of CP0 register 20. Backports commit 14f92b0b9ca0abe48f9a23a73e8dc413d919eab9 from qemu --- qemu/target/mips/translate.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 9f6343c1..c16da24e 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -7420,7 +7420,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_XContext)); @@ -8156,7 +8156,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: #if defined(TARGET_MIPS64) check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(tcg_ctx, tcg_ctx->cpu_env, arg); @@ -8889,7 +8889,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_XContext)); register_name = "XContext"; @@ -9603,7 +9603,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case CP0_REGISTER_20: switch (sel) { - case 0: + case CP0_REG20__XCONTEXT: check_insn(ctx, ISA_MIPS3); gen_helper_mtc0_xcontext(tcg_ctx, tcg_ctx->cpu_env, arg); register_name = "XContext";