diff --git a/qemu/aarch64.h b/qemu/aarch64.h
index f4286c66..f3aa3277 100644
--- a/qemu/aarch64.h
+++ b/qemu/aarch64.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_aarch64
 #define helper_get_r13_banked helper_get_r13_banked_aarch64
 #define helper_get_user_reg helper_get_user_reg_aarch64
+#define helper_gvec_abs8 helper_gvec_abs8_aarch64
+#define helper_gvec_abs16 helper_gvec_abs16_aarch64
+#define helper_gvec_abs32 helper_gvec_abs32_aarch64
+#define helper_gvec_abs64 helper_gvec_abs64_aarch64
 #define helper_gvec_add8 helper_gvec_add8_aarch64
 #define helper_gvec_add16 helper_gvec_add16_aarch64
 #define helper_gvec_add32 helper_gvec_add32_aarch64
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_aarch64
 #define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_aarch64
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_aarch64
diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h
index cebc3411..0c757bf7 100644
--- a/qemu/aarch64eb.h
+++ b/qemu/aarch64eb.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_aarch64eb
 #define helper_get_r13_banked helper_get_r13_banked_aarch64eb
 #define helper_get_user_reg helper_get_user_reg_aarch64eb
+#define helper_gvec_abs8 helper_gvec_abs8_aarch64eb
+#define helper_gvec_abs16 helper_gvec_abs16_aarch64eb
+#define helper_gvec_abs32 helper_gvec_abs32_aarch64eb
+#define helper_gvec_abs64 helper_gvec_abs64_aarch64eb
 #define helper_gvec_add8 helper_gvec_add8_aarch64eb
 #define helper_gvec_add16 helper_gvec_add16_aarch64eb
 #define helper_gvec_add32 helper_gvec_add32_aarch64eb
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_aarch64eb
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_aarch64eb
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_aarch64eb
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_aarch64eb
 #define tcg_gen_gvec_add tcg_gen_gvec_add_aarch64eb
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_aarch64eb
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_aarch64eb
diff --git a/qemu/accel/tcg/tcg-runtime-gvec.c b/qemu/accel/tcg/tcg-runtime-gvec.c
index 2152fb69..0f09e0ef 100644
--- a/qemu/accel/tcg/tcg-runtime-gvec.c
+++ b/qemu/accel/tcg/tcg-runtime-gvec.c
@@ -398,6 +398,54 @@ void HELPER(gvec_neg64)(void *d, void *a, uint32_t desc)
     clear_high(d, oprsz, desc);
 }
 
+void HELPER(gvec_abs8)(void *d, void *a, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(int8_t)) {
+        int8_t aa = *(int8_t *)(a + i);
+        *(int8_t *)(d + i) = aa < 0 ? -aa : aa;
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_abs16)(void *d, void *a, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(int16_t)) {
+        int16_t aa = *(int16_t *)(a + i);
+        *(int16_t *)(d + i) = aa < 0 ? -aa : aa;
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_abs32)(void *d, void *a, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(int32_t)) {
+        int32_t aa = *(int32_t *)(a + i);
+        *(int32_t *)(d + i) = aa < 0 ? -aa : aa;
+    }
+    clear_high(d, oprsz, desc);
+}
+
+void HELPER(gvec_abs64)(void *d, void *a, uint32_t desc)
+{
+    intptr_t oprsz = simd_oprsz(desc);
+    intptr_t i;
+
+    for (i = 0; i < oprsz; i += sizeof(int64_t)) {
+        int64_t aa = *(int64_t *)(a + i);
+        *(int64_t *)(d + i) = aa < 0 ? -aa : aa;
+    }
+    clear_high(d, oprsz, desc);
+}
+
 void HELPER(gvec_mov)(void *d, void *a, uint32_t desc)
 {
     intptr_t oprsz = simd_oprsz(desc);
diff --git a/qemu/accel/tcg/tcg-runtime.h b/qemu/accel/tcg/tcg-runtime.h
index ed3ce5fd..6d73dc2d 100644
--- a/qemu/accel/tcg/tcg-runtime.h
+++ b/qemu/accel/tcg/tcg-runtime.h
@@ -225,6 +225,11 @@ DEF_HELPER_FLAGS_3(gvec_neg16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(gvec_neg32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_3(gvec_neg64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 
+DEF_HELPER_FLAGS_3(gvec_abs8, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_abs16, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_abs32, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+DEF_HELPER_FLAGS_3(gvec_abs64, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
+
 DEF_HELPER_FLAGS_3(gvec_not, TCG_CALL_NO_RWG, void, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_and, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
 DEF_HELPER_FLAGS_4(gvec_or, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
diff --git a/qemu/arm.h b/qemu/arm.h
index 1f677522..265d1b88 100644
--- a/qemu/arm.h
+++ b/qemu/arm.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_arm
 #define helper_get_r13_banked helper_get_r13_banked_arm
 #define helper_get_user_reg helper_get_user_reg_arm
+#define helper_gvec_abs8 helper_gvec_abs8_arm
+#define helper_gvec_abs16 helper_gvec_abs16_arm
+#define helper_gvec_abs32 helper_gvec_abs32_arm
+#define helper_gvec_abs64 helper_gvec_abs64_arm
 #define helper_gvec_add8 helper_gvec_add8_arm
 #define helper_gvec_add16 helper_gvec_add16_arm
 #define helper_gvec_add32 helper_gvec_add32_arm
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_arm
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_arm
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_arm
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_arm
 #define tcg_gen_gvec_add tcg_gen_gvec_add_arm
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_arm
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_arm
diff --git a/qemu/armeb.h b/qemu/armeb.h
index 64abcefd..6b95a0be 100644
--- a/qemu/armeb.h
+++ b/qemu/armeb.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_armeb
 #define helper_get_r13_banked helper_get_r13_banked_armeb
 #define helper_get_user_reg helper_get_user_reg_armeb
+#define helper_gvec_abs8 helper_gvec_abs8_armeb
+#define helper_gvec_abs16 helper_gvec_abs16_armeb
+#define helper_gvec_abs32 helper_gvec_abs32_armeb
+#define helper_gvec_abs64 helper_gvec_abs64_armeb
 #define helper_gvec_add8 helper_gvec_add8_armeb
 #define helper_gvec_add16 helper_gvec_add16_armeb
 #define helper_gvec_add32 helper_gvec_add32_armeb
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_armeb
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_armeb
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_armeb
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_armeb
 #define tcg_gen_gvec_add tcg_gen_gvec_add_armeb
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_armeb
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_armeb
diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 166f10d9..ce95e062 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -1119,6 +1119,10 @@ symbols = (
     'helper_get_cp_reg64',
     'helper_get_r13_banked',
     'helper_get_user_reg',
+    'helper_gvec_abs8',
+    'helper_gvec_abs16',
+    'helper_gvec_abs32',
+    'helper_gvec_abs64',
     'helper_gvec_add8',
     'helper_gvec_add16',
     'helper_gvec_add32',
@@ -2873,6 +2877,7 @@ symbols = (
     'tcg_gen_gvec_4_ool',
     'tcg_gen_gvec_4_ptr',
     'tcg_gen_gvec_5_ool',
+    'tcg_gen_gvec_abs',
     'tcg_gen_gvec_add',
     'tcg_gen_gvec_addi',
     'tcg_gen_gvec_adds',
diff --git a/qemu/m68k.h b/qemu/m68k.h
index 38c9e788..88955e36 100644
--- a/qemu/m68k.h
+++ b/qemu/m68k.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_m68k
 #define helper_get_r13_banked helper_get_r13_banked_m68k
 #define helper_get_user_reg helper_get_user_reg_m68k
+#define helper_gvec_abs8 helper_gvec_abs8_m68k
+#define helper_gvec_abs16 helper_gvec_abs16_m68k
+#define helper_gvec_abs32 helper_gvec_abs32_m68k
+#define helper_gvec_abs64 helper_gvec_abs64_m68k
 #define helper_gvec_add8 helper_gvec_add8_m68k
 #define helper_gvec_add16 helper_gvec_add16_m68k
 #define helper_gvec_add32 helper_gvec_add32_m68k
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_m68k
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_m68k
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_m68k
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_m68k
 #define tcg_gen_gvec_add tcg_gen_gvec_add_m68k
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_m68k
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_m68k
diff --git a/qemu/mips.h b/qemu/mips.h
index 5253fc56..94722eae 100644
--- a/qemu/mips.h
+++ b/qemu/mips.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_mips
 #define helper_get_r13_banked helper_get_r13_banked_mips
 #define helper_get_user_reg helper_get_user_reg_mips
+#define helper_gvec_abs8 helper_gvec_abs8_mips
+#define helper_gvec_abs16 helper_gvec_abs16_mips
+#define helper_gvec_abs32 helper_gvec_abs32_mips
+#define helper_gvec_abs64 helper_gvec_abs64_mips
 #define helper_gvec_add8 helper_gvec_add8_mips
 #define helper_gvec_add16 helper_gvec_add16_mips
 #define helper_gvec_add32 helper_gvec_add32_mips
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips
 #define tcg_gen_gvec_add tcg_gen_gvec_add_mips
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_mips
diff --git a/qemu/mips64.h b/qemu/mips64.h
index e3c7c6f0..182f0683 100644
--- a/qemu/mips64.h
+++ b/qemu/mips64.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_mips64
 #define helper_get_r13_banked helper_get_r13_banked_mips64
 #define helper_get_user_reg helper_get_user_reg_mips64
+#define helper_gvec_abs8 helper_gvec_abs8_mips64
+#define helper_gvec_abs16 helper_gvec_abs16_mips64
+#define helper_gvec_abs32 helper_gvec_abs32_mips64
+#define helper_gvec_abs64 helper_gvec_abs64_mips64
 #define helper_gvec_add8 helper_gvec_add8_mips64
 #define helper_gvec_add16 helper_gvec_add16_mips64
 #define helper_gvec_add32 helper_gvec_add32_mips64
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips64
 #define tcg_gen_gvec_add tcg_gen_gvec_add_mips64
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips64
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_mips64
diff --git a/qemu/mips64el.h b/qemu/mips64el.h
index 17831fa0..31c3cd0b 100644
--- a/qemu/mips64el.h
+++ b/qemu/mips64el.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_mips64el
 #define helper_get_r13_banked helper_get_r13_banked_mips64el
 #define helper_get_user_reg helper_get_user_reg_mips64el
+#define helper_gvec_abs8 helper_gvec_abs8_mips64el
+#define helper_gvec_abs16 helper_gvec_abs16_mips64el
+#define helper_gvec_abs32 helper_gvec_abs32_mips64el
+#define helper_gvec_abs64 helper_gvec_abs64_mips64el
 #define helper_gvec_add8 helper_gvec_add8_mips64el
 #define helper_gvec_add16 helper_gvec_add16_mips64el
 #define helper_gvec_add32 helper_gvec_add32_mips64el
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mips64el
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mips64el
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mips64el
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_mips64el
 #define tcg_gen_gvec_add tcg_gen_gvec_add_mips64el
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_mips64el
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_mips64el
diff --git a/qemu/mipsel.h b/qemu/mipsel.h
index 5abeea76..a81b0d51 100644
--- a/qemu/mipsel.h
+++ b/qemu/mipsel.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_mipsel
 #define helper_get_r13_banked helper_get_r13_banked_mipsel
 #define helper_get_user_reg helper_get_user_reg_mipsel
+#define helper_gvec_abs8 helper_gvec_abs8_mipsel
+#define helper_gvec_abs16 helper_gvec_abs16_mipsel
+#define helper_gvec_abs32 helper_gvec_abs32_mipsel
+#define helper_gvec_abs64 helper_gvec_abs64_mipsel
 #define helper_gvec_add8 helper_gvec_add8_mipsel
 #define helper_gvec_add16 helper_gvec_add16_mipsel
 #define helper_gvec_add32 helper_gvec_add32_mipsel
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_mipsel
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_mipsel
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_mipsel
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_mipsel
 #define tcg_gen_gvec_add tcg_gen_gvec_add_mipsel
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_mipsel
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_mipsel
diff --git a/qemu/powerpc.h b/qemu/powerpc.h
index 36bf76c5..d3e87a58 100644
--- a/qemu/powerpc.h
+++ b/qemu/powerpc.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_powerpc
 #define helper_get_r13_banked helper_get_r13_banked_powerpc
 #define helper_get_user_reg helper_get_user_reg_powerpc
+#define helper_gvec_abs8 helper_gvec_abs8_powerpc
+#define helper_gvec_abs16 helper_gvec_abs16_powerpc
+#define helper_gvec_abs32 helper_gvec_abs32_powerpc
+#define helper_gvec_abs64 helper_gvec_abs64_powerpc
 #define helper_gvec_add8 helper_gvec_add8_powerpc
 #define helper_gvec_add16 helper_gvec_add16_powerpc
 #define helper_gvec_add32 helper_gvec_add32_powerpc
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_powerpc
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_powerpc
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_powerpc
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_powerpc
 #define tcg_gen_gvec_add tcg_gen_gvec_add_powerpc
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_powerpc
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_powerpc
diff --git a/qemu/riscv32.h b/qemu/riscv32.h
index 7069cc0f..6bb75b68 100644
--- a/qemu/riscv32.h
+++ b/qemu/riscv32.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_riscv32
 #define helper_get_r13_banked helper_get_r13_banked_riscv32
 #define helper_get_user_reg helper_get_user_reg_riscv32
+#define helper_gvec_abs8 helper_gvec_abs8_riscv32
+#define helper_gvec_abs16 helper_gvec_abs16_riscv32
+#define helper_gvec_abs32 helper_gvec_abs32_riscv32
+#define helper_gvec_abs64 helper_gvec_abs64_riscv32
 #define helper_gvec_add8 helper_gvec_add8_riscv32
 #define helper_gvec_add16 helper_gvec_add16_riscv32
 #define helper_gvec_add32 helper_gvec_add32_riscv32
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv32
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv32
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv32
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_riscv32
 #define tcg_gen_gvec_add tcg_gen_gvec_add_riscv32
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv32
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_riscv32
diff --git a/qemu/riscv64.h b/qemu/riscv64.h
index 08c8d239..7f44d6e0 100644
--- a/qemu/riscv64.h
+++ b/qemu/riscv64.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_riscv64
 #define helper_get_r13_banked helper_get_r13_banked_riscv64
 #define helper_get_user_reg helper_get_user_reg_riscv64
+#define helper_gvec_abs8 helper_gvec_abs8_riscv64
+#define helper_gvec_abs16 helper_gvec_abs16_riscv64
+#define helper_gvec_abs32 helper_gvec_abs32_riscv64
+#define helper_gvec_abs64 helper_gvec_abs64_riscv64
 #define helper_gvec_add8 helper_gvec_add8_riscv64
 #define helper_gvec_add16 helper_gvec_add16_riscv64
 #define helper_gvec_add32 helper_gvec_add32_riscv64
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv64
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv64
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv64
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_riscv64
 #define tcg_gen_gvec_add tcg_gen_gvec_add_riscv64
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv64
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_riscv64
diff --git a/qemu/sparc.h b/qemu/sparc.h
index 49d8ec57..11793de7 100644
--- a/qemu/sparc.h
+++ b/qemu/sparc.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_sparc
 #define helper_get_r13_banked helper_get_r13_banked_sparc
 #define helper_get_user_reg helper_get_user_reg_sparc
+#define helper_gvec_abs8 helper_gvec_abs8_sparc
+#define helper_gvec_abs16 helper_gvec_abs16_sparc
+#define helper_gvec_abs32 helper_gvec_abs32_sparc
+#define helper_gvec_abs64 helper_gvec_abs64_sparc
 #define helper_gvec_add8 helper_gvec_add8_sparc
 #define helper_gvec_add16 helper_gvec_add16_sparc
 #define helper_gvec_add32 helper_gvec_add32_sparc
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_sparc
 #define tcg_gen_gvec_add tcg_gen_gvec_add_sparc
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_sparc
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_sparc
diff --git a/qemu/sparc64.h b/qemu/sparc64.h
index b140ed02..3982a6ca 100644
--- a/qemu/sparc64.h
+++ b/qemu/sparc64.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_sparc64
 #define helper_get_r13_banked helper_get_r13_banked_sparc64
 #define helper_get_user_reg helper_get_user_reg_sparc64
+#define helper_gvec_abs8 helper_gvec_abs8_sparc64
+#define helper_gvec_abs16 helper_gvec_abs16_sparc64
+#define helper_gvec_abs32 helper_gvec_abs32_sparc64
+#define helper_gvec_abs64 helper_gvec_abs64_sparc64
 #define helper_gvec_add8 helper_gvec_add8_sparc64
 #define helper_gvec_add16 helper_gvec_add16_sparc64
 #define helper_gvec_add32 helper_gvec_add32_sparc64
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_sparc64
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_sparc64
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_sparc64
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_sparc64
 #define tcg_gen_gvec_add tcg_gen_gvec_add_sparc64
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_sparc64
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_sparc64
diff --git a/qemu/tcg/README b/qemu/tcg/README
index 3d06d61e..197ee692 100644
--- a/qemu/tcg/README
+++ b/qemu/tcg/README
@@ -556,6 +556,10 @@ E.g. VECL=1 -> 64 << 1 -> v128, and VECE=2 -> 1 << 2 -> i32.
 
   Similarly, v0 = -v1.
 
+* abs_vec   v0, v1
+
+  Similarly, v0 = v1 < 0 ? -v1 : v1, in elements across the vector.
+
 * smin_vec:
 * umin_vec:
 
diff --git a/qemu/tcg/aarch64/tcg-target.h b/qemu/tcg/aarch64/tcg-target.h
index f5640a22..21d06d92 100644
--- a/qemu/tcg/aarch64/tcg-target.h
+++ b/qemu/tcg/aarch64/tcg-target.h
@@ -132,6 +132,7 @@ typedef enum {
 #define TCG_TARGET_HAS_orc_vec          1
 #define TCG_TARGET_HAS_not_vec          1
 #define TCG_TARGET_HAS_neg_vec          1
+#define TCG_TARGET_HAS_abs_vec          0
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          0
 #define TCG_TARGET_HAS_shv_vec          1
diff --git a/qemu/tcg/i386/tcg-target.h b/qemu/tcg/i386/tcg-target.h
index d32b8d31..74eaaa45 100644
--- a/qemu/tcg/i386/tcg-target.h
+++ b/qemu/tcg/i386/tcg-target.h
@@ -215,6 +215,7 @@ extern bool have_avx2;
 #define TCG_TARGET_HAS_orc_vec          0
 #define TCG_TARGET_HAS_not_vec          0
 #define TCG_TARGET_HAS_neg_vec          0
+#define TCG_TARGET_HAS_abs_vec          0
 #define TCG_TARGET_HAS_shi_vec          1
 #define TCG_TARGET_HAS_shs_vec          1
 #define TCG_TARGET_HAS_shv_vec          have_avx2
diff --git a/qemu/tcg/tcg-op-gvec.c b/qemu/tcg/tcg-op-gvec.c
index c3c19880..66ccc94f 100644
--- a/qemu/tcg/tcg-op-gvec.c
+++ b/qemu/tcg/tcg-op-gvec.c
@@ -2179,6 +2179,69 @@ void tcg_gen_gvec_neg(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs
     tcg_gen_gvec_2(s, dofs, aofs, oprsz, maxsz, &g[vece]);
 }
 
+static void gen_absv_mask(TCGContext *s, TCGv_i64 d, TCGv_i64 b, unsigned vece)
+{
+    TCGv_i64 t = tcg_temp_new_i64(s);
+    int nbit = 8 << vece;
+
+    /* Create -1 for each negative element.  */
+    tcg_gen_shri_i64(s, t, b, nbit - 1);
+    tcg_gen_andi_i64(s, t, t, dup_const(vece, 1));
+    tcg_gen_muli_i64(s, t, t, (1 << nbit) - 1);
+
+    /*
+     * Invert (via xor -1) and add one (via sub -1).
+     * Because of the ordering the msb is cleared,
+     * so we never have carry into the next element.
+     */
+    tcg_gen_xor_i64(s, d, b, t);
+    tcg_gen_sub_i64(s, d, d, t);
+
+    tcg_temp_free_i64(s, t);
+}
+
+static void tcg_gen_vec_abs8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 b)
+{
+    gen_absv_mask(s, d, b, MO_8);
+}
+
+static void tcg_gen_vec_abs16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 b)
+{
+    gen_absv_mask(s, d, b, MO_16);
+}
+
+void tcg_gen_gvec_abs(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
+                      uint32_t oprsz, uint32_t maxsz)
+{
+    static const TCGOpcode vecop_list[] = { INDEX_op_abs_vec, 0 };
+    static const GVecGen2 g[4] = {
+        { .fni8 = tcg_gen_vec_abs8_i64,
+          .fniv = tcg_gen_abs_vec,
+          .fno = gen_helper_gvec_abs8,
+          .opt_opc = vecop_list,
+          .vece = MO_8 },
+        { .fni8 = tcg_gen_vec_abs16_i64,
+          .fniv = tcg_gen_abs_vec,
+          .fno = gen_helper_gvec_abs16,
+          .opt_opc = vecop_list,
+          .vece = MO_16 },
+        { .fni4 = tcg_gen_abs_i32,
+          .fniv = tcg_gen_abs_vec,
+          .fno = gen_helper_gvec_abs32,
+          .opt_opc = vecop_list,
+          .vece = MO_32 },
+        { .fni8 = tcg_gen_abs_i64,
+          .fniv = tcg_gen_abs_vec,
+          .fno = gen_helper_gvec_abs64,
+          .opt_opc = vecop_list,
+          .prefer_i64 = TCG_TARGET_REG_BITS == 64,
+          .vece = MO_64 },
+    };
+
+    tcg_debug_assert(vece <= MO_64);
+    tcg_gen_gvec_2(s, dofs, aofs, oprsz, maxsz, &g[vece]);
+}
+
 void tcg_gen_gvec_and(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
                       uint32_t bofs, uint32_t oprsz, uint32_t maxsz)
 {
diff --git a/qemu/tcg/tcg-op-gvec.h b/qemu/tcg/tcg-op-gvec.h
index ab0daaed..86977903 100644
--- a/qemu/tcg/tcg-op-gvec.h
+++ b/qemu/tcg/tcg-op-gvec.h
@@ -228,6 +228,8 @@ void tcg_gen_gvec_not(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
                       uint32_t oprsz, uint32_t maxsz);
 void tcg_gen_gvec_neg(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
                       uint32_t oprsz, uint32_t maxsz);
+void tcg_gen_gvec_abs(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
+                      uint32_t oprsz, uint32_t maxsz);
 
 void tcg_gen_gvec_add(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs,
                       uint32_t bofs, uint32_t oprsz, uint32_t maxsz);
diff --git a/qemu/tcg/tcg-op-vec.c b/qemu/tcg/tcg-op-vec.c
index e9be941c..97b74ef7 100644
--- a/qemu/tcg/tcg-op-vec.c
+++ b/qemu/tcg/tcg-op-vec.c
@@ -111,6 +111,14 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list,
                 continue;
             }
             break;
+        case INDEX_op_abs_vec:
+            if (tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece)
+                && (tcg_can_emit_vec_op(INDEX_op_smax_vec, type, vece) > 0
+                    || tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0
+                    || tcg_can_emit_vec_op(INDEX_op_cmp_vec, type, vece))) {
+                continue;
+            }
+            break;
         default:
             break;
         }
@@ -434,6 +442,37 @@ void tcg_gen_neg_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a)
     tcg_swap_vecop_list(s, hold_list);
 }
 
+void tcg_gen_abs_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a)
+{
+    const TCGOpcode *hold_list;
+
+    tcg_assert_listed_vecop(s, INDEX_op_abs_vec);
+    hold_list = tcg_swap_vecop_list(s, NULL);
+
+    if (!do_op2(s, vece, r, a, INDEX_op_abs_vec)) {
+        TCGType type = tcgv_vec_temp(s, r)->base_type;
+        TCGv_vec t = tcg_temp_new_vec(s, type);
+
+        tcg_debug_assert(tcg_can_emit_vec_op(INDEX_op_sub_vec, type, vece));
+        if (tcg_can_emit_vec_op(INDEX_op_smax_vec, type, vece) > 0) {
+            tcg_gen_neg_vec(s, vece, t, a);
+            tcg_gen_smax_vec(s, vece, r, a, t);
+        } else {
+            if (tcg_can_emit_vec_op(INDEX_op_sari_vec, type, vece) > 0) {
+                tcg_gen_sari_vec(s, vece, t, a, (8 << vece) - 1);
+            } else {
+                do_dupi_vec(s, t, MO_REG, 0);
+                tcg_gen_cmp_vec(s, TCG_COND_LT, vece, t, a, t);
+            }
+            tcg_gen_xor_vec(s, vece, r, a, t);
+            tcg_gen_sub_vec(s, vece, r, r, t);
+        }
+
+        tcg_temp_free_vec(s, t);
+    }
+    tcg_swap_vecop_list(s, hold_list);
+}
+
 static void do_shifti(TCGContext *s, TCGOpcode opc, unsigned vece,
                       TCGv_vec r, TCGv_vec a, int64_t i)
 {
diff --git a/qemu/tcg/tcg-opc.h b/qemu/tcg/tcg-opc.h
index 09143a23..3306ed67 100644
--- a/qemu/tcg/tcg-opc.h
+++ b/qemu/tcg/tcg-opc.h
@@ -230,6 +230,7 @@ DEF(add_vec, 1, 2, 0, IMPLVEC)
 DEF(sub_vec, 1, 2, 0, IMPLVEC)
 DEF(mul_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_mul_vec))
 DEF(neg_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_neg_vec))
+DEF(abs_vec, 1, 1, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_abs_vec))
 DEF(ssadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
 DEF(usadd_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
 DEF(sssub_vec, 1, 2, 0, IMPLVEC | IMPL(TCG_TARGET_HAS_sat_vec))
diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c
index ff9872aa..acd34eaa 100644
--- a/qemu/tcg/tcg.c
+++ b/qemu/tcg/tcg.c
@@ -1058,6 +1058,8 @@ bool tcg_op_supported(TCGOpcode op)
         return have_vec && TCG_TARGET_HAS_not_vec;
     case INDEX_op_neg_vec:
         return have_vec && TCG_TARGET_HAS_neg_vec;
+    case INDEX_op_abs_vec:
+        return have_vec && TCG_TARGET_HAS_abs_vec;
     case INDEX_op_andc_vec:
         return have_vec && TCG_TARGET_HAS_andc_vec;
     case INDEX_op_orc_vec:
diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h
index 9a1e8726..de1a1a39 100644
--- a/qemu/tcg/tcg.h
+++ b/qemu/tcg/tcg.h
@@ -179,6 +179,7 @@ typedef uint64_t TCGRegSet;
     && !defined(TCG_TARGET_HAS_v128) \
     && !defined(TCG_TARGET_HAS_v256)
 #define TCG_TARGET_MAYBE_vec            0
+#define TCG_TARGET_HAS_abs_vec          0
 #define TCG_TARGET_HAS_neg_vec          0
 #define TCG_TARGET_HAS_not_vec          0
 #define TCG_TARGET_HAS_andc_vec         0
@@ -1175,7 +1176,7 @@ static inline TCGv_ptr tcg_temp_local_new_ptr(TCGContext *s)
 }
 
 // UNICORN: Added
-#define TCG_OP_DEFS_TABLE_SIZE 182
+#define TCG_OP_DEFS_TABLE_SIZE 183
 extern const TCGOpDef tcg_op_defs_org[TCG_OP_DEFS_TABLE_SIZE];
 
 typedef struct TCGTargetOpDef {
diff --git a/qemu/x86_64.h b/qemu/x86_64.h
index da754870..2b5c5d9f 100644
--- a/qemu/x86_64.h
+++ b/qemu/x86_64.h
@@ -1113,6 +1113,10 @@
 #define helper_get_cp_reg64 helper_get_cp_reg64_x86_64
 #define helper_get_r13_banked helper_get_r13_banked_x86_64
 #define helper_get_user_reg helper_get_user_reg_x86_64
+#define helper_gvec_abs8 helper_gvec_abs8_x86_64
+#define helper_gvec_abs16 helper_gvec_abs16_x86_64
+#define helper_gvec_abs32 helper_gvec_abs32_x86_64
+#define helper_gvec_abs64 helper_gvec_abs64_x86_64
 #define helper_gvec_add8 helper_gvec_add8_x86_64
 #define helper_gvec_add16 helper_gvec_add16_x86_64
 #define helper_gvec_add32 helper_gvec_add32_x86_64
@@ -2867,6 +2871,7 @@
 #define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_x86_64
 #define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_x86_64
 #define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_x86_64
+#define tcg_gen_gvec_abs tcg_gen_gvec_abs_x86_64
 #define tcg_gen_gvec_add tcg_gen_gvec_add_x86_64
 #define tcg_gen_gvec_addi tcg_gen_gvec_addi_x86_64
 #define tcg_gen_gvec_adds tcg_gen_gvec_adds_x86_64