From 6eb847234475b3fec5ac9288d9ac7c12be2b18e5 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 21 Mar 2020 17:56:06 -0400 Subject: [PATCH] target/arm: Flush high bits of sve register after AdvSIMD TBL/TBX Writes to AdvSIMD registers flush the bits above 128. Backports commit 263273bc988e677ebadeaf7d0e49f6792a112db5 from qemu --- qemu/target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 69cadeb1..e3a381d8 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -7218,6 +7218,7 @@ static void disas_simd_tb(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_ctx, tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_ctx, tcg_resh); + clear_vec_high(s, true, rd); } /* ZIP/UZP/TRN