From 72dadc6518381ce9276f6368eb5c20bdc27bb01d Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Mon, 5 Mar 2018 00:54:08 -0500 Subject: [PATCH] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index() Now that we have a banked FAULTMASK register and banked exceptions, we can implement the correct check in cpu_mmu_index() for whether the MPU_CTRL.HFNMIENA bit's effect should apply. This bit causes handlers which have requested a negative execution priority to run with the MPU disabled. In v8M the test has to check this for the current security state and so takes account of banking. Backports relevant part of commit 5d4791991d4de12e83d44738417c9e964167b6e8 from qemu --- qemu/target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index df495d0a..686bcabf 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -1451,6 +1451,21 @@ int armv7m_nvic_complete_irq(void *opaque, int irq); * (v8M ARM ARM I_PKLD.) */ int armv7m_nvic_raw_execution_priority(void *opaque); +/** + * armv7m_nvic_neg_prio_requested: return true if the requested execution + * priority is negative for the specified security state. + * @opaque: the NVIC + * @secure: the security state to test + * This corresponds to the pseudocode IsReqExecPriNeg(). + */ +#ifndef CONFIG_USER_ONLY +bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure); +#else +static inline bool armv7m_nvic_neg_prio_requested(void *opaque, bool secure) +{ + return false; +} +#endif /* Interface for defining coprocessor registers. * Registers are defined in tables of arm_cp_reginfo structs