diff --git a/qemu/target/arm/cpu-qom.h b/qemu/target/arm/cpu-qom.h
index bf6e2e7a..b0865c9f 100644
--- a/qemu/target/arm/cpu-qom.h
+++ b/qemu/target/arm/cpu-qom.h
@@ -30,6 +30,8 @@
 #define ARM_CPU_GET_CLASS(uc, obj) \
     OBJECT_GET_CLASS(uc, ARMCPUClass, (obj), TYPE_ARM_CPU)
 
+#define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU
+
 /**
  * ARMCPUClass:
  * @parent_realize: The parent class' realize handler.
diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c
index 4a9d6bd8..576b1eba 100644
--- a/qemu/target/arm/cpu.c
+++ b/qemu/target/arm/cpu.c
@@ -1466,6 +1466,21 @@ static void pxa270c5_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->reset_sctlr = 0x00000078;
 }
 
+#ifndef TARGET_AARCH64
+/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
+ * otherwise, a CPU with as many features enabled as our emulation supports.
+ * The version of '-cpu max' for qemu-system-aarch64 is defined in cpu64.c;
+ * this only needs to handle 32 bits.
+ */
+static void arm_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
+{
+    cortex_a15_initfn(uc, obj, opaque);
+    /* In future we might add feature bits here even if the
+     * real-world A15 doesn't implement them.
+     */
+}
+#endif
+
 #ifdef CONFIG_USER_ONLY
 static void arm_any_initfn(struct uc_struct *uc, Object *obj, void *opaque)
 {
@@ -1530,6 +1545,9 @@ static const ARMCPUInfo arm_cpus[] = {
     { "pxa270-b1",   pxa270b1_initfn },
     { "pxa270-c0",   pxa270c0_initfn },
     { "pxa270-c5",   pxa270c5_initfn },
+#ifndef TARGET_AARCH64
+    { "max",         arm_max_initfn },
+#endif
 #ifdef CONFIG_USER_ONLY
     { "any",         arm_any_initfn },
 #endif
diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c
index 62ff6271..062747bc 100644
--- a/qemu/target/arm/cpu64.c
+++ b/qemu/target/arm/cpu64.c
@@ -190,6 +190,19 @@ static void aarch64_a53_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 }
 
+/* -cpu max: if KVM is enabled, like -cpu host (best possible with this host);
+ * otherwise, a CPU with as many features enabled as our emulation supports.
+ * The version of '-cpu max' for qemu-system-arm is defined in cpu.c;
+ * this only needs to handle 64 bits.
+ */
+static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
+{
+    aarch64_a57_initfn(uc, obj, opaque);
+    /* In future we might add feature bits here even if the
+     * real-world A57 doesn't implement them.
+     */
+}
+
 // Unicorn: enabled for the general use-case as well.
 static void aarch64_any_initfn(struct uc_struct *uc, Object *obj, void *opaque)
 {
@@ -224,6 +237,7 @@ typedef struct ARMCPUInfo {
 static const ARMCPUInfo aarch64_cpus[] = {
     { "cortex-a57",  aarch64_a57_initfn },
     { "cortex-a53",  aarch64_a53_initfn },
+    { "max",         aarch64_max_initfn },
     // Unicorn: enabled for the general use case as well
     { "any",         aarch64_any_initfn },
     { NULL }