From 73f45735354396766a4bfb26d0b96b06e5cf31b2 Mon Sep 17 00:00:00 2001 From: bunnei Date: Wed, 3 Jan 2018 19:41:12 -0500 Subject: [PATCH] aarch64: Add exception syndrome pseudo register. --- include/unicorn/arm64.h | 1 + qemu/target-arm/unicorn_aarch64.c | 3 +++ 2 files changed, 4 insertions(+) diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h index fe46f159..40f76aa1 100644 --- a/include/unicorn/arm64.h +++ b/include/unicorn/arm64.h @@ -284,6 +284,7 @@ typedef enum uc_arm64_reg { UC_ARM64_REG_PC, // program counter register UC_ARM64_REG_CPACR_EL1, + UC_ARM64_REG_ESR, //> thread registers UC_ARM64_REG_TPIDR_EL0, diff --git a/qemu/target-arm/unicorn_aarch64.c b/qemu/target-arm/unicorn_aarch64.c index 76e580b5..45ce2b37 100644 --- a/qemu/target-arm/unicorn_aarch64.c +++ b/qemu/target-arm/unicorn_aarch64.c @@ -79,6 +79,9 @@ int arm64_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int co case UC_ARM64_REG_CPACR_EL1: *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.cp15.c1_coproc; break; + case UC_ARM64_REG_ESR: + *(uint32_t *)value = ARM_CPU(uc, mycpu)->env.exception.syndrome; + break; case UC_ARM64_REG_TPIDR_EL0: *(int64_t *)value = ARM_CPU(uc, mycpu)->env.cp15.tpidr_el0; break;