From 74cbfceb5629053369083e01842df2900da53628 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 21 Mar 2020 17:56:37 -0400 Subject: [PATCH] target/arm: Flush high bits of sve register after AdvSIMD ZIP/UZP/TRN Writes to AdvSIMD registers flush the bits above 128. Backports commit 33649de62e40df0060a1c514574e4ef25c4e52e1 from qemu --- qemu/target/arm/translate-a64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index e3a381d8..8ef9dbef 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -7309,6 +7309,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint32_t insn) tcg_temp_free_i64(tcg_ctx, tcg_resl); write_vec_element(s, tcg_resh, rd, 1, MO_64); tcg_temp_free_i64(tcg_ctx, tcg_resh); + clear_vec_high(s, true, rd); } /*