diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c
index 62df271f..540ead2c 100644
--- a/qemu/target/arm/translate.c
+++ b/qemu/target/arm/translate.c
@@ -8935,6 +8935,8 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
             } else {
                 int address_offset;
                 bool load = insn & (1 << 20);
+                bool wbit = insn & (1 << 21);
+                bool pbit = insn & (1 << 24);
                 bool doubleword = false;
                 /* Misc load/store */
                 rn = (insn >> 16) & 0xf;
@@ -8952,8 +8954,9 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                 }
 
                 addr = load_reg(s, rn);
-                if (insn & (1 << 24))
+                if (pbit) {
                     gen_add_datah_offset(s, insn, 0, addr);
+                }
                 address_offset = 0;
 
                 if (doubleword) {
@@ -9002,10 +9005,10 @@ static void disas_arm_insn(DisasContext *s, unsigned int insn)  // qq
                    ensure correct behavior with overlapping index registers.
                    ldrd with base writeback is is undefined if the
                    destination and index registers overlap.  */
-                if (!(insn & (1 << 24))) {
+                if (!pbit) {
                     gen_add_datah_offset(s, insn, address_offset, addr);
                     store_reg(s, rn, addr);
-                } else if (insn & (1 << 21)) {
+                } else if (wbit) {
                     if (address_offset)
                         tcg_gen_addi_i32(tcg_ctx, addr, addr, address_offset);
                     store_reg(s, rn, addr);