From 76a10fa8e03c4adce4e78413e81735a2d1835b88 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Thu, 4 Mar 2021 17:00:52 -0500 Subject: [PATCH] cpu: Move tlb_fill to tcg_ops Backports e124536f37377cff5d68925d4976ad604d0ebf3a --- qemu/accel/tcg/cputlb.c | 8 ++++---- qemu/include/qom/cpu.h | 21 ++++++++++++--------- qemu/target/arm/cpu.c | 2 +- qemu/target/i386/cpu.c | 2 +- qemu/target/m68k/cpu.c | 2 +- qemu/target/mips/cpu.c | 2 +- qemu/target/riscv/cpu.c | 4 ++-- qemu/target/sparc/cpu.c | 2 +- 8 files changed, 23 insertions(+), 20 deletions(-) diff --git a/qemu/accel/tcg/cputlb.c b/qemu/accel/tcg/cputlb.c index a3782915..6e443628 100644 --- a/qemu/accel/tcg/cputlb.c +++ b/qemu/accel/tcg/cputlb.c @@ -500,7 +500,7 @@ static void tlb_fill(CPUState *cpu, target_ulong addr, int size, * This is not a probe, so only valid return is success; failure * should result in exception + longjmp to the cpu loop. */ - ok = cc->tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr); + ok = cc->tcg_ops.tlb_fill(cpu, addr, size, access_type, mmu_idx, false, retaddr); assert(ok); } @@ -738,8 +738,8 @@ static int probe_access_internal(CPUArchState *env, target_ulong addr, CPUState *cs = env_cpu(env); CPUClass *cc = CPU_GET_CLASS(cs->uc, cs); - if (!cc->tlb_fill(cs, addr, fault_size, access_type, - mmu_idx, nonfault, retaddr)) { + if (!cc->tcg_ops.tlb_fill(cs, addr, fault_size, access_type, + mmu_idx, nonfault, retaddr)) { /* Non-faulting page table read failed. */ *phost = NULL; return TLB_INVALID_MASK; @@ -882,7 +882,7 @@ void *tlb_vaddr_to_host(CPUArchState *env, abi_ptr addr, CPUState *cs = env_cpu(env); CPUClass *cc = CPU_GET_CLASS(cs->uc, cs); - if (!cc->tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) { + if (!cc->tcg_ops.tlb_fill(cs, addr, 0, access_type, mmu_idx, true, 0)) { /* Non-faulting page table read failed. */ return NULL; } diff --git a/qemu/include/qom/cpu.h b/qemu/include/qom/cpu.h index f571c637..4af038ea 100644 --- a/qemu/include/qom/cpu.h +++ b/qemu/include/qom/cpu.h @@ -104,6 +104,18 @@ typedef struct TcgCpuOperations { void (*cpu_exec_exit)(CPUState *cpu); /** @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec */ bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); + /** + * @tlb_fill: Handle a softmmu tlb miss or user-only address fault + * + * For system mode, if the access is valid, call tlb_set_page + * and return true; if the access is invalid, and probe is + * true, return false; otherwise raise an exception and do + * not return. For user-only mode, always raise an exception + * and do not return. + */ + bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); } TcgCpuOperations; @@ -136,12 +148,6 @@ typedef struct TcgCpuOperations { * If the target behaviour here is anything other than "set * the PC register to the value passed in" then the target must * also implement the synchronize_from_tb hook. - * @tlb_fill: Callback for handling a softmmu tlb miss or user-only - * address fault. For system mode, if the access is valid, call - * tlb_set_page and return true; if the access is invalid, and - * probe is true, return false; otherwise raise an exception and - * do not return. For user-only mode, always raise an exception - * and do not return. * @get_phys_page_debug: Callback for obtaining a physical address. * @get_phys_page_attrs_debug: Callback for obtaining a physical address and the * associated memory transaction attributes to use for the access. @@ -189,9 +195,6 @@ typedef struct CPUClass { void (*get_memory_mapping)(CPUState *cpu, MemoryMappingList *list, Error **errp); void (*set_pc)(CPUState *cpu, vaddr value); - bool (*tlb_fill)(CPUState *cpu, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); hwaddr (*get_phys_page_debug)(CPUState *cpu, vaddr addr); hwaddr (*get_phys_page_attrs_debug)(CPUState *cpu, vaddr addr, MemTxAttrs *attrs); diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 737da2cd..c2baa507 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -2111,7 +2111,7 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data cc->tcg_ops.initialize = arm_translate_init; cc->tcg_ops.cpu_exec_interrupt = arm_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb = arm_cpu_synchronize_from_tb; - cc->tlb_fill = arm_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill; cc->debug_excp_handler = arm_debug_excp_handler; cc->debug_check_watchpoint = arm_debug_check_watchpoint; cc->do_unaligned_access = arm_cpu_do_unaligned_access; diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c index b8001621..79a5daef 100644 --- a/qemu/target/i386/cpu.c +++ b/qemu/target/i386/cpu.c @@ -5884,12 +5884,12 @@ static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, voi #endif #ifdef CONFIG_TCG cc->tcg_ops.initialize = tcg_x86_init; + cc->tcg_ops.tlb_fill = x86_cpu_tlb_fill; cc->tcg_ops.synchronize_from_tb = x86_cpu_synchronize_from_tb; cc->tcg_ops.cpu_exec_enter = x86_cpu_exec_enter; cc->tcg_ops.cpu_exec_exit = x86_cpu_exec_exit; cc->tcg_ops.cpu_exec_interrupt = x86_cpu_exec_interrupt; cc->do_interrupt = x86_cpu_do_interrupt; - cc->tlb_fill = x86_cpu_tlb_fill; #endif #if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) cc->debug_excp_handler = breakpoint_handler; diff --git a/qemu/target/m68k/cpu.c b/qemu/target/m68k/cpu.c index 10f4ec89..1742b901 100644 --- a/qemu/target/m68k/cpu.c +++ b/qemu/target/m68k/cpu.c @@ -268,7 +268,7 @@ static void m68k_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data cc->do_interrupt = m68k_cpu_do_interrupt; cc->tcg_ops.cpu_exec_interrupt = m68k_cpu_exec_interrupt; cc->set_pc = m68k_cpu_set_pc; - cc->tlb_fill = m68k_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = m68k_cpu_tlb_fill; #if defined(CONFIG_SOFTMMU) cc->do_transaction_failed = m68k_cpu_transaction_failed; cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; diff --git a/qemu/target/mips/cpu.c b/qemu/target/mips/cpu.c index 5e3debc1..069d83c8 100644 --- a/qemu/target/mips/cpu.c +++ b/qemu/target/mips/cpu.c @@ -184,7 +184,7 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data cc->tcg_ops.initialize = mips_tcg_init; cc->tcg_ops.cpu_exec_interrupt = mips_cpu_exec_interrupt; cc->tcg_ops.synchronize_from_tb = mips_cpu_synchronize_from_tb; - cc->tlb_fill = mips_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill; #endif } diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c index e474893f..5de31e4a 100644 --- a/qemu/target/riscv/cpu.c +++ b/qemu/target/riscv/cpu.c @@ -358,7 +358,7 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da cc->class_by_name = riscv_cpu_class_by_name; cc->has_work = riscv_cpu_has_work; cc->do_interrupt = riscv_cpu_do_interrupt; - cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; + cc->tcg_ops.cpu_exec_interrupt = riscv_cpu_exec_interrupt; //cc->dump_state = riscv_cpu_dump_state; cc->set_pc = riscv_cpu_set_pc; cc->tcg_ops.synchronize_from_tb = riscv_cpu_synchronize_from_tb; @@ -373,7 +373,7 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; #endif cc->tcg_ops.initialize = riscv_translate_init; - cc->tlb_fill = riscv_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = riscv_cpu_tlb_fill; /* For now, mark unmigratable: */ //cc->vmsd = &vmstate_riscv_cpu; } diff --git a/qemu/target/sparc/cpu.c b/qemu/target/sparc/cpu.c index f320a967..d141ebb6 100644 --- a/qemu/target/sparc/cpu.c +++ b/qemu/target/sparc/cpu.c @@ -848,7 +848,7 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da #endif cc->set_pc = sparc_cpu_set_pc; cc->tcg_ops.synchronize_from_tb = sparc_cpu_synchronize_from_tb; - cc->tlb_fill = sparc_cpu_tlb_fill; + cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY cc->do_transaction_failed = sparc_cpu_do_transaction_failed; cc->do_unaligned_access = sparc_cpu_do_unaligned_access;