diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index 1ceab37f..cf0f1bd5 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -5093,8 +5093,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
 }
 
 /*
- * These MULT and MULTU instructions implemented in for example the
- * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
+ * These MULT[U] and MADD[U] instructions implemented in for example
+ * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
  * architectures are special three-operand variants with the syntax
  *
  *     MULT[U][1] rd, rs, rt
@@ -5103,6 +5103,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
  *
  *     (rd, LO, HI) <- rs * rt
  *
+ * and
+ *
+ *     MADD[U]    rd, rs, rt
+ *
+ * such that
+ *
+ *     (rd, LO, HI) <- (LO, HI) + rs * rt
+ *
  * where the low-order 32-bits of the result is placed into both the
  * GPR rd and the special register LO. The high-order 32-bits of the
  * result is placed into the special register HI.
@@ -5160,8 +5168,48 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
             tcg_temp_free_i32(tcg_ctx, t3);
         }
         break;
+    case MMI_OPC_MADD:
+        {
+            TCGv_i64 t2 = tcg_temp_new_i64(tcg_ctx);
+            TCGv_i64 t3 = tcg_temp_new_i64(tcg_ctx);
+
+            tcg_gen_ext_tl_i64(tcg_ctx, t2, t0);
+            tcg_gen_ext_tl_i64(tcg_ctx, t3, t1);
+            tcg_gen_mul_i64(tcg_ctx, t2, t2, t3);
+            tcg_gen_concat_tl_i64(tcg_ctx, t3, tcg_ctx->cpu_LO[acc], tcg_ctx->cpu_HI[acc]);
+            tcg_gen_add_i64(tcg_ctx, t2, t2, t3);
+            tcg_temp_free_i64(tcg_ctx, t3);
+            gen_move_low32(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
+            gen_move_high32(tcg_ctx, tcg_ctx->cpu_HI[acc], t2);
+            if (rd) {
+                gen_move_low32(tcg_ctx, tcg_ctx->cpu_gpr[rd], t2);
+            }
+            tcg_temp_free_i64(tcg_ctx, t2);
+        }
+        break;
+    case MMI_OPC_MADDU:
+        {
+            TCGv_i64 t2 = tcg_temp_new_i64(tcg_ctx);
+            TCGv_i64 t3 = tcg_temp_new_i64(tcg_ctx);
+
+            tcg_gen_ext32u_tl(tcg_ctx, t0, t0);
+            tcg_gen_ext32u_tl(tcg_ctx, t1, t1);
+            tcg_gen_extu_tl_i64(tcg_ctx, t2, t0);
+            tcg_gen_extu_tl_i64(tcg_ctx, t3, t1);
+            tcg_gen_mul_i64(tcg_ctx, t2, t2, t3);
+            tcg_gen_concat_tl_i64(tcg_ctx, t3, tcg_ctx->cpu_LO[acc], tcg_ctx->cpu_HI[acc]);
+            tcg_gen_add_i64(tcg_ctx, t2, t2, t3);
+            tcg_temp_free_i64(tcg_ctx, t3);
+            gen_move_low32(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
+            gen_move_high32(tcg_ctx, tcg_ctx->cpu_HI[acc], t2);
+            if (rd) {
+                gen_move_low32(tcg_ctx, tcg_ctx->cpu_gpr[rd], t2);
+            }
+            tcg_temp_free_i64(tcg_ctx, t2);
+        }
+        break;
     default:
-        MIPS_INVAL("mul TXx9");
+        MIPS_INVAL("mul/madd TXx9");
         generate_exception_end(ctx, EXCP_RI);
         goto out;
     }
@@ -27487,6 +27535,8 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
         break;
     case MMI_OPC_MULT1:
     case MMI_OPC_MULTU1:
+    case MMI_OPC_MADD:
+    case MMI_OPC_MADDU:
         gen_mul_txx9(ctx, opc, rd, rs, rt);
         break;
     case MMI_OPC_DIV1:
@@ -27501,8 +27551,6 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx)
     case MMI_OPC_MFHI1:
         gen_HILO1_tx79(ctx, opc, rd);
         break;
-    case MMI_OPC_MADD:          /* TODO: MMI_OPC_MADD */
-    case MMI_OPC_MADDU:         /* TODO: MMI_OPC_MADDU */
     case MMI_OPC_PLZCW:         /* TODO: MMI_OPC_PLZCW */
     case MMI_OPC_MADD1:         /* TODO: MMI_OPC_MADD1 */
     case MMI_OPC_MADDU1:        /* TODO: MMI_OPC_MADDU1 */