From 770c5616e22de17996aa3f0f23b8bd97b1488243 Mon Sep 17 00:00:00 2001 From: xorstream Date: Sat, 21 Jan 2017 12:28:22 +1100 Subject: [PATCH] Automated leading tab to spaces conversion. --- bindings/java/unicorn_Unicorn.c | 4 +- bindings/msvc/samples/main.c | 100 +- bindings/msvc/unicorn_dynload.c | 26 +- include/unicorn/arm.h | 240 +- include/unicorn/arm64.h | 536 ++-- include/unicorn/m68k.h | 40 +- include/unicorn/mips.h | 370 +-- include/unicorn/platform.h | 34 +- include/unicorn/sparc.h | 190 +- include/unicorn/x86.h | 2784 ++++++++++----------- qemu/accel.c | 14 +- qemu/exec.c | 30 +- qemu/fpu/softfloat.c | 6 +- qemu/glib_compat.c | 38 +- qemu/hw/core/machine.c | 16 +- qemu/hw/core/qdev.c | 32 +- qemu/hw/i386/pc.c | 30 +- qemu/hw/i386/pc_piix.c | 6 +- qemu/hw/intc/apic.c | 18 +- qemu/hw/intc/apic_common.c | 30 +- qemu/hw/mips/cputimer.c | 2 +- qemu/include/elf.h | 2 +- qemu/include/exec/cpu-defs.h | 4 +- qemu/include/exec/exec-all.h | 2 +- qemu/include/exec/memory.h | 16 +- qemu/include/qemu/aes.h | 12 +- qemu/include/qemu/bitops.h | 40 +- qemu/include/qemu/compiler.h | 2 +- qemu/include/qemu/int128.h | 28 +- qemu/include/qemu/timer.h | 4 +- qemu/memory.c | 40 +- qemu/qom/container.c | 2 +- qemu/qom/cpu.c | 22 +- qemu/qom/object.c | 38 +- qemu/softmmu_template.h | 14 +- qemu/target-arm/helper-a64.c | 2 +- qemu/target-arm/helper.c | 98 +- qemu/target-i386/cpu.c | 328 +-- qemu/target-i386/cpu.h | 6 +- qemu/target-i386/fpu_helper.c | 28 +- qemu/target-i386/svm.h | 154 +- qemu/target-i386/svm_helper.c | 20 +- qemu/target-i386/translate.c | 746 +++--- qemu/target-i386/unicorn.c | 168 +- qemu/target-mips/cpu.h | 2 +- qemu/tcg/i386/tcg-target.c | 180 +- qemu/tcg/sparc/tcg-target.c | 30 +- qemu/tcg/sparc/tcg-target.h | 4 +- qemu/tcg/tcg.c | 106 +- qemu/util/bitops.c | 4 +- samples/mem_apis.c | 6 +- samples/sample_arm.c | 4 +- samples/sample_arm64.c | 4 +- samples/sample_m68k.c | 4 +- samples/sample_mips.c | 4 +- samples/sample_sparc.c | 4 +- samples/sample_x86.c | 2 +- samples/shellcode.c | 2 +- tests/regress/memleak_arm.c | 2 +- tests/regress/memleak_arm64.c | 2 +- tests/regress/memleak_m68k.c | 2 +- tests/regress/memleak_mips.c | 2 +- tests/regress/memleak_sparc.c | 2 +- tests/regress/memleak_x86.c | 2 +- tests/regress/mips_delay_slot_code_hook.c | 94 +- tests/regress/threaded_emu_start.c | 208 +- tests/unit/test_hang.c | 116 +- tests/unit/test_x86_shl_enter_leave.c | 548 ++-- uc.c | 22 +- 69 files changed, 3839 insertions(+), 3839 deletions(-) diff --git a/bindings/java/unicorn_Unicorn.c b/bindings/java/unicorn_Unicorn.c index b5690882..ccf335f2 100644 --- a/bindings/java/unicorn_Unicorn.c +++ b/bindings/java/unicorn_Unicorn.c @@ -334,7 +334,7 @@ JNIEXPORT jlong JNICALL Java_unicorn_Unicorn_open */ JNIEXPORT jint JNICALL Java_unicorn_Unicorn_version (JNIEnv *env, jclass clz) { - return (jint)uc_version(NULL, NULL); + return (jint)uc_version(NULL, NULL); } /* @@ -344,7 +344,7 @@ JNIEXPORT jint JNICALL Java_unicorn_Unicorn_version */ JNIEXPORT jboolean JNICALL Java_unicorn_Unicorn_arch_1supported (JNIEnv *env, jclass clz, jint arch) { - return (jboolean)(uc_arch_supported((uc_arch)arch) != 0); + return (jboolean)(uc_arch_supported((uc_arch)arch) != 0); } /* diff --git a/bindings/msvc/samples/main.c b/bindings/msvc/samples/main.c index 3d3f109d..9fc27bb6 100644 --- a/bindings/msvc/samples/main.c +++ b/bindings/msvc/samples/main.c @@ -31,11 +31,11 @@ // It should loop 3 times before ending. const uint64_t addr = 0x100000; const unsigned char loop_test_code[] = { - 0x02,0x00,0x04,0x24, // 100000: li $a0, 2 - // loop1 - 0x00,0x00,0x00,0x00, // 100004: nop - 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 - 0xFF,0xFF,0x84,0x24, // 10000C: addiu $a0, -1 + 0x02,0x00,0x04,0x24, // 100000: li $a0, 2 + // loop1 + 0x00,0x00,0x00,0x00, // 100004: nop + 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 + 0xFF,0xFF,0x84,0x24, // 10000C: addiu $a0, -1 }; bool test_passed_ok = false; int loop_count = 0; @@ -43,14 +43,14 @@ int loop_count = 0; static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) { - if( address == 0x10000C ) - test_passed_ok = true; - if( address == 0x100004 ) - { - printf("\nloop %d:\n", loop_count); - loop_count++; - } - printf("Code: %llX\n", address); + if( address == 0x10000C ) + test_passed_ok = true; + if( address == 0x100004 ) + { + printf("\nloop %d:\n", loop_count); + loop_count++; + } + printf("Code: %llX\n", address); } @@ -58,76 +58,76 @@ int main(int argc, char **argv, char **envp) { uc_engine *uc; uc_err err; - uc_hook hhc; - uint32_t val; + uc_hook hhc; + uint32_t val; - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD - if( !uc_dyn_load(NULL, 0) ) - { - printf("Error dynamically loading shared library.\n"); - printf("Please check that unicorn.dll/unicorn.so is available as well as\n"); - printf("any other dependent dll/so files.\n"); - printf("The easiest way is to place them in the same directory as this app.\n"); - return 1; - } + if( !uc_dyn_load(NULL, 0) ) + { + printf("Error dynamically loading shared library.\n"); + printf("Please check that unicorn.dll/unicorn.so is available as well as\n"); + printf("any other dependent dll/so files.\n"); + printf("The easiest way is to place them in the same directory as this app.\n"); + return 1; + } #endif - // Initialize emulator in MIPS 32bit little endian mode + // Initialize emulator in MIPS 32bit little endian mode err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32 | UC_MODE_LITTLE_ENDIAN, &uc); if (err) - { + { printf("Failed on uc_open() with error returned: %u\n", err); return err; } - // map in a page of mem - err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); + // map in a page of mem + err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); if (err) - { + { printf("Failed on uc_mem_map() with error returned: %u\n", err); return err; } - // write machine code to be emulated to memory + // write machine code to be emulated to memory err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code)); - if( err ) - { + if( err ) + { printf("Failed on uc_mem_write() with error returned: %u\n", err); return err; } - + // hook all instructions by having @begin > @end uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, (uint64_t)1, (uint64_t)0); - if( err ) - { + if( err ) + { printf("Failed on uc_hook_add(code) with error returned: %u\n", err); return err; } - + // execute code - printf("---- Executing Code ----\n"); - err = uc_emu_start(uc, addr, addr + sizeof(loop_test_code), 0, 0); + printf("---- Executing Code ----\n"); + err = uc_emu_start(uc, addr, addr + sizeof(loop_test_code), 0, 0); if (err) - { + { printf("Failed on uc_emu_start() with error returned %u: %s\n", err, uc_strerror(err)); - return err; + return err; } - // done executing, print some reg values as a test - printf("---- Execution Complete ----\n\n"); - uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); - uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); - - // free resources - uc_close(uc); - - // dynamically free shared library + // done executing, print some reg values as a test + printf("---- Execution Complete ----\n\n"); + uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); + uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); + + // free resources + uc_close(uc); + + // dynamically free shared library #ifdef DYNLOAD uc_dyn_free(); #endif - return 0; + return 0; } diff --git a/bindings/msvc/unicorn_dynload.c b/bindings/msvc/unicorn_dynload.c index fa9c71e8..f7c4ea96 100644 --- a/bindings/msvc/unicorn_dynload.c +++ b/bindings/msvc/unicorn_dynload.c @@ -154,12 +154,12 @@ bool uc_dyn_load(const char* path, int flags) gp_uc_mem_protect = (uc_mem_protect_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_mem_protect"); gp_uc_mem_regions = (uc_mem_regions_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_mem_regions"); gp_uc_context_alloc = (uc_context_alloc_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_alloc"); - gp_uc_context_save = (uc_context_save_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_save"); - gp_uc_context_restore = (uc_context_restore_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_restore"); - gp_uc_free = (uc_free_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_free"); + gp_uc_context_save = (uc_context_save_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_save"); + gp_uc_context_restore = (uc_context_restore_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_restore"); + gp_uc_free = (uc_free_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_free"); - //support old compiled dlls - if(gp_uc_free==0) gp_uc_free = (uc_free_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_free"); + //support old compiled dlls + if(gp_uc_free==0) gp_uc_free = (uc_free_t)DYNLOAD_GETFUNC(g_dyn_handle, "uc_context_free"); return true; } @@ -194,10 +194,10 @@ bool uc_dyn_free(void) gp_uc_mem_unmap = NULL; gp_uc_mem_protect = NULL; gp_uc_mem_regions = NULL; - gp_uc_context_alloc = NULL; - gp_uc_context_save = NULL; - gp_uc_context_restore = NULL; - gp_uc_free = NULL; + gp_uc_context_alloc = NULL; + gp_uc_context_save = NULL; + gp_uc_context_restore = NULL; + gp_uc_free = NULL; return true; } @@ -350,20 +350,20 @@ uc_err uc_mem_regions(uc_engine *uc, uc_mem_region **regions, uint32_t *count) } uc_err uc_context_alloc(uc_engine *uc, uc_context **context){ - return gp_uc_context_alloc(uc,context); + return gp_uc_context_alloc(uc,context); } uc_err uc_context_save(uc_engine *uc, uc_context *context) { - return gp_uc_context_save(uc,context); + return gp_uc_context_save(uc,context); } uc_err uc_context_restore(uc_engine *uc, uc_context *context){ - return gp_uc_context_restore(uc,context); + return gp_uc_context_restore(uc,context); } uc_err uc_free(void *mem){ - return gp_uc_free(mem); + return gp_uc_free(mem); } diff --git a/include/unicorn/arm.h b/include/unicorn/arm.h index 783e418f..1572615d 100644 --- a/include/unicorn/arm.h +++ b/include/unicorn/arm.h @@ -14,129 +14,129 @@ extern "C" { //> ARM registers typedef enum uc_arm_reg { - UC_ARM_REG_INVALID = 0, - UC_ARM_REG_APSR, - UC_ARM_REG_APSR_NZCV, - UC_ARM_REG_CPSR, - UC_ARM_REG_FPEXC, - UC_ARM_REG_FPINST, - UC_ARM_REG_FPSCR, - UC_ARM_REG_FPSCR_NZCV, - UC_ARM_REG_FPSID, - UC_ARM_REG_ITSTATE, - UC_ARM_REG_LR, - UC_ARM_REG_PC, - UC_ARM_REG_SP, - UC_ARM_REG_SPSR, - UC_ARM_REG_D0, - UC_ARM_REG_D1, - UC_ARM_REG_D2, - UC_ARM_REG_D3, - UC_ARM_REG_D4, - UC_ARM_REG_D5, - UC_ARM_REG_D6, - UC_ARM_REG_D7, - UC_ARM_REG_D8, - UC_ARM_REG_D9, - UC_ARM_REG_D10, - UC_ARM_REG_D11, - UC_ARM_REG_D12, - UC_ARM_REG_D13, - UC_ARM_REG_D14, - UC_ARM_REG_D15, - UC_ARM_REG_D16, - UC_ARM_REG_D17, - UC_ARM_REG_D18, - UC_ARM_REG_D19, - UC_ARM_REG_D20, - UC_ARM_REG_D21, - UC_ARM_REG_D22, - UC_ARM_REG_D23, - UC_ARM_REG_D24, - UC_ARM_REG_D25, - UC_ARM_REG_D26, - UC_ARM_REG_D27, - UC_ARM_REG_D28, - UC_ARM_REG_D29, - UC_ARM_REG_D30, - UC_ARM_REG_D31, - UC_ARM_REG_FPINST2, - UC_ARM_REG_MVFR0, - UC_ARM_REG_MVFR1, - UC_ARM_REG_MVFR2, - UC_ARM_REG_Q0, - UC_ARM_REG_Q1, - UC_ARM_REG_Q2, - UC_ARM_REG_Q3, - UC_ARM_REG_Q4, - UC_ARM_REG_Q5, - UC_ARM_REG_Q6, - UC_ARM_REG_Q7, - UC_ARM_REG_Q8, - UC_ARM_REG_Q9, - UC_ARM_REG_Q10, - UC_ARM_REG_Q11, - UC_ARM_REG_Q12, - UC_ARM_REG_Q13, - UC_ARM_REG_Q14, - UC_ARM_REG_Q15, - UC_ARM_REG_R0, - UC_ARM_REG_R1, - UC_ARM_REG_R2, - UC_ARM_REG_R3, - UC_ARM_REG_R4, - UC_ARM_REG_R5, - UC_ARM_REG_R6, - UC_ARM_REG_R7, - UC_ARM_REG_R8, - UC_ARM_REG_R9, - UC_ARM_REG_R10, - UC_ARM_REG_R11, - UC_ARM_REG_R12, - UC_ARM_REG_S0, - UC_ARM_REG_S1, - UC_ARM_REG_S2, - UC_ARM_REG_S3, - UC_ARM_REG_S4, - UC_ARM_REG_S5, - UC_ARM_REG_S6, - UC_ARM_REG_S7, - UC_ARM_REG_S8, - UC_ARM_REG_S9, - UC_ARM_REG_S10, - UC_ARM_REG_S11, - UC_ARM_REG_S12, - UC_ARM_REG_S13, - UC_ARM_REG_S14, - UC_ARM_REG_S15, - UC_ARM_REG_S16, - UC_ARM_REG_S17, - UC_ARM_REG_S18, - UC_ARM_REG_S19, - UC_ARM_REG_S20, - UC_ARM_REG_S21, - UC_ARM_REG_S22, - UC_ARM_REG_S23, - UC_ARM_REG_S24, - UC_ARM_REG_S25, - UC_ARM_REG_S26, - UC_ARM_REG_S27, - UC_ARM_REG_S28, - UC_ARM_REG_S29, - UC_ARM_REG_S30, - UC_ARM_REG_S31, + UC_ARM_REG_INVALID = 0, + UC_ARM_REG_APSR, + UC_ARM_REG_APSR_NZCV, + UC_ARM_REG_CPSR, + UC_ARM_REG_FPEXC, + UC_ARM_REG_FPINST, + UC_ARM_REG_FPSCR, + UC_ARM_REG_FPSCR_NZCV, + UC_ARM_REG_FPSID, + UC_ARM_REG_ITSTATE, + UC_ARM_REG_LR, + UC_ARM_REG_PC, + UC_ARM_REG_SP, + UC_ARM_REG_SPSR, + UC_ARM_REG_D0, + UC_ARM_REG_D1, + UC_ARM_REG_D2, + UC_ARM_REG_D3, + UC_ARM_REG_D4, + UC_ARM_REG_D5, + UC_ARM_REG_D6, + UC_ARM_REG_D7, + UC_ARM_REG_D8, + UC_ARM_REG_D9, + UC_ARM_REG_D10, + UC_ARM_REG_D11, + UC_ARM_REG_D12, + UC_ARM_REG_D13, + UC_ARM_REG_D14, + UC_ARM_REG_D15, + UC_ARM_REG_D16, + UC_ARM_REG_D17, + UC_ARM_REG_D18, + UC_ARM_REG_D19, + UC_ARM_REG_D20, + UC_ARM_REG_D21, + UC_ARM_REG_D22, + UC_ARM_REG_D23, + UC_ARM_REG_D24, + UC_ARM_REG_D25, + UC_ARM_REG_D26, + UC_ARM_REG_D27, + UC_ARM_REG_D28, + UC_ARM_REG_D29, + UC_ARM_REG_D30, + UC_ARM_REG_D31, + UC_ARM_REG_FPINST2, + UC_ARM_REG_MVFR0, + UC_ARM_REG_MVFR1, + UC_ARM_REG_MVFR2, + UC_ARM_REG_Q0, + UC_ARM_REG_Q1, + UC_ARM_REG_Q2, + UC_ARM_REG_Q3, + UC_ARM_REG_Q4, + UC_ARM_REG_Q5, + UC_ARM_REG_Q6, + UC_ARM_REG_Q7, + UC_ARM_REG_Q8, + UC_ARM_REG_Q9, + UC_ARM_REG_Q10, + UC_ARM_REG_Q11, + UC_ARM_REG_Q12, + UC_ARM_REG_Q13, + UC_ARM_REG_Q14, + UC_ARM_REG_Q15, + UC_ARM_REG_R0, + UC_ARM_REG_R1, + UC_ARM_REG_R2, + UC_ARM_REG_R3, + UC_ARM_REG_R4, + UC_ARM_REG_R5, + UC_ARM_REG_R6, + UC_ARM_REG_R7, + UC_ARM_REG_R8, + UC_ARM_REG_R9, + UC_ARM_REG_R10, + UC_ARM_REG_R11, + UC_ARM_REG_R12, + UC_ARM_REG_S0, + UC_ARM_REG_S1, + UC_ARM_REG_S2, + UC_ARM_REG_S3, + UC_ARM_REG_S4, + UC_ARM_REG_S5, + UC_ARM_REG_S6, + UC_ARM_REG_S7, + UC_ARM_REG_S8, + UC_ARM_REG_S9, + UC_ARM_REG_S10, + UC_ARM_REG_S11, + UC_ARM_REG_S12, + UC_ARM_REG_S13, + UC_ARM_REG_S14, + UC_ARM_REG_S15, + UC_ARM_REG_S16, + UC_ARM_REG_S17, + UC_ARM_REG_S18, + UC_ARM_REG_S19, + UC_ARM_REG_S20, + UC_ARM_REG_S21, + UC_ARM_REG_S22, + UC_ARM_REG_S23, + UC_ARM_REG_S24, + UC_ARM_REG_S25, + UC_ARM_REG_S26, + UC_ARM_REG_S27, + UC_ARM_REG_S28, + UC_ARM_REG_S29, + UC_ARM_REG_S30, + UC_ARM_REG_S31, - UC_ARM_REG_ENDING, // <-- mark the end of the list or registers + UC_ARM_REG_ENDING, // <-- mark the end of the list or registers - //> alias registers - UC_ARM_REG_R13 = UC_ARM_REG_SP, - UC_ARM_REG_R14 = UC_ARM_REG_LR, - UC_ARM_REG_R15 = UC_ARM_REG_PC, + //> alias registers + UC_ARM_REG_R13 = UC_ARM_REG_SP, + UC_ARM_REG_R14 = UC_ARM_REG_LR, + UC_ARM_REG_R15 = UC_ARM_REG_PC, - UC_ARM_REG_SB = UC_ARM_REG_R9, - UC_ARM_REG_SL = UC_ARM_REG_R10, - UC_ARM_REG_FP = UC_ARM_REG_R11, - UC_ARM_REG_IP = UC_ARM_REG_R12, + UC_ARM_REG_SB = UC_ARM_REG_R9, + UC_ARM_REG_SL = UC_ARM_REG_R10, + UC_ARM_REG_FP = UC_ARM_REG_R11, + UC_ARM_REG_IP = UC_ARM_REG_R12, } uc_arm_reg; #ifdef __cplusplus diff --git a/include/unicorn/arm64.h b/include/unicorn/arm64.h index 6f58c300..12619abc 100644 --- a/include/unicorn/arm64.h +++ b/include/unicorn/arm64.h @@ -14,280 +14,280 @@ extern "C" { //> ARM64 registers typedef enum uc_arm64_reg { - UC_ARM64_REG_INVALID = 0, + UC_ARM64_REG_INVALID = 0, - UC_ARM64_REG_X29, - UC_ARM64_REG_X30, - UC_ARM64_REG_NZCV, - UC_ARM64_REG_SP, - UC_ARM64_REG_WSP, - UC_ARM64_REG_WZR, - UC_ARM64_REG_XZR, - UC_ARM64_REG_B0, - UC_ARM64_REG_B1, - UC_ARM64_REG_B2, - UC_ARM64_REG_B3, - UC_ARM64_REG_B4, - UC_ARM64_REG_B5, - UC_ARM64_REG_B6, - UC_ARM64_REG_B7, - UC_ARM64_REG_B8, - UC_ARM64_REG_B9, - UC_ARM64_REG_B10, - UC_ARM64_REG_B11, - UC_ARM64_REG_B12, - UC_ARM64_REG_B13, - UC_ARM64_REG_B14, - UC_ARM64_REG_B15, - UC_ARM64_REG_B16, - UC_ARM64_REG_B17, - UC_ARM64_REG_B18, - UC_ARM64_REG_B19, - UC_ARM64_REG_B20, - UC_ARM64_REG_B21, - UC_ARM64_REG_B22, - UC_ARM64_REG_B23, - UC_ARM64_REG_B24, - UC_ARM64_REG_B25, - UC_ARM64_REG_B26, - UC_ARM64_REG_B27, - UC_ARM64_REG_B28, - UC_ARM64_REG_B29, - UC_ARM64_REG_B30, - UC_ARM64_REG_B31, - UC_ARM64_REG_D0, - UC_ARM64_REG_D1, - UC_ARM64_REG_D2, - UC_ARM64_REG_D3, - UC_ARM64_REG_D4, - UC_ARM64_REG_D5, - UC_ARM64_REG_D6, - UC_ARM64_REG_D7, - UC_ARM64_REG_D8, - UC_ARM64_REG_D9, - UC_ARM64_REG_D10, - UC_ARM64_REG_D11, - UC_ARM64_REG_D12, - UC_ARM64_REG_D13, - UC_ARM64_REG_D14, - UC_ARM64_REG_D15, - UC_ARM64_REG_D16, - UC_ARM64_REG_D17, - UC_ARM64_REG_D18, - UC_ARM64_REG_D19, - UC_ARM64_REG_D20, - UC_ARM64_REG_D21, - UC_ARM64_REG_D22, - UC_ARM64_REG_D23, - UC_ARM64_REG_D24, - UC_ARM64_REG_D25, - UC_ARM64_REG_D26, - UC_ARM64_REG_D27, - UC_ARM64_REG_D28, - UC_ARM64_REG_D29, - UC_ARM64_REG_D30, - UC_ARM64_REG_D31, - UC_ARM64_REG_H0, - UC_ARM64_REG_H1, - UC_ARM64_REG_H2, - UC_ARM64_REG_H3, - UC_ARM64_REG_H4, - UC_ARM64_REG_H5, - UC_ARM64_REG_H6, - UC_ARM64_REG_H7, - UC_ARM64_REG_H8, - UC_ARM64_REG_H9, - UC_ARM64_REG_H10, - UC_ARM64_REG_H11, - UC_ARM64_REG_H12, - UC_ARM64_REG_H13, - UC_ARM64_REG_H14, - UC_ARM64_REG_H15, - UC_ARM64_REG_H16, - UC_ARM64_REG_H17, - UC_ARM64_REG_H18, - UC_ARM64_REG_H19, - UC_ARM64_REG_H20, - UC_ARM64_REG_H21, - UC_ARM64_REG_H22, - UC_ARM64_REG_H23, - UC_ARM64_REG_H24, - UC_ARM64_REG_H25, - UC_ARM64_REG_H26, - UC_ARM64_REG_H27, - UC_ARM64_REG_H28, - UC_ARM64_REG_H29, - UC_ARM64_REG_H30, - UC_ARM64_REG_H31, - UC_ARM64_REG_Q0, - UC_ARM64_REG_Q1, - UC_ARM64_REG_Q2, - UC_ARM64_REG_Q3, - UC_ARM64_REG_Q4, - UC_ARM64_REG_Q5, - UC_ARM64_REG_Q6, - UC_ARM64_REG_Q7, - UC_ARM64_REG_Q8, - UC_ARM64_REG_Q9, - UC_ARM64_REG_Q10, - UC_ARM64_REG_Q11, - UC_ARM64_REG_Q12, - UC_ARM64_REG_Q13, - UC_ARM64_REG_Q14, - UC_ARM64_REG_Q15, - UC_ARM64_REG_Q16, - UC_ARM64_REG_Q17, - UC_ARM64_REG_Q18, - UC_ARM64_REG_Q19, - UC_ARM64_REG_Q20, - UC_ARM64_REG_Q21, - UC_ARM64_REG_Q22, - UC_ARM64_REG_Q23, - UC_ARM64_REG_Q24, - UC_ARM64_REG_Q25, - UC_ARM64_REG_Q26, - UC_ARM64_REG_Q27, - UC_ARM64_REG_Q28, - UC_ARM64_REG_Q29, - UC_ARM64_REG_Q30, - UC_ARM64_REG_Q31, - UC_ARM64_REG_S0, - UC_ARM64_REG_S1, - UC_ARM64_REG_S2, - UC_ARM64_REG_S3, - UC_ARM64_REG_S4, - UC_ARM64_REG_S5, - UC_ARM64_REG_S6, - UC_ARM64_REG_S7, - UC_ARM64_REG_S8, - UC_ARM64_REG_S9, - UC_ARM64_REG_S10, - UC_ARM64_REG_S11, - UC_ARM64_REG_S12, - UC_ARM64_REG_S13, - UC_ARM64_REG_S14, - UC_ARM64_REG_S15, - UC_ARM64_REG_S16, - UC_ARM64_REG_S17, - UC_ARM64_REG_S18, - UC_ARM64_REG_S19, - UC_ARM64_REG_S20, - UC_ARM64_REG_S21, - UC_ARM64_REG_S22, - UC_ARM64_REG_S23, - UC_ARM64_REG_S24, - UC_ARM64_REG_S25, - UC_ARM64_REG_S26, - UC_ARM64_REG_S27, - UC_ARM64_REG_S28, - UC_ARM64_REG_S29, - UC_ARM64_REG_S30, - UC_ARM64_REG_S31, - UC_ARM64_REG_W0, - UC_ARM64_REG_W1, - UC_ARM64_REG_W2, - UC_ARM64_REG_W3, - UC_ARM64_REG_W4, - UC_ARM64_REG_W5, - UC_ARM64_REG_W6, - UC_ARM64_REG_W7, - UC_ARM64_REG_W8, - UC_ARM64_REG_W9, - UC_ARM64_REG_W10, - UC_ARM64_REG_W11, - UC_ARM64_REG_W12, - UC_ARM64_REG_W13, - UC_ARM64_REG_W14, - UC_ARM64_REG_W15, - UC_ARM64_REG_W16, - UC_ARM64_REG_W17, - UC_ARM64_REG_W18, - UC_ARM64_REG_W19, - UC_ARM64_REG_W20, - UC_ARM64_REG_W21, - UC_ARM64_REG_W22, - UC_ARM64_REG_W23, - UC_ARM64_REG_W24, - UC_ARM64_REG_W25, - UC_ARM64_REG_W26, - UC_ARM64_REG_W27, - UC_ARM64_REG_W28, - UC_ARM64_REG_W29, - UC_ARM64_REG_W30, - UC_ARM64_REG_X0, - UC_ARM64_REG_X1, - UC_ARM64_REG_X2, - UC_ARM64_REG_X3, - UC_ARM64_REG_X4, - UC_ARM64_REG_X5, - UC_ARM64_REG_X6, - UC_ARM64_REG_X7, - UC_ARM64_REG_X8, - UC_ARM64_REG_X9, - UC_ARM64_REG_X10, - UC_ARM64_REG_X11, - UC_ARM64_REG_X12, - UC_ARM64_REG_X13, - UC_ARM64_REG_X14, - UC_ARM64_REG_X15, - UC_ARM64_REG_X16, - UC_ARM64_REG_X17, - UC_ARM64_REG_X18, - UC_ARM64_REG_X19, - UC_ARM64_REG_X20, - UC_ARM64_REG_X21, - UC_ARM64_REG_X22, - UC_ARM64_REG_X23, - UC_ARM64_REG_X24, - UC_ARM64_REG_X25, - UC_ARM64_REG_X26, - UC_ARM64_REG_X27, - UC_ARM64_REG_X28, + UC_ARM64_REG_X29, + UC_ARM64_REG_X30, + UC_ARM64_REG_NZCV, + UC_ARM64_REG_SP, + UC_ARM64_REG_WSP, + UC_ARM64_REG_WZR, + UC_ARM64_REG_XZR, + UC_ARM64_REG_B0, + UC_ARM64_REG_B1, + UC_ARM64_REG_B2, + UC_ARM64_REG_B3, + UC_ARM64_REG_B4, + UC_ARM64_REG_B5, + UC_ARM64_REG_B6, + UC_ARM64_REG_B7, + UC_ARM64_REG_B8, + UC_ARM64_REG_B9, + UC_ARM64_REG_B10, + UC_ARM64_REG_B11, + UC_ARM64_REG_B12, + UC_ARM64_REG_B13, + UC_ARM64_REG_B14, + UC_ARM64_REG_B15, + UC_ARM64_REG_B16, + UC_ARM64_REG_B17, + UC_ARM64_REG_B18, + UC_ARM64_REG_B19, + UC_ARM64_REG_B20, + UC_ARM64_REG_B21, + UC_ARM64_REG_B22, + UC_ARM64_REG_B23, + UC_ARM64_REG_B24, + UC_ARM64_REG_B25, + UC_ARM64_REG_B26, + UC_ARM64_REG_B27, + UC_ARM64_REG_B28, + UC_ARM64_REG_B29, + UC_ARM64_REG_B30, + UC_ARM64_REG_B31, + UC_ARM64_REG_D0, + UC_ARM64_REG_D1, + UC_ARM64_REG_D2, + UC_ARM64_REG_D3, + UC_ARM64_REG_D4, + UC_ARM64_REG_D5, + UC_ARM64_REG_D6, + UC_ARM64_REG_D7, + UC_ARM64_REG_D8, + UC_ARM64_REG_D9, + UC_ARM64_REG_D10, + UC_ARM64_REG_D11, + UC_ARM64_REG_D12, + UC_ARM64_REG_D13, + UC_ARM64_REG_D14, + UC_ARM64_REG_D15, + UC_ARM64_REG_D16, + UC_ARM64_REG_D17, + UC_ARM64_REG_D18, + UC_ARM64_REG_D19, + UC_ARM64_REG_D20, + UC_ARM64_REG_D21, + UC_ARM64_REG_D22, + UC_ARM64_REG_D23, + UC_ARM64_REG_D24, + UC_ARM64_REG_D25, + UC_ARM64_REG_D26, + UC_ARM64_REG_D27, + UC_ARM64_REG_D28, + UC_ARM64_REG_D29, + UC_ARM64_REG_D30, + UC_ARM64_REG_D31, + UC_ARM64_REG_H0, + UC_ARM64_REG_H1, + UC_ARM64_REG_H2, + UC_ARM64_REG_H3, + UC_ARM64_REG_H4, + UC_ARM64_REG_H5, + UC_ARM64_REG_H6, + UC_ARM64_REG_H7, + UC_ARM64_REG_H8, + UC_ARM64_REG_H9, + UC_ARM64_REG_H10, + UC_ARM64_REG_H11, + UC_ARM64_REG_H12, + UC_ARM64_REG_H13, + UC_ARM64_REG_H14, + UC_ARM64_REG_H15, + UC_ARM64_REG_H16, + UC_ARM64_REG_H17, + UC_ARM64_REG_H18, + UC_ARM64_REG_H19, + UC_ARM64_REG_H20, + UC_ARM64_REG_H21, + UC_ARM64_REG_H22, + UC_ARM64_REG_H23, + UC_ARM64_REG_H24, + UC_ARM64_REG_H25, + UC_ARM64_REG_H26, + UC_ARM64_REG_H27, + UC_ARM64_REG_H28, + UC_ARM64_REG_H29, + UC_ARM64_REG_H30, + UC_ARM64_REG_H31, + UC_ARM64_REG_Q0, + UC_ARM64_REG_Q1, + UC_ARM64_REG_Q2, + UC_ARM64_REG_Q3, + UC_ARM64_REG_Q4, + UC_ARM64_REG_Q5, + UC_ARM64_REG_Q6, + UC_ARM64_REG_Q7, + UC_ARM64_REG_Q8, + UC_ARM64_REG_Q9, + UC_ARM64_REG_Q10, + UC_ARM64_REG_Q11, + UC_ARM64_REG_Q12, + UC_ARM64_REG_Q13, + UC_ARM64_REG_Q14, + UC_ARM64_REG_Q15, + UC_ARM64_REG_Q16, + UC_ARM64_REG_Q17, + UC_ARM64_REG_Q18, + UC_ARM64_REG_Q19, + UC_ARM64_REG_Q20, + UC_ARM64_REG_Q21, + UC_ARM64_REG_Q22, + UC_ARM64_REG_Q23, + UC_ARM64_REG_Q24, + UC_ARM64_REG_Q25, + UC_ARM64_REG_Q26, + UC_ARM64_REG_Q27, + UC_ARM64_REG_Q28, + UC_ARM64_REG_Q29, + UC_ARM64_REG_Q30, + UC_ARM64_REG_Q31, + UC_ARM64_REG_S0, + UC_ARM64_REG_S1, + UC_ARM64_REG_S2, + UC_ARM64_REG_S3, + UC_ARM64_REG_S4, + UC_ARM64_REG_S5, + UC_ARM64_REG_S6, + UC_ARM64_REG_S7, + UC_ARM64_REG_S8, + UC_ARM64_REG_S9, + UC_ARM64_REG_S10, + UC_ARM64_REG_S11, + UC_ARM64_REG_S12, + UC_ARM64_REG_S13, + UC_ARM64_REG_S14, + UC_ARM64_REG_S15, + UC_ARM64_REG_S16, + UC_ARM64_REG_S17, + UC_ARM64_REG_S18, + UC_ARM64_REG_S19, + UC_ARM64_REG_S20, + UC_ARM64_REG_S21, + UC_ARM64_REG_S22, + UC_ARM64_REG_S23, + UC_ARM64_REG_S24, + UC_ARM64_REG_S25, + UC_ARM64_REG_S26, + UC_ARM64_REG_S27, + UC_ARM64_REG_S28, + UC_ARM64_REG_S29, + UC_ARM64_REG_S30, + UC_ARM64_REG_S31, + UC_ARM64_REG_W0, + UC_ARM64_REG_W1, + UC_ARM64_REG_W2, + UC_ARM64_REG_W3, + UC_ARM64_REG_W4, + UC_ARM64_REG_W5, + UC_ARM64_REG_W6, + UC_ARM64_REG_W7, + UC_ARM64_REG_W8, + UC_ARM64_REG_W9, + UC_ARM64_REG_W10, + UC_ARM64_REG_W11, + UC_ARM64_REG_W12, + UC_ARM64_REG_W13, + UC_ARM64_REG_W14, + UC_ARM64_REG_W15, + UC_ARM64_REG_W16, + UC_ARM64_REG_W17, + UC_ARM64_REG_W18, + UC_ARM64_REG_W19, + UC_ARM64_REG_W20, + UC_ARM64_REG_W21, + UC_ARM64_REG_W22, + UC_ARM64_REG_W23, + UC_ARM64_REG_W24, + UC_ARM64_REG_W25, + UC_ARM64_REG_W26, + UC_ARM64_REG_W27, + UC_ARM64_REG_W28, + UC_ARM64_REG_W29, + UC_ARM64_REG_W30, + UC_ARM64_REG_X0, + UC_ARM64_REG_X1, + UC_ARM64_REG_X2, + UC_ARM64_REG_X3, + UC_ARM64_REG_X4, + UC_ARM64_REG_X5, + UC_ARM64_REG_X6, + UC_ARM64_REG_X7, + UC_ARM64_REG_X8, + UC_ARM64_REG_X9, + UC_ARM64_REG_X10, + UC_ARM64_REG_X11, + UC_ARM64_REG_X12, + UC_ARM64_REG_X13, + UC_ARM64_REG_X14, + UC_ARM64_REG_X15, + UC_ARM64_REG_X16, + UC_ARM64_REG_X17, + UC_ARM64_REG_X18, + UC_ARM64_REG_X19, + UC_ARM64_REG_X20, + UC_ARM64_REG_X21, + UC_ARM64_REG_X22, + UC_ARM64_REG_X23, + UC_ARM64_REG_X24, + UC_ARM64_REG_X25, + UC_ARM64_REG_X26, + UC_ARM64_REG_X27, + UC_ARM64_REG_X28, - UC_ARM64_REG_V0, - UC_ARM64_REG_V1, - UC_ARM64_REG_V2, - UC_ARM64_REG_V3, - UC_ARM64_REG_V4, - UC_ARM64_REG_V5, - UC_ARM64_REG_V6, - UC_ARM64_REG_V7, - UC_ARM64_REG_V8, - UC_ARM64_REG_V9, - UC_ARM64_REG_V10, - UC_ARM64_REG_V11, - UC_ARM64_REG_V12, - UC_ARM64_REG_V13, - UC_ARM64_REG_V14, - UC_ARM64_REG_V15, - UC_ARM64_REG_V16, - UC_ARM64_REG_V17, - UC_ARM64_REG_V18, - UC_ARM64_REG_V19, - UC_ARM64_REG_V20, - UC_ARM64_REG_V21, - UC_ARM64_REG_V22, - UC_ARM64_REG_V23, - UC_ARM64_REG_V24, - UC_ARM64_REG_V25, - UC_ARM64_REG_V26, - UC_ARM64_REG_V27, - UC_ARM64_REG_V28, - UC_ARM64_REG_V29, - UC_ARM64_REG_V30, - UC_ARM64_REG_V31, + UC_ARM64_REG_V0, + UC_ARM64_REG_V1, + UC_ARM64_REG_V2, + UC_ARM64_REG_V3, + UC_ARM64_REG_V4, + UC_ARM64_REG_V5, + UC_ARM64_REG_V6, + UC_ARM64_REG_V7, + UC_ARM64_REG_V8, + UC_ARM64_REG_V9, + UC_ARM64_REG_V10, + UC_ARM64_REG_V11, + UC_ARM64_REG_V12, + UC_ARM64_REG_V13, + UC_ARM64_REG_V14, + UC_ARM64_REG_V15, + UC_ARM64_REG_V16, + UC_ARM64_REG_V17, + UC_ARM64_REG_V18, + UC_ARM64_REG_V19, + UC_ARM64_REG_V20, + UC_ARM64_REG_V21, + UC_ARM64_REG_V22, + UC_ARM64_REG_V23, + UC_ARM64_REG_V24, + UC_ARM64_REG_V25, + UC_ARM64_REG_V26, + UC_ARM64_REG_V27, + UC_ARM64_REG_V28, + UC_ARM64_REG_V29, + UC_ARM64_REG_V30, + UC_ARM64_REG_V31, - //> pseudo registers - UC_ARM64_REG_PC, // program counter register + //> pseudo registers + UC_ARM64_REG_PC, // program counter register - UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers + UC_ARM64_REG_ENDING, // <-- mark the end of the list of registers - //> alias registers + //> alias registers - UC_ARM64_REG_IP1 = UC_ARM64_REG_X16, - UC_ARM64_REG_IP0 = UC_ARM64_REG_X17, - UC_ARM64_REG_FP = UC_ARM64_REG_X29, - UC_ARM64_REG_LR = UC_ARM64_REG_X30, + UC_ARM64_REG_IP1 = UC_ARM64_REG_X16, + UC_ARM64_REG_IP0 = UC_ARM64_REG_X17, + UC_ARM64_REG_FP = UC_ARM64_REG_X29, + UC_ARM64_REG_LR = UC_ARM64_REG_X30, } uc_arm64_reg; #ifdef __cplusplus diff --git a/include/unicorn/m68k.h b/include/unicorn/m68k.h index 97c5575c..9f4d39d0 100644 --- a/include/unicorn/m68k.h +++ b/include/unicorn/m68k.h @@ -16,30 +16,30 @@ extern "C" { //> M68K registers typedef enum uc_m68k_reg { - UC_M68K_REG_INVALID = 0, + UC_M68K_REG_INVALID = 0, - UC_M68K_REG_A0, - UC_M68K_REG_A1, - UC_M68K_REG_A2, - UC_M68K_REG_A3, - UC_M68K_REG_A4, - UC_M68K_REG_A5, - UC_M68K_REG_A6, - UC_M68K_REG_A7, + UC_M68K_REG_A0, + UC_M68K_REG_A1, + UC_M68K_REG_A2, + UC_M68K_REG_A3, + UC_M68K_REG_A4, + UC_M68K_REG_A5, + UC_M68K_REG_A6, + UC_M68K_REG_A7, - UC_M68K_REG_D0, - UC_M68K_REG_D1, - UC_M68K_REG_D2, - UC_M68K_REG_D3, - UC_M68K_REG_D4, - UC_M68K_REG_D5, - UC_M68K_REG_D6, - UC_M68K_REG_D7, + UC_M68K_REG_D0, + UC_M68K_REG_D1, + UC_M68K_REG_D2, + UC_M68K_REG_D3, + UC_M68K_REG_D4, + UC_M68K_REG_D5, + UC_M68K_REG_D6, + UC_M68K_REG_D7, - UC_M68K_REG_SR, - UC_M68K_REG_PC, + UC_M68K_REG_SR, + UC_M68K_REG_PC, - UC_M68K_REG_ENDING, // <-- mark the end of the list of registers + UC_M68K_REG_ENDING, // <-- mark the end of the list of registers } uc_m68k_reg; #ifdef __cplusplus diff --git a/include/unicorn/mips.h b/include/unicorn/mips.h index d7072a95..e97468cd 100644 --- a/include/unicorn/mips.h +++ b/include/unicorn/mips.h @@ -18,205 +18,205 @@ extern "C" { //> MIPS registers typedef enum UC_MIPS_REG { - UC_MIPS_REG_INVALID = 0, - //> General purpose registers - UC_MIPS_REG_PC, + UC_MIPS_REG_INVALID = 0, + //> General purpose registers + UC_MIPS_REG_PC, - UC_MIPS_REG_0, - UC_MIPS_REG_1, - UC_MIPS_REG_2, - UC_MIPS_REG_3, - UC_MIPS_REG_4, - UC_MIPS_REG_5, - UC_MIPS_REG_6, - UC_MIPS_REG_7, - UC_MIPS_REG_8, - UC_MIPS_REG_9, - UC_MIPS_REG_10, - UC_MIPS_REG_11, - UC_MIPS_REG_12, - UC_MIPS_REG_13, - UC_MIPS_REG_14, - UC_MIPS_REG_15, - UC_MIPS_REG_16, - UC_MIPS_REG_17, - UC_MIPS_REG_18, - UC_MIPS_REG_19, - UC_MIPS_REG_20, - UC_MIPS_REG_21, - UC_MIPS_REG_22, - UC_MIPS_REG_23, - UC_MIPS_REG_24, - UC_MIPS_REG_25, - UC_MIPS_REG_26, - UC_MIPS_REG_27, - UC_MIPS_REG_28, - UC_MIPS_REG_29, - UC_MIPS_REG_30, - UC_MIPS_REG_31, + UC_MIPS_REG_0, + UC_MIPS_REG_1, + UC_MIPS_REG_2, + UC_MIPS_REG_3, + UC_MIPS_REG_4, + UC_MIPS_REG_5, + UC_MIPS_REG_6, + UC_MIPS_REG_7, + UC_MIPS_REG_8, + UC_MIPS_REG_9, + UC_MIPS_REG_10, + UC_MIPS_REG_11, + UC_MIPS_REG_12, + UC_MIPS_REG_13, + UC_MIPS_REG_14, + UC_MIPS_REG_15, + UC_MIPS_REG_16, + UC_MIPS_REG_17, + UC_MIPS_REG_18, + UC_MIPS_REG_19, + UC_MIPS_REG_20, + UC_MIPS_REG_21, + UC_MIPS_REG_22, + UC_MIPS_REG_23, + UC_MIPS_REG_24, + UC_MIPS_REG_25, + UC_MIPS_REG_26, + UC_MIPS_REG_27, + UC_MIPS_REG_28, + UC_MIPS_REG_29, + UC_MIPS_REG_30, + UC_MIPS_REG_31, - //> DSP registers - UC_MIPS_REG_DSPCCOND, - UC_MIPS_REG_DSPCARRY, - UC_MIPS_REG_DSPEFI, - UC_MIPS_REG_DSPOUTFLAG, - UC_MIPS_REG_DSPOUTFLAG16_19, - UC_MIPS_REG_DSPOUTFLAG20, - UC_MIPS_REG_DSPOUTFLAG21, - UC_MIPS_REG_DSPOUTFLAG22, - UC_MIPS_REG_DSPOUTFLAG23, - UC_MIPS_REG_DSPPOS, - UC_MIPS_REG_DSPSCOUNT, + //> DSP registers + UC_MIPS_REG_DSPCCOND, + UC_MIPS_REG_DSPCARRY, + UC_MIPS_REG_DSPEFI, + UC_MIPS_REG_DSPOUTFLAG, + UC_MIPS_REG_DSPOUTFLAG16_19, + UC_MIPS_REG_DSPOUTFLAG20, + UC_MIPS_REG_DSPOUTFLAG21, + UC_MIPS_REG_DSPOUTFLAG22, + UC_MIPS_REG_DSPOUTFLAG23, + UC_MIPS_REG_DSPPOS, + UC_MIPS_REG_DSPSCOUNT, - //> ACC registers - UC_MIPS_REG_AC0, - UC_MIPS_REG_AC1, - UC_MIPS_REG_AC2, - UC_MIPS_REG_AC3, + //> ACC registers + UC_MIPS_REG_AC0, + UC_MIPS_REG_AC1, + UC_MIPS_REG_AC2, + UC_MIPS_REG_AC3, - //> COP registers - UC_MIPS_REG_CC0, - UC_MIPS_REG_CC1, - UC_MIPS_REG_CC2, - UC_MIPS_REG_CC3, - UC_MIPS_REG_CC4, - UC_MIPS_REG_CC5, - UC_MIPS_REG_CC6, - UC_MIPS_REG_CC7, + //> COP registers + UC_MIPS_REG_CC0, + UC_MIPS_REG_CC1, + UC_MIPS_REG_CC2, + UC_MIPS_REG_CC3, + UC_MIPS_REG_CC4, + UC_MIPS_REG_CC5, + UC_MIPS_REG_CC6, + UC_MIPS_REG_CC7, - //> FPU registers - UC_MIPS_REG_F0, - UC_MIPS_REG_F1, - UC_MIPS_REG_F2, - UC_MIPS_REG_F3, - UC_MIPS_REG_F4, - UC_MIPS_REG_F5, - UC_MIPS_REG_F6, - UC_MIPS_REG_F7, - UC_MIPS_REG_F8, - UC_MIPS_REG_F9, - UC_MIPS_REG_F10, - UC_MIPS_REG_F11, - UC_MIPS_REG_F12, - UC_MIPS_REG_F13, - UC_MIPS_REG_F14, - UC_MIPS_REG_F15, - UC_MIPS_REG_F16, - UC_MIPS_REG_F17, - UC_MIPS_REG_F18, - UC_MIPS_REG_F19, - UC_MIPS_REG_F20, - UC_MIPS_REG_F21, - UC_MIPS_REG_F22, - UC_MIPS_REG_F23, - UC_MIPS_REG_F24, - UC_MIPS_REG_F25, - UC_MIPS_REG_F26, - UC_MIPS_REG_F27, - UC_MIPS_REG_F28, - UC_MIPS_REG_F29, - UC_MIPS_REG_F30, - UC_MIPS_REG_F31, + //> FPU registers + UC_MIPS_REG_F0, + UC_MIPS_REG_F1, + UC_MIPS_REG_F2, + UC_MIPS_REG_F3, + UC_MIPS_REG_F4, + UC_MIPS_REG_F5, + UC_MIPS_REG_F6, + UC_MIPS_REG_F7, + UC_MIPS_REG_F8, + UC_MIPS_REG_F9, + UC_MIPS_REG_F10, + UC_MIPS_REG_F11, + UC_MIPS_REG_F12, + UC_MIPS_REG_F13, + UC_MIPS_REG_F14, + UC_MIPS_REG_F15, + UC_MIPS_REG_F16, + UC_MIPS_REG_F17, + UC_MIPS_REG_F18, + UC_MIPS_REG_F19, + UC_MIPS_REG_F20, + UC_MIPS_REG_F21, + UC_MIPS_REG_F22, + UC_MIPS_REG_F23, + UC_MIPS_REG_F24, + UC_MIPS_REG_F25, + UC_MIPS_REG_F26, + UC_MIPS_REG_F27, + UC_MIPS_REG_F28, + UC_MIPS_REG_F29, + UC_MIPS_REG_F30, + UC_MIPS_REG_F31, - UC_MIPS_REG_FCC0, - UC_MIPS_REG_FCC1, - UC_MIPS_REG_FCC2, - UC_MIPS_REG_FCC3, - UC_MIPS_REG_FCC4, - UC_MIPS_REG_FCC5, - UC_MIPS_REG_FCC6, - UC_MIPS_REG_FCC7, + UC_MIPS_REG_FCC0, + UC_MIPS_REG_FCC1, + UC_MIPS_REG_FCC2, + UC_MIPS_REG_FCC3, + UC_MIPS_REG_FCC4, + UC_MIPS_REG_FCC5, + UC_MIPS_REG_FCC6, + UC_MIPS_REG_FCC7, - //> AFPR128 - UC_MIPS_REG_W0, - UC_MIPS_REG_W1, - UC_MIPS_REG_W2, - UC_MIPS_REG_W3, - UC_MIPS_REG_W4, - UC_MIPS_REG_W5, - UC_MIPS_REG_W6, - UC_MIPS_REG_W7, - UC_MIPS_REG_W8, - UC_MIPS_REG_W9, - UC_MIPS_REG_W10, - UC_MIPS_REG_W11, - UC_MIPS_REG_W12, - UC_MIPS_REG_W13, - UC_MIPS_REG_W14, - UC_MIPS_REG_W15, - UC_MIPS_REG_W16, - UC_MIPS_REG_W17, - UC_MIPS_REG_W18, - UC_MIPS_REG_W19, - UC_MIPS_REG_W20, - UC_MIPS_REG_W21, - UC_MIPS_REG_W22, - UC_MIPS_REG_W23, - UC_MIPS_REG_W24, - UC_MIPS_REG_W25, - UC_MIPS_REG_W26, - UC_MIPS_REG_W27, - UC_MIPS_REG_W28, - UC_MIPS_REG_W29, - UC_MIPS_REG_W30, - UC_MIPS_REG_W31, + //> AFPR128 + UC_MIPS_REG_W0, + UC_MIPS_REG_W1, + UC_MIPS_REG_W2, + UC_MIPS_REG_W3, + UC_MIPS_REG_W4, + UC_MIPS_REG_W5, + UC_MIPS_REG_W6, + UC_MIPS_REG_W7, + UC_MIPS_REG_W8, + UC_MIPS_REG_W9, + UC_MIPS_REG_W10, + UC_MIPS_REG_W11, + UC_MIPS_REG_W12, + UC_MIPS_REG_W13, + UC_MIPS_REG_W14, + UC_MIPS_REG_W15, + UC_MIPS_REG_W16, + UC_MIPS_REG_W17, + UC_MIPS_REG_W18, + UC_MIPS_REG_W19, + UC_MIPS_REG_W20, + UC_MIPS_REG_W21, + UC_MIPS_REG_W22, + UC_MIPS_REG_W23, + UC_MIPS_REG_W24, + UC_MIPS_REG_W25, + UC_MIPS_REG_W26, + UC_MIPS_REG_W27, + UC_MIPS_REG_W28, + UC_MIPS_REG_W29, + UC_MIPS_REG_W30, + UC_MIPS_REG_W31, - UC_MIPS_REG_HI, - UC_MIPS_REG_LO, + UC_MIPS_REG_HI, + UC_MIPS_REG_LO, - UC_MIPS_REG_P0, - UC_MIPS_REG_P1, - UC_MIPS_REG_P2, + UC_MIPS_REG_P0, + UC_MIPS_REG_P1, + UC_MIPS_REG_P2, - UC_MIPS_REG_MPL0, - UC_MIPS_REG_MPL1, - UC_MIPS_REG_MPL2, + UC_MIPS_REG_MPL0, + UC_MIPS_REG_MPL1, + UC_MIPS_REG_MPL2, - UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers + UC_MIPS_REG_ENDING, // <-- mark the end of the list or registers - // alias registers - UC_MIPS_REG_ZERO = UC_MIPS_REG_0, - UC_MIPS_REG_AT = UC_MIPS_REG_1, - UC_MIPS_REG_V0 = UC_MIPS_REG_2, - UC_MIPS_REG_V1 = UC_MIPS_REG_3, - UC_MIPS_REG_A0 = UC_MIPS_REG_4, - UC_MIPS_REG_A1 = UC_MIPS_REG_5, - UC_MIPS_REG_A2 = UC_MIPS_REG_6, - UC_MIPS_REG_A3 = UC_MIPS_REG_7, - UC_MIPS_REG_T0 = UC_MIPS_REG_8, - UC_MIPS_REG_T1 = UC_MIPS_REG_9, - UC_MIPS_REG_T2 = UC_MIPS_REG_10, - UC_MIPS_REG_T3 = UC_MIPS_REG_11, - UC_MIPS_REG_T4 = UC_MIPS_REG_12, - UC_MIPS_REG_T5 = UC_MIPS_REG_13, - UC_MIPS_REG_T6 = UC_MIPS_REG_14, - UC_MIPS_REG_T7 = UC_MIPS_REG_15, - UC_MIPS_REG_S0 = UC_MIPS_REG_16, - UC_MIPS_REG_S1 = UC_MIPS_REG_17, - UC_MIPS_REG_S2 = UC_MIPS_REG_18, - UC_MIPS_REG_S3 = UC_MIPS_REG_19, - UC_MIPS_REG_S4 = UC_MIPS_REG_20, - UC_MIPS_REG_S5 = UC_MIPS_REG_21, - UC_MIPS_REG_S6 = UC_MIPS_REG_22, - UC_MIPS_REG_S7 = UC_MIPS_REG_23, - UC_MIPS_REG_T8 = UC_MIPS_REG_24, - UC_MIPS_REG_T9 = UC_MIPS_REG_25, - UC_MIPS_REG_K0 = UC_MIPS_REG_26, - UC_MIPS_REG_K1 = UC_MIPS_REG_27, - UC_MIPS_REG_GP = UC_MIPS_REG_28, - UC_MIPS_REG_SP = UC_MIPS_REG_29, - UC_MIPS_REG_FP = UC_MIPS_REG_30, UC_MIPS_REG_S8 = UC_MIPS_REG_30, - UC_MIPS_REG_RA = UC_MIPS_REG_31, + // alias registers + UC_MIPS_REG_ZERO = UC_MIPS_REG_0, + UC_MIPS_REG_AT = UC_MIPS_REG_1, + UC_MIPS_REG_V0 = UC_MIPS_REG_2, + UC_MIPS_REG_V1 = UC_MIPS_REG_3, + UC_MIPS_REG_A0 = UC_MIPS_REG_4, + UC_MIPS_REG_A1 = UC_MIPS_REG_5, + UC_MIPS_REG_A2 = UC_MIPS_REG_6, + UC_MIPS_REG_A3 = UC_MIPS_REG_7, + UC_MIPS_REG_T0 = UC_MIPS_REG_8, + UC_MIPS_REG_T1 = UC_MIPS_REG_9, + UC_MIPS_REG_T2 = UC_MIPS_REG_10, + UC_MIPS_REG_T3 = UC_MIPS_REG_11, + UC_MIPS_REG_T4 = UC_MIPS_REG_12, + UC_MIPS_REG_T5 = UC_MIPS_REG_13, + UC_MIPS_REG_T6 = UC_MIPS_REG_14, + UC_MIPS_REG_T7 = UC_MIPS_REG_15, + UC_MIPS_REG_S0 = UC_MIPS_REG_16, + UC_MIPS_REG_S1 = UC_MIPS_REG_17, + UC_MIPS_REG_S2 = UC_MIPS_REG_18, + UC_MIPS_REG_S3 = UC_MIPS_REG_19, + UC_MIPS_REG_S4 = UC_MIPS_REG_20, + UC_MIPS_REG_S5 = UC_MIPS_REG_21, + UC_MIPS_REG_S6 = UC_MIPS_REG_22, + UC_MIPS_REG_S7 = UC_MIPS_REG_23, + UC_MIPS_REG_T8 = UC_MIPS_REG_24, + UC_MIPS_REG_T9 = UC_MIPS_REG_25, + UC_MIPS_REG_K0 = UC_MIPS_REG_26, + UC_MIPS_REG_K1 = UC_MIPS_REG_27, + UC_MIPS_REG_GP = UC_MIPS_REG_28, + UC_MIPS_REG_SP = UC_MIPS_REG_29, + UC_MIPS_REG_FP = UC_MIPS_REG_30, UC_MIPS_REG_S8 = UC_MIPS_REG_30, + UC_MIPS_REG_RA = UC_MIPS_REG_31, - UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0, - UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1, - UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2, - UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3, + UC_MIPS_REG_HI0 = UC_MIPS_REG_AC0, + UC_MIPS_REG_HI1 = UC_MIPS_REG_AC1, + UC_MIPS_REG_HI2 = UC_MIPS_REG_AC2, + UC_MIPS_REG_HI3 = UC_MIPS_REG_AC3, - UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0, - UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1, - UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2, - UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3, + UC_MIPS_REG_LO0 = UC_MIPS_REG_HI0, + UC_MIPS_REG_LO1 = UC_MIPS_REG_HI1, + UC_MIPS_REG_LO2 = UC_MIPS_REG_HI2, + UC_MIPS_REG_LO3 = UC_MIPS_REG_HI3, } UC_MIPS_REG; #ifdef __cplusplus diff --git a/include/unicorn/platform.h b/include/unicorn/platform.h index 7bf37e02..38db99d3 100644 --- a/include/unicorn/platform.h +++ b/include/unicorn/platform.h @@ -1,5 +1,5 @@ /* - This file is primarily to support header files that are missing in MSVC and other non-standard compilers. + This file is primarily to support header files that are missing in MSVC and other non-standard compilers. */ #ifndef UNICORN_PLATFORM_H @@ -176,11 +176,11 @@ typedef _W64 unsigned int uintptr_t; static int gettimeofday(struct timeval* t, void* timezone) { - struct _timeb timebuffer; - _ftime( &timebuffer ); - t->tv_sec = (long)timebuffer.time; - t->tv_usec = 1000*timebuffer.millitm; - return 0; + struct _timeb timebuffer; + _ftime( &timebuffer ); + t->tv_sec = (long)timebuffer.time; + t->tv_usec = 1000*timebuffer.millitm; + return 0; } #else @@ -195,22 +195,22 @@ static int gettimeofday(struct timeval* t, void* timezone) // TODO: add unistd stuff here ... static int usleep(uint32_t t) { - int ret, err_code; - long value = t; // time in microseconds - struct timeval tv; - FD_SET dummy_set; - FD_ZERO(&dummy_set); - tv.tv_sec = value / 1000000; - tv.tv_usec = value % 1000000; - ret = select(0, &dummy_set, NULL, NULL, &tv); - err_code = WSAGetLastError(); - return ret==0 ? 0 : -1; + int ret, err_code; + long value = t; // time in microseconds + struct timeval tv; + FD_SET dummy_set; + FD_ZERO(&dummy_set); + tv.tv_sec = value / 1000000; + tv.tv_usec = value % 1000000; + ret = select(0, &dummy_set, NULL, NULL, &tv); + err_code = WSAGetLastError(); + return ret==0 ? 0 : -1; } /* #include #include static void usleep(const int64_t &t) { - std::this_thread::sleep_for(std::chrono::microseconds(t)); + std::this_thread::sleep_for(std::chrono::microseconds(t)); } */ diff --git a/include/unicorn/sparc.h b/include/unicorn/sparc.h index ca607709..4a1acff2 100644 --- a/include/unicorn/sparc.h +++ b/include/unicorn/sparc.h @@ -20,106 +20,106 @@ extern "C" { //> SPARC registers typedef enum uc_sparc_reg { - UC_SPARC_REG_INVALID = 0, + UC_SPARC_REG_INVALID = 0, - UC_SPARC_REG_F0, - UC_SPARC_REG_F1, - UC_SPARC_REG_F2, - UC_SPARC_REG_F3, - UC_SPARC_REG_F4, - UC_SPARC_REG_F5, - UC_SPARC_REG_F6, - UC_SPARC_REG_F7, - UC_SPARC_REG_F8, - UC_SPARC_REG_F9, - UC_SPARC_REG_F10, - UC_SPARC_REG_F11, - UC_SPARC_REG_F12, - UC_SPARC_REG_F13, - UC_SPARC_REG_F14, - UC_SPARC_REG_F15, - UC_SPARC_REG_F16, - UC_SPARC_REG_F17, - UC_SPARC_REG_F18, - UC_SPARC_REG_F19, - UC_SPARC_REG_F20, - UC_SPARC_REG_F21, - UC_SPARC_REG_F22, - UC_SPARC_REG_F23, - UC_SPARC_REG_F24, - UC_SPARC_REG_F25, - UC_SPARC_REG_F26, - UC_SPARC_REG_F27, - UC_SPARC_REG_F28, - UC_SPARC_REG_F29, - UC_SPARC_REG_F30, - UC_SPARC_REG_F31, - UC_SPARC_REG_F32, - UC_SPARC_REG_F34, - UC_SPARC_REG_F36, - UC_SPARC_REG_F38, - UC_SPARC_REG_F40, - UC_SPARC_REG_F42, - UC_SPARC_REG_F44, - UC_SPARC_REG_F46, - UC_SPARC_REG_F48, - UC_SPARC_REG_F50, - UC_SPARC_REG_F52, - UC_SPARC_REG_F54, - UC_SPARC_REG_F56, - UC_SPARC_REG_F58, - UC_SPARC_REG_F60, - UC_SPARC_REG_F62, - UC_SPARC_REG_FCC0, // Floating condition codes - UC_SPARC_REG_FCC1, - UC_SPARC_REG_FCC2, - UC_SPARC_REG_FCC3, - UC_SPARC_REG_G0, - UC_SPARC_REG_G1, - UC_SPARC_REG_G2, - UC_SPARC_REG_G3, - UC_SPARC_REG_G4, - UC_SPARC_REG_G5, - UC_SPARC_REG_G6, - UC_SPARC_REG_G7, - UC_SPARC_REG_I0, - UC_SPARC_REG_I1, - UC_SPARC_REG_I2, - UC_SPARC_REG_I3, - UC_SPARC_REG_I4, - UC_SPARC_REG_I5, - UC_SPARC_REG_FP, - UC_SPARC_REG_I7, - UC_SPARC_REG_ICC, // Integer condition codes - UC_SPARC_REG_L0, - UC_SPARC_REG_L1, - UC_SPARC_REG_L2, - UC_SPARC_REG_L3, - UC_SPARC_REG_L4, - UC_SPARC_REG_L5, - UC_SPARC_REG_L6, - UC_SPARC_REG_L7, - UC_SPARC_REG_O0, - UC_SPARC_REG_O1, - UC_SPARC_REG_O2, - UC_SPARC_REG_O3, - UC_SPARC_REG_O4, - UC_SPARC_REG_O5, - UC_SPARC_REG_SP, - UC_SPARC_REG_O7, - UC_SPARC_REG_Y, + UC_SPARC_REG_F0, + UC_SPARC_REG_F1, + UC_SPARC_REG_F2, + UC_SPARC_REG_F3, + UC_SPARC_REG_F4, + UC_SPARC_REG_F5, + UC_SPARC_REG_F6, + UC_SPARC_REG_F7, + UC_SPARC_REG_F8, + UC_SPARC_REG_F9, + UC_SPARC_REG_F10, + UC_SPARC_REG_F11, + UC_SPARC_REG_F12, + UC_SPARC_REG_F13, + UC_SPARC_REG_F14, + UC_SPARC_REG_F15, + UC_SPARC_REG_F16, + UC_SPARC_REG_F17, + UC_SPARC_REG_F18, + UC_SPARC_REG_F19, + UC_SPARC_REG_F20, + UC_SPARC_REG_F21, + UC_SPARC_REG_F22, + UC_SPARC_REG_F23, + UC_SPARC_REG_F24, + UC_SPARC_REG_F25, + UC_SPARC_REG_F26, + UC_SPARC_REG_F27, + UC_SPARC_REG_F28, + UC_SPARC_REG_F29, + UC_SPARC_REG_F30, + UC_SPARC_REG_F31, + UC_SPARC_REG_F32, + UC_SPARC_REG_F34, + UC_SPARC_REG_F36, + UC_SPARC_REG_F38, + UC_SPARC_REG_F40, + UC_SPARC_REG_F42, + UC_SPARC_REG_F44, + UC_SPARC_REG_F46, + UC_SPARC_REG_F48, + UC_SPARC_REG_F50, + UC_SPARC_REG_F52, + UC_SPARC_REG_F54, + UC_SPARC_REG_F56, + UC_SPARC_REG_F58, + UC_SPARC_REG_F60, + UC_SPARC_REG_F62, + UC_SPARC_REG_FCC0, // Floating condition codes + UC_SPARC_REG_FCC1, + UC_SPARC_REG_FCC2, + UC_SPARC_REG_FCC3, + UC_SPARC_REG_G0, + UC_SPARC_REG_G1, + UC_SPARC_REG_G2, + UC_SPARC_REG_G3, + UC_SPARC_REG_G4, + UC_SPARC_REG_G5, + UC_SPARC_REG_G6, + UC_SPARC_REG_G7, + UC_SPARC_REG_I0, + UC_SPARC_REG_I1, + UC_SPARC_REG_I2, + UC_SPARC_REG_I3, + UC_SPARC_REG_I4, + UC_SPARC_REG_I5, + UC_SPARC_REG_FP, + UC_SPARC_REG_I7, + UC_SPARC_REG_ICC, // Integer condition codes + UC_SPARC_REG_L0, + UC_SPARC_REG_L1, + UC_SPARC_REG_L2, + UC_SPARC_REG_L3, + UC_SPARC_REG_L4, + UC_SPARC_REG_L5, + UC_SPARC_REG_L6, + UC_SPARC_REG_L7, + UC_SPARC_REG_O0, + UC_SPARC_REG_O1, + UC_SPARC_REG_O2, + UC_SPARC_REG_O3, + UC_SPARC_REG_O4, + UC_SPARC_REG_O5, + UC_SPARC_REG_SP, + UC_SPARC_REG_O7, + UC_SPARC_REG_Y, - // special register - UC_SPARC_REG_XCC, + // special register + UC_SPARC_REG_XCC, - // pseudo register - UC_SPARC_REG_PC, // program counter register + // pseudo register + UC_SPARC_REG_PC, // program counter register - UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers + UC_SPARC_REG_ENDING, // <-- mark the end of the list of registers - // extras - UC_SPARC_REG_O6 = UC_SPARC_REG_SP, - UC_SPARC_REG_I6 = UC_SPARC_REG_FP, + // extras + UC_SPARC_REG_O6 = UC_SPARC_REG_SP, + UC_SPARC_REG_I6 = UC_SPARC_REG_FP, } uc_sparc_reg; #ifdef __cplusplus diff --git a/include/unicorn/x86.h b/include/unicorn/x86.h index 3a339d33..c1d560ee 100644 --- a/include/unicorn/x86.h +++ b/include/unicorn/x86.h @@ -25,1405 +25,1405 @@ typedef void (*uc_cb_insn_syscall_t)(struct uc_struct *uc, void *user_data); //> X86 registers typedef enum uc_x86_reg { - UC_X86_REG_INVALID = 0, - UC_X86_REG_AH, UC_X86_REG_AL, UC_X86_REG_AX, UC_X86_REG_BH, UC_X86_REG_BL, - UC_X86_REG_BP, UC_X86_REG_BPL, UC_X86_REG_BX, UC_X86_REG_CH, UC_X86_REG_CL, - UC_X86_REG_CS, UC_X86_REG_CX, UC_X86_REG_DH, UC_X86_REG_DI, UC_X86_REG_DIL, - UC_X86_REG_DL, UC_X86_REG_DS, UC_X86_REG_DX, UC_X86_REG_EAX, UC_X86_REG_EBP, - UC_X86_REG_EBX, UC_X86_REG_ECX, UC_X86_REG_EDI, UC_X86_REG_EDX, UC_X86_REG_EFLAGS, - UC_X86_REG_EIP, UC_X86_REG_EIZ, UC_X86_REG_ES, UC_X86_REG_ESI, UC_X86_REG_ESP, - UC_X86_REG_FPSW, UC_X86_REG_FS, UC_X86_REG_GS, UC_X86_REG_IP, UC_X86_REG_RAX, - UC_X86_REG_RBP, UC_X86_REG_RBX, UC_X86_REG_RCX, UC_X86_REG_RDI, UC_X86_REG_RDX, - UC_X86_REG_RIP, UC_X86_REG_RIZ, UC_X86_REG_RSI, UC_X86_REG_RSP, UC_X86_REG_SI, - UC_X86_REG_SIL, UC_X86_REG_SP, UC_X86_REG_SPL, UC_X86_REG_SS, UC_X86_REG_CR0, - UC_X86_REG_CR1, UC_X86_REG_CR2, UC_X86_REG_CR3, UC_X86_REG_CR4, UC_X86_REG_CR5, - UC_X86_REG_CR6, UC_X86_REG_CR7, UC_X86_REG_CR8, UC_X86_REG_CR9, UC_X86_REG_CR10, - UC_X86_REG_CR11, UC_X86_REG_CR12, UC_X86_REG_CR13, UC_X86_REG_CR14, UC_X86_REG_CR15, - UC_X86_REG_DR0, UC_X86_REG_DR1, UC_X86_REG_DR2, UC_X86_REG_DR3, UC_X86_REG_DR4, - UC_X86_REG_DR5, UC_X86_REG_DR6, UC_X86_REG_DR7, UC_X86_REG_DR8, UC_X86_REG_DR9, - UC_X86_REG_DR10, UC_X86_REG_DR11, UC_X86_REG_DR12, UC_X86_REG_DR13, UC_X86_REG_DR14, - UC_X86_REG_DR15, UC_X86_REG_FP0, UC_X86_REG_FP1, UC_X86_REG_FP2, UC_X86_REG_FP3, - UC_X86_REG_FP4, UC_X86_REG_FP5, UC_X86_REG_FP6, UC_X86_REG_FP7, - UC_X86_REG_K0, UC_X86_REG_K1, UC_X86_REG_K2, UC_X86_REG_K3, UC_X86_REG_K4, - UC_X86_REG_K5, UC_X86_REG_K6, UC_X86_REG_K7, UC_X86_REG_MM0, UC_X86_REG_MM1, - UC_X86_REG_MM2, UC_X86_REG_MM3, UC_X86_REG_MM4, UC_X86_REG_MM5, UC_X86_REG_MM6, - UC_X86_REG_MM7, UC_X86_REG_R8, UC_X86_REG_R9, UC_X86_REG_R10, UC_X86_REG_R11, - UC_X86_REG_R12, UC_X86_REG_R13, UC_X86_REG_R14, UC_X86_REG_R15, - UC_X86_REG_ST0, UC_X86_REG_ST1, UC_X86_REG_ST2, UC_X86_REG_ST3, - UC_X86_REG_ST4, UC_X86_REG_ST5, UC_X86_REG_ST6, UC_X86_REG_ST7, - UC_X86_REG_XMM0, UC_X86_REG_XMM1, UC_X86_REG_XMM2, UC_X86_REG_XMM3, UC_X86_REG_XMM4, - UC_X86_REG_XMM5, UC_X86_REG_XMM6, UC_X86_REG_XMM7, UC_X86_REG_XMM8, UC_X86_REG_XMM9, - UC_X86_REG_XMM10, UC_X86_REG_XMM11, UC_X86_REG_XMM12, UC_X86_REG_XMM13, UC_X86_REG_XMM14, - UC_X86_REG_XMM15, UC_X86_REG_XMM16, UC_X86_REG_XMM17, UC_X86_REG_XMM18, UC_X86_REG_XMM19, - UC_X86_REG_XMM20, UC_X86_REG_XMM21, UC_X86_REG_XMM22, UC_X86_REG_XMM23, UC_X86_REG_XMM24, - UC_X86_REG_XMM25, UC_X86_REG_XMM26, UC_X86_REG_XMM27, UC_X86_REG_XMM28, UC_X86_REG_XMM29, - UC_X86_REG_XMM30, UC_X86_REG_XMM31, UC_X86_REG_YMM0, UC_X86_REG_YMM1, UC_X86_REG_YMM2, - UC_X86_REG_YMM3, UC_X86_REG_YMM4, UC_X86_REG_YMM5, UC_X86_REG_YMM6, UC_X86_REG_YMM7, - UC_X86_REG_YMM8, UC_X86_REG_YMM9, UC_X86_REG_YMM10, UC_X86_REG_YMM11, UC_X86_REG_YMM12, - UC_X86_REG_YMM13, UC_X86_REG_YMM14, UC_X86_REG_YMM15, UC_X86_REG_YMM16, UC_X86_REG_YMM17, - UC_X86_REG_YMM18, UC_X86_REG_YMM19, UC_X86_REG_YMM20, UC_X86_REG_YMM21, UC_X86_REG_YMM22, - UC_X86_REG_YMM23, UC_X86_REG_YMM24, UC_X86_REG_YMM25, UC_X86_REG_YMM26, UC_X86_REG_YMM27, - UC_X86_REG_YMM28, UC_X86_REG_YMM29, UC_X86_REG_YMM30, UC_X86_REG_YMM31, UC_X86_REG_ZMM0, - UC_X86_REG_ZMM1, UC_X86_REG_ZMM2, UC_X86_REG_ZMM3, UC_X86_REG_ZMM4, UC_X86_REG_ZMM5, - UC_X86_REG_ZMM6, UC_X86_REG_ZMM7, UC_X86_REG_ZMM8, UC_X86_REG_ZMM9, UC_X86_REG_ZMM10, - UC_X86_REG_ZMM11, UC_X86_REG_ZMM12, UC_X86_REG_ZMM13, UC_X86_REG_ZMM14, UC_X86_REG_ZMM15, - UC_X86_REG_ZMM16, UC_X86_REG_ZMM17, UC_X86_REG_ZMM18, UC_X86_REG_ZMM19, UC_X86_REG_ZMM20, - UC_X86_REG_ZMM21, UC_X86_REG_ZMM22, UC_X86_REG_ZMM23, UC_X86_REG_ZMM24, UC_X86_REG_ZMM25, - UC_X86_REG_ZMM26, UC_X86_REG_ZMM27, UC_X86_REG_ZMM28, UC_X86_REG_ZMM29, UC_X86_REG_ZMM30, - UC_X86_REG_ZMM31, UC_X86_REG_R8B, UC_X86_REG_R9B, UC_X86_REG_R10B, UC_X86_REG_R11B, - UC_X86_REG_R12B, UC_X86_REG_R13B, UC_X86_REG_R14B, UC_X86_REG_R15B, UC_X86_REG_R8D, - UC_X86_REG_R9D, UC_X86_REG_R10D, UC_X86_REG_R11D, UC_X86_REG_R12D, UC_X86_REG_R13D, - UC_X86_REG_R14D, UC_X86_REG_R15D, UC_X86_REG_R8W, UC_X86_REG_R9W, UC_X86_REG_R10W, - UC_X86_REG_R11W, UC_X86_REG_R12W, UC_X86_REG_R13W, UC_X86_REG_R14W, UC_X86_REG_R15W, - UC_X86_REG_IDTR, UC_X86_REG_GDTR, UC_X86_REG_LDTR, UC_X86_REG_TR, UC_X86_REG_FPCW, - UC_X86_REG_FPTAG, + UC_X86_REG_INVALID = 0, + UC_X86_REG_AH, UC_X86_REG_AL, UC_X86_REG_AX, UC_X86_REG_BH, UC_X86_REG_BL, + UC_X86_REG_BP, UC_X86_REG_BPL, UC_X86_REG_BX, UC_X86_REG_CH, UC_X86_REG_CL, + UC_X86_REG_CS, UC_X86_REG_CX, UC_X86_REG_DH, UC_X86_REG_DI, UC_X86_REG_DIL, + UC_X86_REG_DL, UC_X86_REG_DS, UC_X86_REG_DX, UC_X86_REG_EAX, UC_X86_REG_EBP, + UC_X86_REG_EBX, UC_X86_REG_ECX, UC_X86_REG_EDI, UC_X86_REG_EDX, UC_X86_REG_EFLAGS, + UC_X86_REG_EIP, UC_X86_REG_EIZ, UC_X86_REG_ES, UC_X86_REG_ESI, UC_X86_REG_ESP, + UC_X86_REG_FPSW, UC_X86_REG_FS, UC_X86_REG_GS, UC_X86_REG_IP, UC_X86_REG_RAX, + UC_X86_REG_RBP, UC_X86_REG_RBX, UC_X86_REG_RCX, UC_X86_REG_RDI, UC_X86_REG_RDX, + UC_X86_REG_RIP, UC_X86_REG_RIZ, UC_X86_REG_RSI, UC_X86_REG_RSP, UC_X86_REG_SI, + UC_X86_REG_SIL, UC_X86_REG_SP, UC_X86_REG_SPL, UC_X86_REG_SS, UC_X86_REG_CR0, + UC_X86_REG_CR1, UC_X86_REG_CR2, UC_X86_REG_CR3, UC_X86_REG_CR4, UC_X86_REG_CR5, + UC_X86_REG_CR6, UC_X86_REG_CR7, UC_X86_REG_CR8, UC_X86_REG_CR9, UC_X86_REG_CR10, + UC_X86_REG_CR11, UC_X86_REG_CR12, UC_X86_REG_CR13, UC_X86_REG_CR14, UC_X86_REG_CR15, + UC_X86_REG_DR0, UC_X86_REG_DR1, UC_X86_REG_DR2, UC_X86_REG_DR3, UC_X86_REG_DR4, + UC_X86_REG_DR5, UC_X86_REG_DR6, UC_X86_REG_DR7, UC_X86_REG_DR8, UC_X86_REG_DR9, + UC_X86_REG_DR10, UC_X86_REG_DR11, UC_X86_REG_DR12, UC_X86_REG_DR13, UC_X86_REG_DR14, + UC_X86_REG_DR15, UC_X86_REG_FP0, UC_X86_REG_FP1, UC_X86_REG_FP2, UC_X86_REG_FP3, + UC_X86_REG_FP4, UC_X86_REG_FP5, UC_X86_REG_FP6, UC_X86_REG_FP7, + UC_X86_REG_K0, UC_X86_REG_K1, UC_X86_REG_K2, UC_X86_REG_K3, UC_X86_REG_K4, + UC_X86_REG_K5, UC_X86_REG_K6, UC_X86_REG_K7, UC_X86_REG_MM0, UC_X86_REG_MM1, + UC_X86_REG_MM2, UC_X86_REG_MM3, UC_X86_REG_MM4, UC_X86_REG_MM5, UC_X86_REG_MM6, + UC_X86_REG_MM7, UC_X86_REG_R8, UC_X86_REG_R9, UC_X86_REG_R10, UC_X86_REG_R11, + UC_X86_REG_R12, UC_X86_REG_R13, UC_X86_REG_R14, UC_X86_REG_R15, + UC_X86_REG_ST0, UC_X86_REG_ST1, UC_X86_REG_ST2, UC_X86_REG_ST3, + UC_X86_REG_ST4, UC_X86_REG_ST5, UC_X86_REG_ST6, UC_X86_REG_ST7, + UC_X86_REG_XMM0, UC_X86_REG_XMM1, UC_X86_REG_XMM2, UC_X86_REG_XMM3, UC_X86_REG_XMM4, + UC_X86_REG_XMM5, UC_X86_REG_XMM6, UC_X86_REG_XMM7, UC_X86_REG_XMM8, UC_X86_REG_XMM9, + UC_X86_REG_XMM10, UC_X86_REG_XMM11, UC_X86_REG_XMM12, UC_X86_REG_XMM13, UC_X86_REG_XMM14, + UC_X86_REG_XMM15, UC_X86_REG_XMM16, UC_X86_REG_XMM17, UC_X86_REG_XMM18, UC_X86_REG_XMM19, + UC_X86_REG_XMM20, UC_X86_REG_XMM21, UC_X86_REG_XMM22, UC_X86_REG_XMM23, UC_X86_REG_XMM24, + UC_X86_REG_XMM25, UC_X86_REG_XMM26, UC_X86_REG_XMM27, UC_X86_REG_XMM28, UC_X86_REG_XMM29, + UC_X86_REG_XMM30, UC_X86_REG_XMM31, UC_X86_REG_YMM0, UC_X86_REG_YMM1, UC_X86_REG_YMM2, + UC_X86_REG_YMM3, UC_X86_REG_YMM4, UC_X86_REG_YMM5, UC_X86_REG_YMM6, UC_X86_REG_YMM7, + UC_X86_REG_YMM8, UC_X86_REG_YMM9, UC_X86_REG_YMM10, UC_X86_REG_YMM11, UC_X86_REG_YMM12, + UC_X86_REG_YMM13, UC_X86_REG_YMM14, UC_X86_REG_YMM15, UC_X86_REG_YMM16, UC_X86_REG_YMM17, + UC_X86_REG_YMM18, UC_X86_REG_YMM19, UC_X86_REG_YMM20, UC_X86_REG_YMM21, UC_X86_REG_YMM22, + UC_X86_REG_YMM23, UC_X86_REG_YMM24, UC_X86_REG_YMM25, UC_X86_REG_YMM26, UC_X86_REG_YMM27, + UC_X86_REG_YMM28, UC_X86_REG_YMM29, UC_X86_REG_YMM30, UC_X86_REG_YMM31, UC_X86_REG_ZMM0, + UC_X86_REG_ZMM1, UC_X86_REG_ZMM2, UC_X86_REG_ZMM3, UC_X86_REG_ZMM4, UC_X86_REG_ZMM5, + UC_X86_REG_ZMM6, UC_X86_REG_ZMM7, UC_X86_REG_ZMM8, UC_X86_REG_ZMM9, UC_X86_REG_ZMM10, + UC_X86_REG_ZMM11, UC_X86_REG_ZMM12, UC_X86_REG_ZMM13, UC_X86_REG_ZMM14, UC_X86_REG_ZMM15, + UC_X86_REG_ZMM16, UC_X86_REG_ZMM17, UC_X86_REG_ZMM18, UC_X86_REG_ZMM19, UC_X86_REG_ZMM20, + UC_X86_REG_ZMM21, UC_X86_REG_ZMM22, UC_X86_REG_ZMM23, UC_X86_REG_ZMM24, UC_X86_REG_ZMM25, + UC_X86_REG_ZMM26, UC_X86_REG_ZMM27, UC_X86_REG_ZMM28, UC_X86_REG_ZMM29, UC_X86_REG_ZMM30, + UC_X86_REG_ZMM31, UC_X86_REG_R8B, UC_X86_REG_R9B, UC_X86_REG_R10B, UC_X86_REG_R11B, + UC_X86_REG_R12B, UC_X86_REG_R13B, UC_X86_REG_R14B, UC_X86_REG_R15B, UC_X86_REG_R8D, + UC_X86_REG_R9D, UC_X86_REG_R10D, UC_X86_REG_R11D, UC_X86_REG_R12D, UC_X86_REG_R13D, + UC_X86_REG_R14D, UC_X86_REG_R15D, UC_X86_REG_R8W, UC_X86_REG_R9W, UC_X86_REG_R10W, + UC_X86_REG_R11W, UC_X86_REG_R12W, UC_X86_REG_R13W, UC_X86_REG_R14W, UC_X86_REG_R15W, + UC_X86_REG_IDTR, UC_X86_REG_GDTR, UC_X86_REG_LDTR, UC_X86_REG_TR, UC_X86_REG_FPCW, + UC_X86_REG_FPTAG, - UC_X86_REG_ENDING // <-- mark the end of the list of registers + UC_X86_REG_ENDING // <-- mark the end of the list of registers } uc_x86_reg; //> X86 instructions typedef enum uc_x86_insn { - UC_X86_INS_INVALID = 0, + UC_X86_INS_INVALID = 0, - UC_X86_INS_AAA, - UC_X86_INS_AAD, - UC_X86_INS_AAM, - UC_X86_INS_AAS, - UC_X86_INS_FABS, - UC_X86_INS_ADC, - UC_X86_INS_ADCX, - UC_X86_INS_ADD, - UC_X86_INS_ADDPD, - UC_X86_INS_ADDPS, - UC_X86_INS_ADDSD, - UC_X86_INS_ADDSS, - UC_X86_INS_ADDSUBPD, - UC_X86_INS_ADDSUBPS, - UC_X86_INS_FADD, - UC_X86_INS_FIADD, - UC_X86_INS_FADDP, - UC_X86_INS_ADOX, - UC_X86_INS_AESDECLAST, - UC_X86_INS_AESDEC, - UC_X86_INS_AESENCLAST, - UC_X86_INS_AESENC, - UC_X86_INS_AESIMC, - UC_X86_INS_AESKEYGENASSIST, - UC_X86_INS_AND, - UC_X86_INS_ANDN, - UC_X86_INS_ANDNPD, - UC_X86_INS_ANDNPS, - UC_X86_INS_ANDPD, - UC_X86_INS_ANDPS, - UC_X86_INS_ARPL, - UC_X86_INS_BEXTR, - UC_X86_INS_BLCFILL, - UC_X86_INS_BLCI, - UC_X86_INS_BLCIC, - UC_X86_INS_BLCMSK, - UC_X86_INS_BLCS, - UC_X86_INS_BLENDPD, - UC_X86_INS_BLENDPS, - UC_X86_INS_BLENDVPD, - UC_X86_INS_BLENDVPS, - UC_X86_INS_BLSFILL, - UC_X86_INS_BLSI, - UC_X86_INS_BLSIC, - UC_X86_INS_BLSMSK, - UC_X86_INS_BLSR, - UC_X86_INS_BOUND, - UC_X86_INS_BSF, - UC_X86_INS_BSR, - UC_X86_INS_BSWAP, - UC_X86_INS_BT, - UC_X86_INS_BTC, - UC_X86_INS_BTR, - UC_X86_INS_BTS, - UC_X86_INS_BZHI, - UC_X86_INS_CALL, - UC_X86_INS_CBW, - UC_X86_INS_CDQ, - UC_X86_INS_CDQE, - UC_X86_INS_FCHS, - UC_X86_INS_CLAC, - UC_X86_INS_CLC, - UC_X86_INS_CLD, - UC_X86_INS_CLFLUSH, - UC_X86_INS_CLFLUSHOPT, - UC_X86_INS_CLGI, - UC_X86_INS_CLI, - UC_X86_INS_CLTS, - UC_X86_INS_CLWB, - UC_X86_INS_CMC, - UC_X86_INS_CMOVA, - UC_X86_INS_CMOVAE, - UC_X86_INS_CMOVB, - UC_X86_INS_CMOVBE, - UC_X86_INS_FCMOVBE, - UC_X86_INS_FCMOVB, - UC_X86_INS_CMOVE, - UC_X86_INS_FCMOVE, - UC_X86_INS_CMOVG, - UC_X86_INS_CMOVGE, - UC_X86_INS_CMOVL, - UC_X86_INS_CMOVLE, - UC_X86_INS_FCMOVNBE, - UC_X86_INS_FCMOVNB, - UC_X86_INS_CMOVNE, - UC_X86_INS_FCMOVNE, - UC_X86_INS_CMOVNO, - UC_X86_INS_CMOVNP, - UC_X86_INS_FCMOVNU, - UC_X86_INS_CMOVNS, - UC_X86_INS_CMOVO, - UC_X86_INS_CMOVP, - UC_X86_INS_FCMOVU, - UC_X86_INS_CMOVS, - UC_X86_INS_CMP, - UC_X86_INS_CMPPD, - UC_X86_INS_CMPPS, - UC_X86_INS_CMPSB, - UC_X86_INS_CMPSD, - UC_X86_INS_CMPSQ, - UC_X86_INS_CMPSS, - UC_X86_INS_CMPSW, - UC_X86_INS_CMPXCHG16B, - UC_X86_INS_CMPXCHG, - UC_X86_INS_CMPXCHG8B, - UC_X86_INS_COMISD, - UC_X86_INS_COMISS, - UC_X86_INS_FCOMP, - UC_X86_INS_FCOMPI, - UC_X86_INS_FCOMI, - UC_X86_INS_FCOM, - UC_X86_INS_FCOS, - UC_X86_INS_CPUID, - UC_X86_INS_CQO, - UC_X86_INS_CRC32, - UC_X86_INS_CVTDQ2PD, - UC_X86_INS_CVTDQ2PS, - UC_X86_INS_CVTPD2DQ, - UC_X86_INS_CVTPD2PS, - UC_X86_INS_CVTPS2DQ, - UC_X86_INS_CVTPS2PD, - UC_X86_INS_CVTSD2SI, - UC_X86_INS_CVTSD2SS, - UC_X86_INS_CVTSI2SD, - UC_X86_INS_CVTSI2SS, - UC_X86_INS_CVTSS2SD, - UC_X86_INS_CVTSS2SI, - UC_X86_INS_CVTTPD2DQ, - UC_X86_INS_CVTTPS2DQ, - UC_X86_INS_CVTTSD2SI, - UC_X86_INS_CVTTSS2SI, - UC_X86_INS_CWD, - UC_X86_INS_CWDE, - UC_X86_INS_DAA, - UC_X86_INS_DAS, - UC_X86_INS_DATA16, - UC_X86_INS_DEC, - UC_X86_INS_DIV, - UC_X86_INS_DIVPD, - UC_X86_INS_DIVPS, - UC_X86_INS_FDIVR, - UC_X86_INS_FIDIVR, - UC_X86_INS_FDIVRP, - UC_X86_INS_DIVSD, - UC_X86_INS_DIVSS, - UC_X86_INS_FDIV, - UC_X86_INS_FIDIV, - UC_X86_INS_FDIVP, - UC_X86_INS_DPPD, - UC_X86_INS_DPPS, - UC_X86_INS_RET, - UC_X86_INS_ENCLS, - UC_X86_INS_ENCLU, - UC_X86_INS_ENTER, - UC_X86_INS_EXTRACTPS, - UC_X86_INS_EXTRQ, - UC_X86_INS_F2XM1, - UC_X86_INS_LCALL, - UC_X86_INS_LJMP, - UC_X86_INS_FBLD, - UC_X86_INS_FBSTP, - UC_X86_INS_FCOMPP, - UC_X86_INS_FDECSTP, - UC_X86_INS_FEMMS, - UC_X86_INS_FFREE, - UC_X86_INS_FICOM, - UC_X86_INS_FICOMP, - UC_X86_INS_FINCSTP, - UC_X86_INS_FLDCW, - UC_X86_INS_FLDENV, - UC_X86_INS_FLDL2E, - UC_X86_INS_FLDL2T, - UC_X86_INS_FLDLG2, - UC_X86_INS_FLDLN2, - UC_X86_INS_FLDPI, - UC_X86_INS_FNCLEX, - UC_X86_INS_FNINIT, - UC_X86_INS_FNOP, - UC_X86_INS_FNSTCW, - UC_X86_INS_FNSTSW, - UC_X86_INS_FPATAN, - UC_X86_INS_FPREM, - UC_X86_INS_FPREM1, - UC_X86_INS_FPTAN, - UC_X86_INS_FFREEP, - UC_X86_INS_FRNDINT, - UC_X86_INS_FRSTOR, - UC_X86_INS_FNSAVE, - UC_X86_INS_FSCALE, - UC_X86_INS_FSETPM, - UC_X86_INS_FSINCOS, - UC_X86_INS_FNSTENV, - UC_X86_INS_FXAM, - UC_X86_INS_FXRSTOR, - UC_X86_INS_FXRSTOR64, - UC_X86_INS_FXSAVE, - UC_X86_INS_FXSAVE64, - UC_X86_INS_FXTRACT, - UC_X86_INS_FYL2X, - UC_X86_INS_FYL2XP1, - UC_X86_INS_MOVAPD, - UC_X86_INS_MOVAPS, - UC_X86_INS_ORPD, - UC_X86_INS_ORPS, - UC_X86_INS_VMOVAPD, - UC_X86_INS_VMOVAPS, - UC_X86_INS_XORPD, - UC_X86_INS_XORPS, - UC_X86_INS_GETSEC, - UC_X86_INS_HADDPD, - UC_X86_INS_HADDPS, - UC_X86_INS_HLT, - UC_X86_INS_HSUBPD, - UC_X86_INS_HSUBPS, - UC_X86_INS_IDIV, - UC_X86_INS_FILD, - UC_X86_INS_IMUL, - UC_X86_INS_IN, - UC_X86_INS_INC, - UC_X86_INS_INSB, - UC_X86_INS_INSERTPS, - UC_X86_INS_INSERTQ, - UC_X86_INS_INSD, - UC_X86_INS_INSW, - UC_X86_INS_INT, - UC_X86_INS_INT1, - UC_X86_INS_INT3, - UC_X86_INS_INTO, - UC_X86_INS_INVD, - UC_X86_INS_INVEPT, - UC_X86_INS_INVLPG, - UC_X86_INS_INVLPGA, - UC_X86_INS_INVPCID, - UC_X86_INS_INVVPID, - UC_X86_INS_IRET, - UC_X86_INS_IRETD, - UC_X86_INS_IRETQ, - UC_X86_INS_FISTTP, - UC_X86_INS_FIST, - UC_X86_INS_FISTP, - UC_X86_INS_UCOMISD, - UC_X86_INS_UCOMISS, - UC_X86_INS_VCOMISD, - UC_X86_INS_VCOMISS, - UC_X86_INS_VCVTSD2SS, - UC_X86_INS_VCVTSI2SD, - UC_X86_INS_VCVTSI2SS, - UC_X86_INS_VCVTSS2SD, - UC_X86_INS_VCVTTSD2SI, - UC_X86_INS_VCVTTSD2USI, - UC_X86_INS_VCVTTSS2SI, - UC_X86_INS_VCVTTSS2USI, - UC_X86_INS_VCVTUSI2SD, - UC_X86_INS_VCVTUSI2SS, - UC_X86_INS_VUCOMISD, - UC_X86_INS_VUCOMISS, - UC_X86_INS_JAE, - UC_X86_INS_JA, - UC_X86_INS_JBE, - UC_X86_INS_JB, - UC_X86_INS_JCXZ, - UC_X86_INS_JECXZ, - UC_X86_INS_JE, - UC_X86_INS_JGE, - UC_X86_INS_JG, - UC_X86_INS_JLE, - UC_X86_INS_JL, - UC_X86_INS_JMP, - UC_X86_INS_JNE, - UC_X86_INS_JNO, - UC_X86_INS_JNP, - UC_X86_INS_JNS, - UC_X86_INS_JO, - UC_X86_INS_JP, - UC_X86_INS_JRCXZ, - UC_X86_INS_JS, - UC_X86_INS_KANDB, - UC_X86_INS_KANDD, - UC_X86_INS_KANDNB, - UC_X86_INS_KANDND, - UC_X86_INS_KANDNQ, - UC_X86_INS_KANDNW, - UC_X86_INS_KANDQ, - UC_X86_INS_KANDW, - UC_X86_INS_KMOVB, - UC_X86_INS_KMOVD, - UC_X86_INS_KMOVQ, - UC_X86_INS_KMOVW, - UC_X86_INS_KNOTB, - UC_X86_INS_KNOTD, - UC_X86_INS_KNOTQ, - UC_X86_INS_KNOTW, - UC_X86_INS_KORB, - UC_X86_INS_KORD, - UC_X86_INS_KORQ, - UC_X86_INS_KORTESTB, - UC_X86_INS_KORTESTD, - UC_X86_INS_KORTESTQ, - UC_X86_INS_KORTESTW, - UC_X86_INS_KORW, - UC_X86_INS_KSHIFTLB, - UC_X86_INS_KSHIFTLD, - UC_X86_INS_KSHIFTLQ, - UC_X86_INS_KSHIFTLW, - UC_X86_INS_KSHIFTRB, - UC_X86_INS_KSHIFTRD, - UC_X86_INS_KSHIFTRQ, - UC_X86_INS_KSHIFTRW, - UC_X86_INS_KUNPCKBW, - UC_X86_INS_KXNORB, - UC_X86_INS_KXNORD, - UC_X86_INS_KXNORQ, - UC_X86_INS_KXNORW, - UC_X86_INS_KXORB, - UC_X86_INS_KXORD, - UC_X86_INS_KXORQ, - UC_X86_INS_KXORW, - UC_X86_INS_LAHF, - UC_X86_INS_LAR, - UC_X86_INS_LDDQU, - UC_X86_INS_LDMXCSR, - UC_X86_INS_LDS, - UC_X86_INS_FLDZ, - UC_X86_INS_FLD1, - UC_X86_INS_FLD, - UC_X86_INS_LEA, - UC_X86_INS_LEAVE, - UC_X86_INS_LES, - UC_X86_INS_LFENCE, - UC_X86_INS_LFS, - UC_X86_INS_LGDT, - UC_X86_INS_LGS, - UC_X86_INS_LIDT, - UC_X86_INS_LLDT, - UC_X86_INS_LMSW, - UC_X86_INS_OR, - UC_X86_INS_SUB, - UC_X86_INS_XOR, - UC_X86_INS_LODSB, - UC_X86_INS_LODSD, - UC_X86_INS_LODSQ, - UC_X86_INS_LODSW, - UC_X86_INS_LOOP, - UC_X86_INS_LOOPE, - UC_X86_INS_LOOPNE, - UC_X86_INS_RETF, - UC_X86_INS_RETFQ, - UC_X86_INS_LSL, - UC_X86_INS_LSS, - UC_X86_INS_LTR, - UC_X86_INS_XADD, - UC_X86_INS_LZCNT, - UC_X86_INS_MASKMOVDQU, - UC_X86_INS_MAXPD, - UC_X86_INS_MAXPS, - UC_X86_INS_MAXSD, - UC_X86_INS_MAXSS, - UC_X86_INS_MFENCE, - UC_X86_INS_MINPD, - UC_X86_INS_MINPS, - UC_X86_INS_MINSD, - UC_X86_INS_MINSS, - UC_X86_INS_CVTPD2PI, - UC_X86_INS_CVTPI2PD, - UC_X86_INS_CVTPI2PS, - UC_X86_INS_CVTPS2PI, - UC_X86_INS_CVTTPD2PI, - UC_X86_INS_CVTTPS2PI, - UC_X86_INS_EMMS, - UC_X86_INS_MASKMOVQ, - UC_X86_INS_MOVD, - UC_X86_INS_MOVDQ2Q, - UC_X86_INS_MOVNTQ, - UC_X86_INS_MOVQ2DQ, - UC_X86_INS_MOVQ, - UC_X86_INS_PABSB, - UC_X86_INS_PABSD, - UC_X86_INS_PABSW, - UC_X86_INS_PACKSSDW, - UC_X86_INS_PACKSSWB, - UC_X86_INS_PACKUSWB, - UC_X86_INS_PADDB, - UC_X86_INS_PADDD, - UC_X86_INS_PADDQ, - UC_X86_INS_PADDSB, - UC_X86_INS_PADDSW, - UC_X86_INS_PADDUSB, - UC_X86_INS_PADDUSW, - UC_X86_INS_PADDW, - UC_X86_INS_PALIGNR, - UC_X86_INS_PANDN, - UC_X86_INS_PAND, - UC_X86_INS_PAVGB, - UC_X86_INS_PAVGW, - UC_X86_INS_PCMPEQB, - UC_X86_INS_PCMPEQD, - UC_X86_INS_PCMPEQW, - UC_X86_INS_PCMPGTB, - UC_X86_INS_PCMPGTD, - UC_X86_INS_PCMPGTW, - UC_X86_INS_PEXTRW, - UC_X86_INS_PHADDSW, - UC_X86_INS_PHADDW, - UC_X86_INS_PHADDD, - UC_X86_INS_PHSUBD, - UC_X86_INS_PHSUBSW, - UC_X86_INS_PHSUBW, - UC_X86_INS_PINSRW, - UC_X86_INS_PMADDUBSW, - UC_X86_INS_PMADDWD, - UC_X86_INS_PMAXSW, - UC_X86_INS_PMAXUB, - UC_X86_INS_PMINSW, - UC_X86_INS_PMINUB, - UC_X86_INS_PMOVMSKB, - UC_X86_INS_PMULHRSW, - UC_X86_INS_PMULHUW, - UC_X86_INS_PMULHW, - UC_X86_INS_PMULLW, - UC_X86_INS_PMULUDQ, - UC_X86_INS_POR, - UC_X86_INS_PSADBW, - UC_X86_INS_PSHUFB, - UC_X86_INS_PSHUFW, - UC_X86_INS_PSIGNB, - UC_X86_INS_PSIGND, - UC_X86_INS_PSIGNW, - UC_X86_INS_PSLLD, - UC_X86_INS_PSLLQ, - UC_X86_INS_PSLLW, - UC_X86_INS_PSRAD, - UC_X86_INS_PSRAW, - UC_X86_INS_PSRLD, - UC_X86_INS_PSRLQ, - UC_X86_INS_PSRLW, - UC_X86_INS_PSUBB, - UC_X86_INS_PSUBD, - UC_X86_INS_PSUBQ, - UC_X86_INS_PSUBSB, - UC_X86_INS_PSUBSW, - UC_X86_INS_PSUBUSB, - UC_X86_INS_PSUBUSW, - UC_X86_INS_PSUBW, - UC_X86_INS_PUNPCKHBW, - UC_X86_INS_PUNPCKHDQ, - UC_X86_INS_PUNPCKHWD, - UC_X86_INS_PUNPCKLBW, - UC_X86_INS_PUNPCKLDQ, - UC_X86_INS_PUNPCKLWD, - UC_X86_INS_PXOR, - UC_X86_INS_MONITOR, - UC_X86_INS_MONTMUL, - UC_X86_INS_MOV, - UC_X86_INS_MOVABS, - UC_X86_INS_MOVBE, - UC_X86_INS_MOVDDUP, - UC_X86_INS_MOVDQA, - UC_X86_INS_MOVDQU, - UC_X86_INS_MOVHLPS, - UC_X86_INS_MOVHPD, - UC_X86_INS_MOVHPS, - UC_X86_INS_MOVLHPS, - UC_X86_INS_MOVLPD, - UC_X86_INS_MOVLPS, - UC_X86_INS_MOVMSKPD, - UC_X86_INS_MOVMSKPS, - UC_X86_INS_MOVNTDQA, - UC_X86_INS_MOVNTDQ, - UC_X86_INS_MOVNTI, - UC_X86_INS_MOVNTPD, - UC_X86_INS_MOVNTPS, - UC_X86_INS_MOVNTSD, - UC_X86_INS_MOVNTSS, - UC_X86_INS_MOVSB, - UC_X86_INS_MOVSD, - UC_X86_INS_MOVSHDUP, - UC_X86_INS_MOVSLDUP, - UC_X86_INS_MOVSQ, - UC_X86_INS_MOVSS, - UC_X86_INS_MOVSW, - UC_X86_INS_MOVSX, - UC_X86_INS_MOVSXD, - UC_X86_INS_MOVUPD, - UC_X86_INS_MOVUPS, - UC_X86_INS_MOVZX, - UC_X86_INS_MPSADBW, - UC_X86_INS_MUL, - UC_X86_INS_MULPD, - UC_X86_INS_MULPS, - UC_X86_INS_MULSD, - UC_X86_INS_MULSS, - UC_X86_INS_MULX, - UC_X86_INS_FMUL, - UC_X86_INS_FIMUL, - UC_X86_INS_FMULP, - UC_X86_INS_MWAIT, - UC_X86_INS_NEG, - UC_X86_INS_NOP, - UC_X86_INS_NOT, - UC_X86_INS_OUT, - UC_X86_INS_OUTSB, - UC_X86_INS_OUTSD, - UC_X86_INS_OUTSW, - UC_X86_INS_PACKUSDW, - UC_X86_INS_PAUSE, - UC_X86_INS_PAVGUSB, - UC_X86_INS_PBLENDVB, - UC_X86_INS_PBLENDW, - UC_X86_INS_PCLMULQDQ, - UC_X86_INS_PCMPEQQ, - UC_X86_INS_PCMPESTRI, - UC_X86_INS_PCMPESTRM, - UC_X86_INS_PCMPGTQ, - UC_X86_INS_PCMPISTRI, - UC_X86_INS_PCMPISTRM, - UC_X86_INS_PCOMMIT, - UC_X86_INS_PDEP, - UC_X86_INS_PEXT, - UC_X86_INS_PEXTRB, - UC_X86_INS_PEXTRD, - UC_X86_INS_PEXTRQ, - UC_X86_INS_PF2ID, - UC_X86_INS_PF2IW, - UC_X86_INS_PFACC, - UC_X86_INS_PFADD, - UC_X86_INS_PFCMPEQ, - UC_X86_INS_PFCMPGE, - UC_X86_INS_PFCMPGT, - UC_X86_INS_PFMAX, - UC_X86_INS_PFMIN, - UC_X86_INS_PFMUL, - UC_X86_INS_PFNACC, - UC_X86_INS_PFPNACC, - UC_X86_INS_PFRCPIT1, - UC_X86_INS_PFRCPIT2, - UC_X86_INS_PFRCP, - UC_X86_INS_PFRSQIT1, - UC_X86_INS_PFRSQRT, - UC_X86_INS_PFSUBR, - UC_X86_INS_PFSUB, - UC_X86_INS_PHMINPOSUW, - UC_X86_INS_PI2FD, - UC_X86_INS_PI2FW, - UC_X86_INS_PINSRB, - UC_X86_INS_PINSRD, - UC_X86_INS_PINSRQ, - UC_X86_INS_PMAXSB, - UC_X86_INS_PMAXSD, - UC_X86_INS_PMAXUD, - UC_X86_INS_PMAXUW, - UC_X86_INS_PMINSB, - UC_X86_INS_PMINSD, - UC_X86_INS_PMINUD, - UC_X86_INS_PMINUW, - UC_X86_INS_PMOVSXBD, - UC_X86_INS_PMOVSXBQ, - UC_X86_INS_PMOVSXBW, - UC_X86_INS_PMOVSXDQ, - UC_X86_INS_PMOVSXWD, - UC_X86_INS_PMOVSXWQ, - UC_X86_INS_PMOVZXBD, - UC_X86_INS_PMOVZXBQ, - UC_X86_INS_PMOVZXBW, - UC_X86_INS_PMOVZXDQ, - UC_X86_INS_PMOVZXWD, - UC_X86_INS_PMOVZXWQ, - UC_X86_INS_PMULDQ, - UC_X86_INS_PMULHRW, - UC_X86_INS_PMULLD, - UC_X86_INS_POP, - UC_X86_INS_POPAW, - UC_X86_INS_POPAL, - UC_X86_INS_POPCNT, - UC_X86_INS_POPF, - UC_X86_INS_POPFD, - UC_X86_INS_POPFQ, - UC_X86_INS_PREFETCH, - UC_X86_INS_PREFETCHNTA, - UC_X86_INS_PREFETCHT0, - UC_X86_INS_PREFETCHT1, - UC_X86_INS_PREFETCHT2, - UC_X86_INS_PREFETCHW, - UC_X86_INS_PSHUFD, - UC_X86_INS_PSHUFHW, - UC_X86_INS_PSHUFLW, - UC_X86_INS_PSLLDQ, - UC_X86_INS_PSRLDQ, - UC_X86_INS_PSWAPD, - UC_X86_INS_PTEST, - UC_X86_INS_PUNPCKHQDQ, - UC_X86_INS_PUNPCKLQDQ, - UC_X86_INS_PUSH, - UC_X86_INS_PUSHAW, - UC_X86_INS_PUSHAL, - UC_X86_INS_PUSHF, - UC_X86_INS_PUSHFD, - UC_X86_INS_PUSHFQ, - UC_X86_INS_RCL, - UC_X86_INS_RCPPS, - UC_X86_INS_RCPSS, - UC_X86_INS_RCR, - UC_X86_INS_RDFSBASE, - UC_X86_INS_RDGSBASE, - UC_X86_INS_RDMSR, - UC_X86_INS_RDPMC, - UC_X86_INS_RDRAND, - UC_X86_INS_RDSEED, - UC_X86_INS_RDTSC, - UC_X86_INS_RDTSCP, - UC_X86_INS_ROL, - UC_X86_INS_ROR, - UC_X86_INS_RORX, - UC_X86_INS_ROUNDPD, - UC_X86_INS_ROUNDPS, - UC_X86_INS_ROUNDSD, - UC_X86_INS_ROUNDSS, - UC_X86_INS_RSM, - UC_X86_INS_RSQRTPS, - UC_X86_INS_RSQRTSS, - UC_X86_INS_SAHF, - UC_X86_INS_SAL, - UC_X86_INS_SALC, - UC_X86_INS_SAR, - UC_X86_INS_SARX, - UC_X86_INS_SBB, - UC_X86_INS_SCASB, - UC_X86_INS_SCASD, - UC_X86_INS_SCASQ, - UC_X86_INS_SCASW, - UC_X86_INS_SETAE, - UC_X86_INS_SETA, - UC_X86_INS_SETBE, - UC_X86_INS_SETB, - UC_X86_INS_SETE, - UC_X86_INS_SETGE, - UC_X86_INS_SETG, - UC_X86_INS_SETLE, - UC_X86_INS_SETL, - UC_X86_INS_SETNE, - UC_X86_INS_SETNO, - UC_X86_INS_SETNP, - UC_X86_INS_SETNS, - UC_X86_INS_SETO, - UC_X86_INS_SETP, - UC_X86_INS_SETS, - UC_X86_INS_SFENCE, - UC_X86_INS_SGDT, - UC_X86_INS_SHA1MSG1, - UC_X86_INS_SHA1MSG2, - UC_X86_INS_SHA1NEXTE, - UC_X86_INS_SHA1RNDS4, - UC_X86_INS_SHA256MSG1, - UC_X86_INS_SHA256MSG2, - UC_X86_INS_SHA256RNDS2, - UC_X86_INS_SHL, - UC_X86_INS_SHLD, - UC_X86_INS_SHLX, - UC_X86_INS_SHR, - UC_X86_INS_SHRD, - UC_X86_INS_SHRX, - UC_X86_INS_SHUFPD, - UC_X86_INS_SHUFPS, - UC_X86_INS_SIDT, - UC_X86_INS_FSIN, - UC_X86_INS_SKINIT, - UC_X86_INS_SLDT, - UC_X86_INS_SMSW, - UC_X86_INS_SQRTPD, - UC_X86_INS_SQRTPS, - UC_X86_INS_SQRTSD, - UC_X86_INS_SQRTSS, - UC_X86_INS_FSQRT, - UC_X86_INS_STAC, - UC_X86_INS_STC, - UC_X86_INS_STD, - UC_X86_INS_STGI, - UC_X86_INS_STI, - UC_X86_INS_STMXCSR, - UC_X86_INS_STOSB, - UC_X86_INS_STOSD, - UC_X86_INS_STOSQ, - UC_X86_INS_STOSW, - UC_X86_INS_STR, - UC_X86_INS_FST, - UC_X86_INS_FSTP, - UC_X86_INS_FSTPNCE, - UC_X86_INS_FXCH, - UC_X86_INS_SUBPD, - UC_X86_INS_SUBPS, - UC_X86_INS_FSUBR, - UC_X86_INS_FISUBR, - UC_X86_INS_FSUBRP, - UC_X86_INS_SUBSD, - UC_X86_INS_SUBSS, - UC_X86_INS_FSUB, - UC_X86_INS_FISUB, - UC_X86_INS_FSUBP, - UC_X86_INS_SWAPGS, - UC_X86_INS_SYSCALL, - UC_X86_INS_SYSENTER, - UC_X86_INS_SYSEXIT, - UC_X86_INS_SYSRET, - UC_X86_INS_T1MSKC, - UC_X86_INS_TEST, - UC_X86_INS_UD2, - UC_X86_INS_FTST, - UC_X86_INS_TZCNT, - UC_X86_INS_TZMSK, - UC_X86_INS_FUCOMPI, - UC_X86_INS_FUCOMI, - UC_X86_INS_FUCOMPP, - UC_X86_INS_FUCOMP, - UC_X86_INS_FUCOM, - UC_X86_INS_UD2B, - UC_X86_INS_UNPCKHPD, - UC_X86_INS_UNPCKHPS, - UC_X86_INS_UNPCKLPD, - UC_X86_INS_UNPCKLPS, - UC_X86_INS_VADDPD, - UC_X86_INS_VADDPS, - UC_X86_INS_VADDSD, - UC_X86_INS_VADDSS, - UC_X86_INS_VADDSUBPD, - UC_X86_INS_VADDSUBPS, - UC_X86_INS_VAESDECLAST, - UC_X86_INS_VAESDEC, - UC_X86_INS_VAESENCLAST, - UC_X86_INS_VAESENC, - UC_X86_INS_VAESIMC, - UC_X86_INS_VAESKEYGENASSIST, - UC_X86_INS_VALIGND, - UC_X86_INS_VALIGNQ, - UC_X86_INS_VANDNPD, - UC_X86_INS_VANDNPS, - UC_X86_INS_VANDPD, - UC_X86_INS_VANDPS, - UC_X86_INS_VBLENDMPD, - UC_X86_INS_VBLENDMPS, - UC_X86_INS_VBLENDPD, - UC_X86_INS_VBLENDPS, - UC_X86_INS_VBLENDVPD, - UC_X86_INS_VBLENDVPS, - UC_X86_INS_VBROADCASTF128, - UC_X86_INS_VBROADCASTI32X4, - UC_X86_INS_VBROADCASTI64X4, - UC_X86_INS_VBROADCASTSD, - UC_X86_INS_VBROADCASTSS, - UC_X86_INS_VCMPPD, - UC_X86_INS_VCMPPS, - UC_X86_INS_VCMPSD, - UC_X86_INS_VCMPSS, - UC_X86_INS_VCOMPRESSPD, - UC_X86_INS_VCOMPRESSPS, - UC_X86_INS_VCVTDQ2PD, - UC_X86_INS_VCVTDQ2PS, - UC_X86_INS_VCVTPD2DQX, - UC_X86_INS_VCVTPD2DQ, - UC_X86_INS_VCVTPD2PSX, - UC_X86_INS_VCVTPD2PS, - UC_X86_INS_VCVTPD2UDQ, - UC_X86_INS_VCVTPH2PS, - UC_X86_INS_VCVTPS2DQ, - UC_X86_INS_VCVTPS2PD, - UC_X86_INS_VCVTPS2PH, - UC_X86_INS_VCVTPS2UDQ, - UC_X86_INS_VCVTSD2SI, - UC_X86_INS_VCVTSD2USI, - UC_X86_INS_VCVTSS2SI, - UC_X86_INS_VCVTSS2USI, - UC_X86_INS_VCVTTPD2DQX, - UC_X86_INS_VCVTTPD2DQ, - UC_X86_INS_VCVTTPD2UDQ, - UC_X86_INS_VCVTTPS2DQ, - UC_X86_INS_VCVTTPS2UDQ, - UC_X86_INS_VCVTUDQ2PD, - UC_X86_INS_VCVTUDQ2PS, - UC_X86_INS_VDIVPD, - UC_X86_INS_VDIVPS, - UC_X86_INS_VDIVSD, - UC_X86_INS_VDIVSS, - UC_X86_INS_VDPPD, - UC_X86_INS_VDPPS, - UC_X86_INS_VERR, - UC_X86_INS_VERW, - UC_X86_INS_VEXP2PD, - UC_X86_INS_VEXP2PS, - UC_X86_INS_VEXPANDPD, - UC_X86_INS_VEXPANDPS, - UC_X86_INS_VEXTRACTF128, - UC_X86_INS_VEXTRACTF32X4, - UC_X86_INS_VEXTRACTF64X4, - UC_X86_INS_VEXTRACTI128, - UC_X86_INS_VEXTRACTI32X4, - UC_X86_INS_VEXTRACTI64X4, - UC_X86_INS_VEXTRACTPS, - UC_X86_INS_VFMADD132PD, - UC_X86_INS_VFMADD132PS, - UC_X86_INS_VFMADDPD, - UC_X86_INS_VFMADD213PD, - UC_X86_INS_VFMADD231PD, - UC_X86_INS_VFMADDPS, - UC_X86_INS_VFMADD213PS, - UC_X86_INS_VFMADD231PS, - UC_X86_INS_VFMADDSD, - UC_X86_INS_VFMADD213SD, - UC_X86_INS_VFMADD132SD, - UC_X86_INS_VFMADD231SD, - UC_X86_INS_VFMADDSS, - UC_X86_INS_VFMADD213SS, - UC_X86_INS_VFMADD132SS, - UC_X86_INS_VFMADD231SS, - UC_X86_INS_VFMADDSUB132PD, - UC_X86_INS_VFMADDSUB132PS, - UC_X86_INS_VFMADDSUBPD, - UC_X86_INS_VFMADDSUB213PD, - UC_X86_INS_VFMADDSUB231PD, - UC_X86_INS_VFMADDSUBPS, - UC_X86_INS_VFMADDSUB213PS, - UC_X86_INS_VFMADDSUB231PS, - UC_X86_INS_VFMSUB132PD, - UC_X86_INS_VFMSUB132PS, - UC_X86_INS_VFMSUBADD132PD, - UC_X86_INS_VFMSUBADD132PS, - UC_X86_INS_VFMSUBADDPD, - UC_X86_INS_VFMSUBADD213PD, - UC_X86_INS_VFMSUBADD231PD, - UC_X86_INS_VFMSUBADDPS, - UC_X86_INS_VFMSUBADD213PS, - UC_X86_INS_VFMSUBADD231PS, - UC_X86_INS_VFMSUBPD, - UC_X86_INS_VFMSUB213PD, - UC_X86_INS_VFMSUB231PD, - UC_X86_INS_VFMSUBPS, - UC_X86_INS_VFMSUB213PS, - UC_X86_INS_VFMSUB231PS, - UC_X86_INS_VFMSUBSD, - UC_X86_INS_VFMSUB213SD, - UC_X86_INS_VFMSUB132SD, - UC_X86_INS_VFMSUB231SD, - UC_X86_INS_VFMSUBSS, - UC_X86_INS_VFMSUB213SS, - UC_X86_INS_VFMSUB132SS, - UC_X86_INS_VFMSUB231SS, - UC_X86_INS_VFNMADD132PD, - UC_X86_INS_VFNMADD132PS, - UC_X86_INS_VFNMADDPD, - UC_X86_INS_VFNMADD213PD, - UC_X86_INS_VFNMADD231PD, - UC_X86_INS_VFNMADDPS, - UC_X86_INS_VFNMADD213PS, - UC_X86_INS_VFNMADD231PS, - UC_X86_INS_VFNMADDSD, - UC_X86_INS_VFNMADD213SD, - UC_X86_INS_VFNMADD132SD, - UC_X86_INS_VFNMADD231SD, - UC_X86_INS_VFNMADDSS, - UC_X86_INS_VFNMADD213SS, - UC_X86_INS_VFNMADD132SS, - UC_X86_INS_VFNMADD231SS, - UC_X86_INS_VFNMSUB132PD, - UC_X86_INS_VFNMSUB132PS, - UC_X86_INS_VFNMSUBPD, - UC_X86_INS_VFNMSUB213PD, - UC_X86_INS_VFNMSUB231PD, - UC_X86_INS_VFNMSUBPS, - UC_X86_INS_VFNMSUB213PS, - UC_X86_INS_VFNMSUB231PS, - UC_X86_INS_VFNMSUBSD, - UC_X86_INS_VFNMSUB213SD, - UC_X86_INS_VFNMSUB132SD, - UC_X86_INS_VFNMSUB231SD, - UC_X86_INS_VFNMSUBSS, - UC_X86_INS_VFNMSUB213SS, - UC_X86_INS_VFNMSUB132SS, - UC_X86_INS_VFNMSUB231SS, - UC_X86_INS_VFRCZPD, - UC_X86_INS_VFRCZPS, - UC_X86_INS_VFRCZSD, - UC_X86_INS_VFRCZSS, - UC_X86_INS_VORPD, - UC_X86_INS_VORPS, - UC_X86_INS_VXORPD, - UC_X86_INS_VXORPS, - UC_X86_INS_VGATHERDPD, - UC_X86_INS_VGATHERDPS, - UC_X86_INS_VGATHERPF0DPD, - UC_X86_INS_VGATHERPF0DPS, - UC_X86_INS_VGATHERPF0QPD, - UC_X86_INS_VGATHERPF0QPS, - UC_X86_INS_VGATHERPF1DPD, - UC_X86_INS_VGATHERPF1DPS, - UC_X86_INS_VGATHERPF1QPD, - UC_X86_INS_VGATHERPF1QPS, - UC_X86_INS_VGATHERQPD, - UC_X86_INS_VGATHERQPS, - UC_X86_INS_VHADDPD, - UC_X86_INS_VHADDPS, - UC_X86_INS_VHSUBPD, - UC_X86_INS_VHSUBPS, - UC_X86_INS_VINSERTF128, - UC_X86_INS_VINSERTF32X4, - UC_X86_INS_VINSERTF32X8, - UC_X86_INS_VINSERTF64X2, - UC_X86_INS_VINSERTF64X4, - UC_X86_INS_VINSERTI128, - UC_X86_INS_VINSERTI32X4, - UC_X86_INS_VINSERTI32X8, - UC_X86_INS_VINSERTI64X2, - UC_X86_INS_VINSERTI64X4, - UC_X86_INS_VINSERTPS, - UC_X86_INS_VLDDQU, - UC_X86_INS_VLDMXCSR, - UC_X86_INS_VMASKMOVDQU, - UC_X86_INS_VMASKMOVPD, - UC_X86_INS_VMASKMOVPS, - UC_X86_INS_VMAXPD, - UC_X86_INS_VMAXPS, - UC_X86_INS_VMAXSD, - UC_X86_INS_VMAXSS, - UC_X86_INS_VMCALL, - UC_X86_INS_VMCLEAR, - UC_X86_INS_VMFUNC, - UC_X86_INS_VMINPD, - UC_X86_INS_VMINPS, - UC_X86_INS_VMINSD, - UC_X86_INS_VMINSS, - UC_X86_INS_VMLAUNCH, - UC_X86_INS_VMLOAD, - UC_X86_INS_VMMCALL, - UC_X86_INS_VMOVQ, - UC_X86_INS_VMOVDDUP, - UC_X86_INS_VMOVD, - UC_X86_INS_VMOVDQA32, - UC_X86_INS_VMOVDQA64, - UC_X86_INS_VMOVDQA, - UC_X86_INS_VMOVDQU16, - UC_X86_INS_VMOVDQU32, - UC_X86_INS_VMOVDQU64, - UC_X86_INS_VMOVDQU8, - UC_X86_INS_VMOVDQU, - UC_X86_INS_VMOVHLPS, - UC_X86_INS_VMOVHPD, - UC_X86_INS_VMOVHPS, - UC_X86_INS_VMOVLHPS, - UC_X86_INS_VMOVLPD, - UC_X86_INS_VMOVLPS, - UC_X86_INS_VMOVMSKPD, - UC_X86_INS_VMOVMSKPS, - UC_X86_INS_VMOVNTDQA, - UC_X86_INS_VMOVNTDQ, - UC_X86_INS_VMOVNTPD, - UC_X86_INS_VMOVNTPS, - UC_X86_INS_VMOVSD, - UC_X86_INS_VMOVSHDUP, - UC_X86_INS_VMOVSLDUP, - UC_X86_INS_VMOVSS, - UC_X86_INS_VMOVUPD, - UC_X86_INS_VMOVUPS, - UC_X86_INS_VMPSADBW, - UC_X86_INS_VMPTRLD, - UC_X86_INS_VMPTRST, - UC_X86_INS_VMREAD, - UC_X86_INS_VMRESUME, - UC_X86_INS_VMRUN, - UC_X86_INS_VMSAVE, - UC_X86_INS_VMULPD, - UC_X86_INS_VMULPS, - UC_X86_INS_VMULSD, - UC_X86_INS_VMULSS, - UC_X86_INS_VMWRITE, - UC_X86_INS_VMXOFF, - UC_X86_INS_VMXON, - UC_X86_INS_VPABSB, - UC_X86_INS_VPABSD, - UC_X86_INS_VPABSQ, - UC_X86_INS_VPABSW, - UC_X86_INS_VPACKSSDW, - UC_X86_INS_VPACKSSWB, - UC_X86_INS_VPACKUSDW, - UC_X86_INS_VPACKUSWB, - UC_X86_INS_VPADDB, - UC_X86_INS_VPADDD, - UC_X86_INS_VPADDQ, - UC_X86_INS_VPADDSB, - UC_X86_INS_VPADDSW, - UC_X86_INS_VPADDUSB, - UC_X86_INS_VPADDUSW, - UC_X86_INS_VPADDW, - UC_X86_INS_VPALIGNR, - UC_X86_INS_VPANDD, - UC_X86_INS_VPANDND, - UC_X86_INS_VPANDNQ, - UC_X86_INS_VPANDN, - UC_X86_INS_VPANDQ, - UC_X86_INS_VPAND, - UC_X86_INS_VPAVGB, - UC_X86_INS_VPAVGW, - UC_X86_INS_VPBLENDD, - UC_X86_INS_VPBLENDMB, - UC_X86_INS_VPBLENDMD, - UC_X86_INS_VPBLENDMQ, - UC_X86_INS_VPBLENDMW, - UC_X86_INS_VPBLENDVB, - UC_X86_INS_VPBLENDW, - UC_X86_INS_VPBROADCASTB, - UC_X86_INS_VPBROADCASTD, - UC_X86_INS_VPBROADCASTMB2Q, - UC_X86_INS_VPBROADCASTMW2D, - UC_X86_INS_VPBROADCASTQ, - UC_X86_INS_VPBROADCASTW, - UC_X86_INS_VPCLMULQDQ, - UC_X86_INS_VPCMOV, - UC_X86_INS_VPCMPB, - UC_X86_INS_VPCMPD, - UC_X86_INS_VPCMPEQB, - UC_X86_INS_VPCMPEQD, - UC_X86_INS_VPCMPEQQ, - UC_X86_INS_VPCMPEQW, - UC_X86_INS_VPCMPESTRI, - UC_X86_INS_VPCMPESTRM, - UC_X86_INS_VPCMPGTB, - UC_X86_INS_VPCMPGTD, - UC_X86_INS_VPCMPGTQ, - UC_X86_INS_VPCMPGTW, - UC_X86_INS_VPCMPISTRI, - UC_X86_INS_VPCMPISTRM, - UC_X86_INS_VPCMPQ, - UC_X86_INS_VPCMPUB, - UC_X86_INS_VPCMPUD, - UC_X86_INS_VPCMPUQ, - UC_X86_INS_VPCMPUW, - UC_X86_INS_VPCMPW, - UC_X86_INS_VPCOMB, - UC_X86_INS_VPCOMD, - UC_X86_INS_VPCOMPRESSD, - UC_X86_INS_VPCOMPRESSQ, - UC_X86_INS_VPCOMQ, - UC_X86_INS_VPCOMUB, - UC_X86_INS_VPCOMUD, - UC_X86_INS_VPCOMUQ, - UC_X86_INS_VPCOMUW, - UC_X86_INS_VPCOMW, - UC_X86_INS_VPCONFLICTD, - UC_X86_INS_VPCONFLICTQ, - UC_X86_INS_VPERM2F128, - UC_X86_INS_VPERM2I128, - UC_X86_INS_VPERMD, - UC_X86_INS_VPERMI2D, - UC_X86_INS_VPERMI2PD, - UC_X86_INS_VPERMI2PS, - UC_X86_INS_VPERMI2Q, - UC_X86_INS_VPERMIL2PD, - UC_X86_INS_VPERMIL2PS, - UC_X86_INS_VPERMILPD, - UC_X86_INS_VPERMILPS, - UC_X86_INS_VPERMPD, - UC_X86_INS_VPERMPS, - UC_X86_INS_VPERMQ, - UC_X86_INS_VPERMT2D, - UC_X86_INS_VPERMT2PD, - UC_X86_INS_VPERMT2PS, - UC_X86_INS_VPERMT2Q, - UC_X86_INS_VPEXPANDD, - UC_X86_INS_VPEXPANDQ, - UC_X86_INS_VPEXTRB, - UC_X86_INS_VPEXTRD, - UC_X86_INS_VPEXTRQ, - UC_X86_INS_VPEXTRW, - UC_X86_INS_VPGATHERDD, - UC_X86_INS_VPGATHERDQ, - UC_X86_INS_VPGATHERQD, - UC_X86_INS_VPGATHERQQ, - UC_X86_INS_VPHADDBD, - UC_X86_INS_VPHADDBQ, - UC_X86_INS_VPHADDBW, - UC_X86_INS_VPHADDDQ, - UC_X86_INS_VPHADDD, - UC_X86_INS_VPHADDSW, - UC_X86_INS_VPHADDUBD, - UC_X86_INS_VPHADDUBQ, - UC_X86_INS_VPHADDUBW, - UC_X86_INS_VPHADDUDQ, - UC_X86_INS_VPHADDUWD, - UC_X86_INS_VPHADDUWQ, - UC_X86_INS_VPHADDWD, - UC_X86_INS_VPHADDWQ, - UC_X86_INS_VPHADDW, - UC_X86_INS_VPHMINPOSUW, - UC_X86_INS_VPHSUBBW, - UC_X86_INS_VPHSUBDQ, - UC_X86_INS_VPHSUBD, - UC_X86_INS_VPHSUBSW, - UC_X86_INS_VPHSUBWD, - UC_X86_INS_VPHSUBW, - UC_X86_INS_VPINSRB, - UC_X86_INS_VPINSRD, - UC_X86_INS_VPINSRQ, - UC_X86_INS_VPINSRW, - UC_X86_INS_VPLZCNTD, - UC_X86_INS_VPLZCNTQ, - UC_X86_INS_VPMACSDD, - UC_X86_INS_VPMACSDQH, - UC_X86_INS_VPMACSDQL, - UC_X86_INS_VPMACSSDD, - UC_X86_INS_VPMACSSDQH, - UC_X86_INS_VPMACSSDQL, - UC_X86_INS_VPMACSSWD, - UC_X86_INS_VPMACSSWW, - UC_X86_INS_VPMACSWD, - UC_X86_INS_VPMACSWW, - UC_X86_INS_VPMADCSSWD, - UC_X86_INS_VPMADCSWD, - UC_X86_INS_VPMADDUBSW, - UC_X86_INS_VPMADDWD, - UC_X86_INS_VPMASKMOVD, - UC_X86_INS_VPMASKMOVQ, - UC_X86_INS_VPMAXSB, - UC_X86_INS_VPMAXSD, - UC_X86_INS_VPMAXSQ, - UC_X86_INS_VPMAXSW, - UC_X86_INS_VPMAXUB, - UC_X86_INS_VPMAXUD, - UC_X86_INS_VPMAXUQ, - UC_X86_INS_VPMAXUW, - UC_X86_INS_VPMINSB, - UC_X86_INS_VPMINSD, - UC_X86_INS_VPMINSQ, - UC_X86_INS_VPMINSW, - UC_X86_INS_VPMINUB, - UC_X86_INS_VPMINUD, - UC_X86_INS_VPMINUQ, - UC_X86_INS_VPMINUW, - UC_X86_INS_VPMOVDB, - UC_X86_INS_VPMOVDW, - UC_X86_INS_VPMOVM2B, - UC_X86_INS_VPMOVM2D, - UC_X86_INS_VPMOVM2Q, - UC_X86_INS_VPMOVM2W, - UC_X86_INS_VPMOVMSKB, - UC_X86_INS_VPMOVQB, - UC_X86_INS_VPMOVQD, - UC_X86_INS_VPMOVQW, - UC_X86_INS_VPMOVSDB, - UC_X86_INS_VPMOVSDW, - UC_X86_INS_VPMOVSQB, - UC_X86_INS_VPMOVSQD, - UC_X86_INS_VPMOVSQW, - UC_X86_INS_VPMOVSXBD, - UC_X86_INS_VPMOVSXBQ, - UC_X86_INS_VPMOVSXBW, - UC_X86_INS_VPMOVSXDQ, - UC_X86_INS_VPMOVSXWD, - UC_X86_INS_VPMOVSXWQ, - UC_X86_INS_VPMOVUSDB, - UC_X86_INS_VPMOVUSDW, - UC_X86_INS_VPMOVUSQB, - UC_X86_INS_VPMOVUSQD, - UC_X86_INS_VPMOVUSQW, - UC_X86_INS_VPMOVZXBD, - UC_X86_INS_VPMOVZXBQ, - UC_X86_INS_VPMOVZXBW, - UC_X86_INS_VPMOVZXDQ, - UC_X86_INS_VPMOVZXWD, - UC_X86_INS_VPMOVZXWQ, - UC_X86_INS_VPMULDQ, - UC_X86_INS_VPMULHRSW, - UC_X86_INS_VPMULHUW, - UC_X86_INS_VPMULHW, - UC_X86_INS_VPMULLD, - UC_X86_INS_VPMULLQ, - UC_X86_INS_VPMULLW, - UC_X86_INS_VPMULUDQ, - UC_X86_INS_VPORD, - UC_X86_INS_VPORQ, - UC_X86_INS_VPOR, - UC_X86_INS_VPPERM, - UC_X86_INS_VPROTB, - UC_X86_INS_VPROTD, - UC_X86_INS_VPROTQ, - UC_X86_INS_VPROTW, - UC_X86_INS_VPSADBW, - UC_X86_INS_VPSCATTERDD, - UC_X86_INS_VPSCATTERDQ, - UC_X86_INS_VPSCATTERQD, - UC_X86_INS_VPSCATTERQQ, - UC_X86_INS_VPSHAB, - UC_X86_INS_VPSHAD, - UC_X86_INS_VPSHAQ, - UC_X86_INS_VPSHAW, - UC_X86_INS_VPSHLB, - UC_X86_INS_VPSHLD, - UC_X86_INS_VPSHLQ, - UC_X86_INS_VPSHLW, - UC_X86_INS_VPSHUFB, - UC_X86_INS_VPSHUFD, - UC_X86_INS_VPSHUFHW, - UC_X86_INS_VPSHUFLW, - UC_X86_INS_VPSIGNB, - UC_X86_INS_VPSIGND, - UC_X86_INS_VPSIGNW, - UC_X86_INS_VPSLLDQ, - UC_X86_INS_VPSLLD, - UC_X86_INS_VPSLLQ, - UC_X86_INS_VPSLLVD, - UC_X86_INS_VPSLLVQ, - UC_X86_INS_VPSLLW, - UC_X86_INS_VPSRAD, - UC_X86_INS_VPSRAQ, - UC_X86_INS_VPSRAVD, - UC_X86_INS_VPSRAVQ, - UC_X86_INS_VPSRAW, - UC_X86_INS_VPSRLDQ, - UC_X86_INS_VPSRLD, - UC_X86_INS_VPSRLQ, - UC_X86_INS_VPSRLVD, - UC_X86_INS_VPSRLVQ, - UC_X86_INS_VPSRLW, - UC_X86_INS_VPSUBB, - UC_X86_INS_VPSUBD, - UC_X86_INS_VPSUBQ, - UC_X86_INS_VPSUBSB, - UC_X86_INS_VPSUBSW, - UC_X86_INS_VPSUBUSB, - UC_X86_INS_VPSUBUSW, - UC_X86_INS_VPSUBW, - UC_X86_INS_VPTESTMD, - UC_X86_INS_VPTESTMQ, - UC_X86_INS_VPTESTNMD, - UC_X86_INS_VPTESTNMQ, - UC_X86_INS_VPTEST, - UC_X86_INS_VPUNPCKHBW, - UC_X86_INS_VPUNPCKHDQ, - UC_X86_INS_VPUNPCKHQDQ, - UC_X86_INS_VPUNPCKHWD, - UC_X86_INS_VPUNPCKLBW, - UC_X86_INS_VPUNPCKLDQ, - UC_X86_INS_VPUNPCKLQDQ, - UC_X86_INS_VPUNPCKLWD, - UC_X86_INS_VPXORD, - UC_X86_INS_VPXORQ, - UC_X86_INS_VPXOR, - UC_X86_INS_VRCP14PD, - UC_X86_INS_VRCP14PS, - UC_X86_INS_VRCP14SD, - UC_X86_INS_VRCP14SS, - UC_X86_INS_VRCP28PD, - UC_X86_INS_VRCP28PS, - UC_X86_INS_VRCP28SD, - UC_X86_INS_VRCP28SS, - UC_X86_INS_VRCPPS, - UC_X86_INS_VRCPSS, - UC_X86_INS_VRNDSCALEPD, - UC_X86_INS_VRNDSCALEPS, - UC_X86_INS_VRNDSCALESD, - UC_X86_INS_VRNDSCALESS, - UC_X86_INS_VROUNDPD, - UC_X86_INS_VROUNDPS, - UC_X86_INS_VROUNDSD, - UC_X86_INS_VROUNDSS, - UC_X86_INS_VRSQRT14PD, - UC_X86_INS_VRSQRT14PS, - UC_X86_INS_VRSQRT14SD, - UC_X86_INS_VRSQRT14SS, - UC_X86_INS_VRSQRT28PD, - UC_X86_INS_VRSQRT28PS, - UC_X86_INS_VRSQRT28SD, - UC_X86_INS_VRSQRT28SS, - UC_X86_INS_VRSQRTPS, - UC_X86_INS_VRSQRTSS, - UC_X86_INS_VSCATTERDPD, - UC_X86_INS_VSCATTERDPS, - UC_X86_INS_VSCATTERPF0DPD, - UC_X86_INS_VSCATTERPF0DPS, - UC_X86_INS_VSCATTERPF0QPD, - UC_X86_INS_VSCATTERPF0QPS, - UC_X86_INS_VSCATTERPF1DPD, - UC_X86_INS_VSCATTERPF1DPS, - UC_X86_INS_VSCATTERPF1QPD, - UC_X86_INS_VSCATTERPF1QPS, - UC_X86_INS_VSCATTERQPD, - UC_X86_INS_VSCATTERQPS, - UC_X86_INS_VSHUFPD, - UC_X86_INS_VSHUFPS, - UC_X86_INS_VSQRTPD, - UC_X86_INS_VSQRTPS, - UC_X86_INS_VSQRTSD, - UC_X86_INS_VSQRTSS, - UC_X86_INS_VSTMXCSR, - UC_X86_INS_VSUBPD, - UC_X86_INS_VSUBPS, - UC_X86_INS_VSUBSD, - UC_X86_INS_VSUBSS, - UC_X86_INS_VTESTPD, - UC_X86_INS_VTESTPS, - UC_X86_INS_VUNPCKHPD, - UC_X86_INS_VUNPCKHPS, - UC_X86_INS_VUNPCKLPD, - UC_X86_INS_VUNPCKLPS, - UC_X86_INS_VZEROALL, - UC_X86_INS_VZEROUPPER, - UC_X86_INS_WAIT, - UC_X86_INS_WBINVD, - UC_X86_INS_WRFSBASE, - UC_X86_INS_WRGSBASE, - UC_X86_INS_WRMSR, - UC_X86_INS_XABORT, - UC_X86_INS_XACQUIRE, - UC_X86_INS_XBEGIN, - UC_X86_INS_XCHG, - UC_X86_INS_XCRYPTCBC, - UC_X86_INS_XCRYPTCFB, - UC_X86_INS_XCRYPTCTR, - UC_X86_INS_XCRYPTECB, - UC_X86_INS_XCRYPTOFB, - UC_X86_INS_XEND, - UC_X86_INS_XGETBV, - UC_X86_INS_XLATB, - UC_X86_INS_XRELEASE, - UC_X86_INS_XRSTOR, - UC_X86_INS_XRSTOR64, - UC_X86_INS_XRSTORS, - UC_X86_INS_XRSTORS64, - UC_X86_INS_XSAVE, - UC_X86_INS_XSAVE64, - UC_X86_INS_XSAVEC, - UC_X86_INS_XSAVEC64, - UC_X86_INS_XSAVEOPT, - UC_X86_INS_XSAVEOPT64, - UC_X86_INS_XSAVES, - UC_X86_INS_XSAVES64, - UC_X86_INS_XSETBV, - UC_X86_INS_XSHA1, - UC_X86_INS_XSHA256, - UC_X86_INS_XSTORE, - UC_X86_INS_XTEST, - UC_X86_INS_FDISI8087_NOP, - UC_X86_INS_FENI8087_NOP, + UC_X86_INS_AAA, + UC_X86_INS_AAD, + UC_X86_INS_AAM, + UC_X86_INS_AAS, + UC_X86_INS_FABS, + UC_X86_INS_ADC, + UC_X86_INS_ADCX, + UC_X86_INS_ADD, + UC_X86_INS_ADDPD, + UC_X86_INS_ADDPS, + UC_X86_INS_ADDSD, + UC_X86_INS_ADDSS, + UC_X86_INS_ADDSUBPD, + UC_X86_INS_ADDSUBPS, + UC_X86_INS_FADD, + UC_X86_INS_FIADD, + UC_X86_INS_FADDP, + UC_X86_INS_ADOX, + UC_X86_INS_AESDECLAST, + UC_X86_INS_AESDEC, + UC_X86_INS_AESENCLAST, + UC_X86_INS_AESENC, + UC_X86_INS_AESIMC, + UC_X86_INS_AESKEYGENASSIST, + UC_X86_INS_AND, + UC_X86_INS_ANDN, + UC_X86_INS_ANDNPD, + UC_X86_INS_ANDNPS, + UC_X86_INS_ANDPD, + UC_X86_INS_ANDPS, + UC_X86_INS_ARPL, + UC_X86_INS_BEXTR, + UC_X86_INS_BLCFILL, + UC_X86_INS_BLCI, + UC_X86_INS_BLCIC, + UC_X86_INS_BLCMSK, + UC_X86_INS_BLCS, + UC_X86_INS_BLENDPD, + UC_X86_INS_BLENDPS, + UC_X86_INS_BLENDVPD, + UC_X86_INS_BLENDVPS, + UC_X86_INS_BLSFILL, + UC_X86_INS_BLSI, + UC_X86_INS_BLSIC, + UC_X86_INS_BLSMSK, + UC_X86_INS_BLSR, + UC_X86_INS_BOUND, + UC_X86_INS_BSF, + UC_X86_INS_BSR, + UC_X86_INS_BSWAP, + UC_X86_INS_BT, + UC_X86_INS_BTC, + UC_X86_INS_BTR, + UC_X86_INS_BTS, + UC_X86_INS_BZHI, + UC_X86_INS_CALL, + UC_X86_INS_CBW, + UC_X86_INS_CDQ, + UC_X86_INS_CDQE, + UC_X86_INS_FCHS, + UC_X86_INS_CLAC, + UC_X86_INS_CLC, + UC_X86_INS_CLD, + UC_X86_INS_CLFLUSH, + UC_X86_INS_CLFLUSHOPT, + UC_X86_INS_CLGI, + UC_X86_INS_CLI, + UC_X86_INS_CLTS, + UC_X86_INS_CLWB, + UC_X86_INS_CMC, + UC_X86_INS_CMOVA, + UC_X86_INS_CMOVAE, + UC_X86_INS_CMOVB, + UC_X86_INS_CMOVBE, + UC_X86_INS_FCMOVBE, + UC_X86_INS_FCMOVB, + UC_X86_INS_CMOVE, + UC_X86_INS_FCMOVE, + UC_X86_INS_CMOVG, + UC_X86_INS_CMOVGE, + UC_X86_INS_CMOVL, + UC_X86_INS_CMOVLE, + UC_X86_INS_FCMOVNBE, + UC_X86_INS_FCMOVNB, + UC_X86_INS_CMOVNE, + UC_X86_INS_FCMOVNE, + UC_X86_INS_CMOVNO, + UC_X86_INS_CMOVNP, + UC_X86_INS_FCMOVNU, + UC_X86_INS_CMOVNS, + UC_X86_INS_CMOVO, + UC_X86_INS_CMOVP, + UC_X86_INS_FCMOVU, + UC_X86_INS_CMOVS, + UC_X86_INS_CMP, + UC_X86_INS_CMPPD, + UC_X86_INS_CMPPS, + UC_X86_INS_CMPSB, + UC_X86_INS_CMPSD, + UC_X86_INS_CMPSQ, + UC_X86_INS_CMPSS, + UC_X86_INS_CMPSW, + UC_X86_INS_CMPXCHG16B, + UC_X86_INS_CMPXCHG, + UC_X86_INS_CMPXCHG8B, + UC_X86_INS_COMISD, + UC_X86_INS_COMISS, + UC_X86_INS_FCOMP, + UC_X86_INS_FCOMPI, + UC_X86_INS_FCOMI, + UC_X86_INS_FCOM, + UC_X86_INS_FCOS, + UC_X86_INS_CPUID, + UC_X86_INS_CQO, + UC_X86_INS_CRC32, + UC_X86_INS_CVTDQ2PD, + UC_X86_INS_CVTDQ2PS, + UC_X86_INS_CVTPD2DQ, + UC_X86_INS_CVTPD2PS, + UC_X86_INS_CVTPS2DQ, + UC_X86_INS_CVTPS2PD, + UC_X86_INS_CVTSD2SI, + UC_X86_INS_CVTSD2SS, + UC_X86_INS_CVTSI2SD, + UC_X86_INS_CVTSI2SS, + UC_X86_INS_CVTSS2SD, + UC_X86_INS_CVTSS2SI, + UC_X86_INS_CVTTPD2DQ, + UC_X86_INS_CVTTPS2DQ, + UC_X86_INS_CVTTSD2SI, + UC_X86_INS_CVTTSS2SI, + UC_X86_INS_CWD, + UC_X86_INS_CWDE, + UC_X86_INS_DAA, + UC_X86_INS_DAS, + UC_X86_INS_DATA16, + UC_X86_INS_DEC, + UC_X86_INS_DIV, + UC_X86_INS_DIVPD, + UC_X86_INS_DIVPS, + UC_X86_INS_FDIVR, + UC_X86_INS_FIDIVR, + UC_X86_INS_FDIVRP, + UC_X86_INS_DIVSD, + UC_X86_INS_DIVSS, + UC_X86_INS_FDIV, + UC_X86_INS_FIDIV, + UC_X86_INS_FDIVP, + UC_X86_INS_DPPD, + UC_X86_INS_DPPS, + UC_X86_INS_RET, + UC_X86_INS_ENCLS, + UC_X86_INS_ENCLU, + UC_X86_INS_ENTER, + UC_X86_INS_EXTRACTPS, + UC_X86_INS_EXTRQ, + UC_X86_INS_F2XM1, + UC_X86_INS_LCALL, + UC_X86_INS_LJMP, + UC_X86_INS_FBLD, + UC_X86_INS_FBSTP, + UC_X86_INS_FCOMPP, + UC_X86_INS_FDECSTP, + UC_X86_INS_FEMMS, + UC_X86_INS_FFREE, + UC_X86_INS_FICOM, + UC_X86_INS_FICOMP, + UC_X86_INS_FINCSTP, + UC_X86_INS_FLDCW, + UC_X86_INS_FLDENV, + UC_X86_INS_FLDL2E, + UC_X86_INS_FLDL2T, + UC_X86_INS_FLDLG2, + UC_X86_INS_FLDLN2, + UC_X86_INS_FLDPI, + UC_X86_INS_FNCLEX, + UC_X86_INS_FNINIT, + UC_X86_INS_FNOP, + UC_X86_INS_FNSTCW, + UC_X86_INS_FNSTSW, + UC_X86_INS_FPATAN, + UC_X86_INS_FPREM, + UC_X86_INS_FPREM1, + UC_X86_INS_FPTAN, + UC_X86_INS_FFREEP, + UC_X86_INS_FRNDINT, + UC_X86_INS_FRSTOR, + UC_X86_INS_FNSAVE, + UC_X86_INS_FSCALE, + UC_X86_INS_FSETPM, + UC_X86_INS_FSINCOS, + UC_X86_INS_FNSTENV, + UC_X86_INS_FXAM, + UC_X86_INS_FXRSTOR, + UC_X86_INS_FXRSTOR64, + UC_X86_INS_FXSAVE, + UC_X86_INS_FXSAVE64, + UC_X86_INS_FXTRACT, + UC_X86_INS_FYL2X, + UC_X86_INS_FYL2XP1, + UC_X86_INS_MOVAPD, + UC_X86_INS_MOVAPS, + UC_X86_INS_ORPD, + UC_X86_INS_ORPS, + UC_X86_INS_VMOVAPD, + UC_X86_INS_VMOVAPS, + UC_X86_INS_XORPD, + UC_X86_INS_XORPS, + UC_X86_INS_GETSEC, + UC_X86_INS_HADDPD, + UC_X86_INS_HADDPS, + UC_X86_INS_HLT, + UC_X86_INS_HSUBPD, + UC_X86_INS_HSUBPS, + UC_X86_INS_IDIV, + UC_X86_INS_FILD, + UC_X86_INS_IMUL, + UC_X86_INS_IN, + UC_X86_INS_INC, + UC_X86_INS_INSB, + UC_X86_INS_INSERTPS, + UC_X86_INS_INSERTQ, + UC_X86_INS_INSD, + UC_X86_INS_INSW, + UC_X86_INS_INT, + UC_X86_INS_INT1, + UC_X86_INS_INT3, + UC_X86_INS_INTO, + UC_X86_INS_INVD, + UC_X86_INS_INVEPT, + UC_X86_INS_INVLPG, + UC_X86_INS_INVLPGA, + UC_X86_INS_INVPCID, + UC_X86_INS_INVVPID, + UC_X86_INS_IRET, + UC_X86_INS_IRETD, + UC_X86_INS_IRETQ, + UC_X86_INS_FISTTP, + UC_X86_INS_FIST, + UC_X86_INS_FISTP, + UC_X86_INS_UCOMISD, + UC_X86_INS_UCOMISS, + UC_X86_INS_VCOMISD, + UC_X86_INS_VCOMISS, + UC_X86_INS_VCVTSD2SS, + UC_X86_INS_VCVTSI2SD, + UC_X86_INS_VCVTSI2SS, + UC_X86_INS_VCVTSS2SD, + UC_X86_INS_VCVTTSD2SI, + UC_X86_INS_VCVTTSD2USI, + UC_X86_INS_VCVTTSS2SI, + UC_X86_INS_VCVTTSS2USI, + UC_X86_INS_VCVTUSI2SD, + UC_X86_INS_VCVTUSI2SS, + UC_X86_INS_VUCOMISD, + UC_X86_INS_VUCOMISS, + UC_X86_INS_JAE, + UC_X86_INS_JA, + UC_X86_INS_JBE, + UC_X86_INS_JB, + UC_X86_INS_JCXZ, + UC_X86_INS_JECXZ, + UC_X86_INS_JE, + UC_X86_INS_JGE, + UC_X86_INS_JG, + UC_X86_INS_JLE, + UC_X86_INS_JL, + UC_X86_INS_JMP, + UC_X86_INS_JNE, + UC_X86_INS_JNO, + UC_X86_INS_JNP, + UC_X86_INS_JNS, + UC_X86_INS_JO, + UC_X86_INS_JP, + UC_X86_INS_JRCXZ, + UC_X86_INS_JS, + UC_X86_INS_KANDB, + UC_X86_INS_KANDD, + UC_X86_INS_KANDNB, + UC_X86_INS_KANDND, + UC_X86_INS_KANDNQ, + UC_X86_INS_KANDNW, + UC_X86_INS_KANDQ, + UC_X86_INS_KANDW, + UC_X86_INS_KMOVB, + UC_X86_INS_KMOVD, + UC_X86_INS_KMOVQ, + UC_X86_INS_KMOVW, + UC_X86_INS_KNOTB, + UC_X86_INS_KNOTD, + UC_X86_INS_KNOTQ, + UC_X86_INS_KNOTW, + UC_X86_INS_KORB, + UC_X86_INS_KORD, + UC_X86_INS_KORQ, + UC_X86_INS_KORTESTB, + UC_X86_INS_KORTESTD, + UC_X86_INS_KORTESTQ, + UC_X86_INS_KORTESTW, + UC_X86_INS_KORW, + UC_X86_INS_KSHIFTLB, + UC_X86_INS_KSHIFTLD, + UC_X86_INS_KSHIFTLQ, + UC_X86_INS_KSHIFTLW, + UC_X86_INS_KSHIFTRB, + UC_X86_INS_KSHIFTRD, + UC_X86_INS_KSHIFTRQ, + UC_X86_INS_KSHIFTRW, + UC_X86_INS_KUNPCKBW, + UC_X86_INS_KXNORB, + UC_X86_INS_KXNORD, + UC_X86_INS_KXNORQ, + UC_X86_INS_KXNORW, + UC_X86_INS_KXORB, + UC_X86_INS_KXORD, + UC_X86_INS_KXORQ, + UC_X86_INS_KXORW, + UC_X86_INS_LAHF, + UC_X86_INS_LAR, + UC_X86_INS_LDDQU, + UC_X86_INS_LDMXCSR, + UC_X86_INS_LDS, + UC_X86_INS_FLDZ, + UC_X86_INS_FLD1, + UC_X86_INS_FLD, + UC_X86_INS_LEA, + UC_X86_INS_LEAVE, + UC_X86_INS_LES, + UC_X86_INS_LFENCE, + UC_X86_INS_LFS, + UC_X86_INS_LGDT, + UC_X86_INS_LGS, + UC_X86_INS_LIDT, + UC_X86_INS_LLDT, + UC_X86_INS_LMSW, + UC_X86_INS_OR, + UC_X86_INS_SUB, + UC_X86_INS_XOR, + UC_X86_INS_LODSB, + UC_X86_INS_LODSD, + UC_X86_INS_LODSQ, + UC_X86_INS_LODSW, + UC_X86_INS_LOOP, + UC_X86_INS_LOOPE, + UC_X86_INS_LOOPNE, + UC_X86_INS_RETF, + UC_X86_INS_RETFQ, + UC_X86_INS_LSL, + UC_X86_INS_LSS, + UC_X86_INS_LTR, + UC_X86_INS_XADD, + UC_X86_INS_LZCNT, + UC_X86_INS_MASKMOVDQU, + UC_X86_INS_MAXPD, + UC_X86_INS_MAXPS, + UC_X86_INS_MAXSD, + UC_X86_INS_MAXSS, + UC_X86_INS_MFENCE, + UC_X86_INS_MINPD, + UC_X86_INS_MINPS, + UC_X86_INS_MINSD, + UC_X86_INS_MINSS, + UC_X86_INS_CVTPD2PI, + UC_X86_INS_CVTPI2PD, + UC_X86_INS_CVTPI2PS, + UC_X86_INS_CVTPS2PI, + UC_X86_INS_CVTTPD2PI, + UC_X86_INS_CVTTPS2PI, + UC_X86_INS_EMMS, + UC_X86_INS_MASKMOVQ, + UC_X86_INS_MOVD, + UC_X86_INS_MOVDQ2Q, + UC_X86_INS_MOVNTQ, + UC_X86_INS_MOVQ2DQ, + UC_X86_INS_MOVQ, + UC_X86_INS_PABSB, + UC_X86_INS_PABSD, + UC_X86_INS_PABSW, + UC_X86_INS_PACKSSDW, + UC_X86_INS_PACKSSWB, + UC_X86_INS_PACKUSWB, + UC_X86_INS_PADDB, + UC_X86_INS_PADDD, + UC_X86_INS_PADDQ, + UC_X86_INS_PADDSB, + UC_X86_INS_PADDSW, + UC_X86_INS_PADDUSB, + UC_X86_INS_PADDUSW, + UC_X86_INS_PADDW, + UC_X86_INS_PALIGNR, + UC_X86_INS_PANDN, + UC_X86_INS_PAND, + UC_X86_INS_PAVGB, + UC_X86_INS_PAVGW, + UC_X86_INS_PCMPEQB, + UC_X86_INS_PCMPEQD, + UC_X86_INS_PCMPEQW, + UC_X86_INS_PCMPGTB, + UC_X86_INS_PCMPGTD, + UC_X86_INS_PCMPGTW, + UC_X86_INS_PEXTRW, + UC_X86_INS_PHADDSW, + UC_X86_INS_PHADDW, + UC_X86_INS_PHADDD, + UC_X86_INS_PHSUBD, + UC_X86_INS_PHSUBSW, + UC_X86_INS_PHSUBW, + UC_X86_INS_PINSRW, + UC_X86_INS_PMADDUBSW, + UC_X86_INS_PMADDWD, + UC_X86_INS_PMAXSW, + UC_X86_INS_PMAXUB, + UC_X86_INS_PMINSW, + UC_X86_INS_PMINUB, + UC_X86_INS_PMOVMSKB, + UC_X86_INS_PMULHRSW, + UC_X86_INS_PMULHUW, + UC_X86_INS_PMULHW, + UC_X86_INS_PMULLW, + UC_X86_INS_PMULUDQ, + UC_X86_INS_POR, + UC_X86_INS_PSADBW, + UC_X86_INS_PSHUFB, + UC_X86_INS_PSHUFW, + UC_X86_INS_PSIGNB, + UC_X86_INS_PSIGND, + UC_X86_INS_PSIGNW, + UC_X86_INS_PSLLD, + UC_X86_INS_PSLLQ, + UC_X86_INS_PSLLW, + UC_X86_INS_PSRAD, + UC_X86_INS_PSRAW, + UC_X86_INS_PSRLD, + UC_X86_INS_PSRLQ, + UC_X86_INS_PSRLW, + UC_X86_INS_PSUBB, + UC_X86_INS_PSUBD, + UC_X86_INS_PSUBQ, + UC_X86_INS_PSUBSB, + UC_X86_INS_PSUBSW, + UC_X86_INS_PSUBUSB, + UC_X86_INS_PSUBUSW, + UC_X86_INS_PSUBW, + UC_X86_INS_PUNPCKHBW, + UC_X86_INS_PUNPCKHDQ, + UC_X86_INS_PUNPCKHWD, + UC_X86_INS_PUNPCKLBW, + UC_X86_INS_PUNPCKLDQ, + UC_X86_INS_PUNPCKLWD, + UC_X86_INS_PXOR, + UC_X86_INS_MONITOR, + UC_X86_INS_MONTMUL, + UC_X86_INS_MOV, + UC_X86_INS_MOVABS, + UC_X86_INS_MOVBE, + UC_X86_INS_MOVDDUP, + UC_X86_INS_MOVDQA, + UC_X86_INS_MOVDQU, + UC_X86_INS_MOVHLPS, + UC_X86_INS_MOVHPD, + UC_X86_INS_MOVHPS, + UC_X86_INS_MOVLHPS, + UC_X86_INS_MOVLPD, + UC_X86_INS_MOVLPS, + UC_X86_INS_MOVMSKPD, + UC_X86_INS_MOVMSKPS, + UC_X86_INS_MOVNTDQA, + UC_X86_INS_MOVNTDQ, + UC_X86_INS_MOVNTI, + UC_X86_INS_MOVNTPD, + UC_X86_INS_MOVNTPS, + UC_X86_INS_MOVNTSD, + UC_X86_INS_MOVNTSS, + UC_X86_INS_MOVSB, + UC_X86_INS_MOVSD, + UC_X86_INS_MOVSHDUP, + UC_X86_INS_MOVSLDUP, + UC_X86_INS_MOVSQ, + UC_X86_INS_MOVSS, + UC_X86_INS_MOVSW, + UC_X86_INS_MOVSX, + UC_X86_INS_MOVSXD, + UC_X86_INS_MOVUPD, + UC_X86_INS_MOVUPS, + UC_X86_INS_MOVZX, + UC_X86_INS_MPSADBW, + UC_X86_INS_MUL, + UC_X86_INS_MULPD, + UC_X86_INS_MULPS, + UC_X86_INS_MULSD, + UC_X86_INS_MULSS, + UC_X86_INS_MULX, + UC_X86_INS_FMUL, + UC_X86_INS_FIMUL, + UC_X86_INS_FMULP, + UC_X86_INS_MWAIT, + UC_X86_INS_NEG, + UC_X86_INS_NOP, + UC_X86_INS_NOT, + UC_X86_INS_OUT, + UC_X86_INS_OUTSB, + UC_X86_INS_OUTSD, + UC_X86_INS_OUTSW, + UC_X86_INS_PACKUSDW, + UC_X86_INS_PAUSE, + UC_X86_INS_PAVGUSB, + UC_X86_INS_PBLENDVB, + UC_X86_INS_PBLENDW, + UC_X86_INS_PCLMULQDQ, + UC_X86_INS_PCMPEQQ, + UC_X86_INS_PCMPESTRI, + UC_X86_INS_PCMPESTRM, + UC_X86_INS_PCMPGTQ, + UC_X86_INS_PCMPISTRI, + UC_X86_INS_PCMPISTRM, + UC_X86_INS_PCOMMIT, + UC_X86_INS_PDEP, + UC_X86_INS_PEXT, + UC_X86_INS_PEXTRB, + UC_X86_INS_PEXTRD, + UC_X86_INS_PEXTRQ, + UC_X86_INS_PF2ID, + UC_X86_INS_PF2IW, + UC_X86_INS_PFACC, + UC_X86_INS_PFADD, + UC_X86_INS_PFCMPEQ, + UC_X86_INS_PFCMPGE, + UC_X86_INS_PFCMPGT, + UC_X86_INS_PFMAX, + UC_X86_INS_PFMIN, + UC_X86_INS_PFMUL, + UC_X86_INS_PFNACC, + UC_X86_INS_PFPNACC, + UC_X86_INS_PFRCPIT1, + UC_X86_INS_PFRCPIT2, + UC_X86_INS_PFRCP, + UC_X86_INS_PFRSQIT1, + UC_X86_INS_PFRSQRT, + UC_X86_INS_PFSUBR, + UC_X86_INS_PFSUB, + UC_X86_INS_PHMINPOSUW, + UC_X86_INS_PI2FD, + UC_X86_INS_PI2FW, + UC_X86_INS_PINSRB, + UC_X86_INS_PINSRD, + UC_X86_INS_PINSRQ, + UC_X86_INS_PMAXSB, + UC_X86_INS_PMAXSD, + UC_X86_INS_PMAXUD, + UC_X86_INS_PMAXUW, + UC_X86_INS_PMINSB, + UC_X86_INS_PMINSD, + UC_X86_INS_PMINUD, + UC_X86_INS_PMINUW, + UC_X86_INS_PMOVSXBD, + UC_X86_INS_PMOVSXBQ, + UC_X86_INS_PMOVSXBW, + UC_X86_INS_PMOVSXDQ, + UC_X86_INS_PMOVSXWD, + UC_X86_INS_PMOVSXWQ, + UC_X86_INS_PMOVZXBD, + UC_X86_INS_PMOVZXBQ, + UC_X86_INS_PMOVZXBW, + UC_X86_INS_PMOVZXDQ, + UC_X86_INS_PMOVZXWD, + UC_X86_INS_PMOVZXWQ, + UC_X86_INS_PMULDQ, + UC_X86_INS_PMULHRW, + UC_X86_INS_PMULLD, + UC_X86_INS_POP, + UC_X86_INS_POPAW, + UC_X86_INS_POPAL, + UC_X86_INS_POPCNT, + UC_X86_INS_POPF, + UC_X86_INS_POPFD, + UC_X86_INS_POPFQ, + UC_X86_INS_PREFETCH, + UC_X86_INS_PREFETCHNTA, + UC_X86_INS_PREFETCHT0, + UC_X86_INS_PREFETCHT1, + UC_X86_INS_PREFETCHT2, + UC_X86_INS_PREFETCHW, + UC_X86_INS_PSHUFD, + UC_X86_INS_PSHUFHW, + UC_X86_INS_PSHUFLW, + UC_X86_INS_PSLLDQ, + UC_X86_INS_PSRLDQ, + UC_X86_INS_PSWAPD, + UC_X86_INS_PTEST, + UC_X86_INS_PUNPCKHQDQ, + UC_X86_INS_PUNPCKLQDQ, + UC_X86_INS_PUSH, + UC_X86_INS_PUSHAW, + UC_X86_INS_PUSHAL, + UC_X86_INS_PUSHF, + UC_X86_INS_PUSHFD, + UC_X86_INS_PUSHFQ, + UC_X86_INS_RCL, + UC_X86_INS_RCPPS, + UC_X86_INS_RCPSS, + UC_X86_INS_RCR, + UC_X86_INS_RDFSBASE, + UC_X86_INS_RDGSBASE, + UC_X86_INS_RDMSR, + UC_X86_INS_RDPMC, + UC_X86_INS_RDRAND, + UC_X86_INS_RDSEED, + UC_X86_INS_RDTSC, + UC_X86_INS_RDTSCP, + UC_X86_INS_ROL, + UC_X86_INS_ROR, + UC_X86_INS_RORX, + UC_X86_INS_ROUNDPD, + UC_X86_INS_ROUNDPS, + UC_X86_INS_ROUNDSD, + UC_X86_INS_ROUNDSS, + UC_X86_INS_RSM, + UC_X86_INS_RSQRTPS, + UC_X86_INS_RSQRTSS, + UC_X86_INS_SAHF, + UC_X86_INS_SAL, + UC_X86_INS_SALC, + UC_X86_INS_SAR, + UC_X86_INS_SARX, + UC_X86_INS_SBB, + UC_X86_INS_SCASB, + UC_X86_INS_SCASD, + UC_X86_INS_SCASQ, + UC_X86_INS_SCASW, + UC_X86_INS_SETAE, + UC_X86_INS_SETA, + UC_X86_INS_SETBE, + UC_X86_INS_SETB, + UC_X86_INS_SETE, + UC_X86_INS_SETGE, + UC_X86_INS_SETG, + UC_X86_INS_SETLE, + UC_X86_INS_SETL, + UC_X86_INS_SETNE, + UC_X86_INS_SETNO, + UC_X86_INS_SETNP, + UC_X86_INS_SETNS, + UC_X86_INS_SETO, + UC_X86_INS_SETP, + UC_X86_INS_SETS, + UC_X86_INS_SFENCE, + UC_X86_INS_SGDT, + UC_X86_INS_SHA1MSG1, + UC_X86_INS_SHA1MSG2, + UC_X86_INS_SHA1NEXTE, + UC_X86_INS_SHA1RNDS4, + UC_X86_INS_SHA256MSG1, + UC_X86_INS_SHA256MSG2, + UC_X86_INS_SHA256RNDS2, + UC_X86_INS_SHL, + UC_X86_INS_SHLD, + UC_X86_INS_SHLX, + UC_X86_INS_SHR, + UC_X86_INS_SHRD, + UC_X86_INS_SHRX, + UC_X86_INS_SHUFPD, + UC_X86_INS_SHUFPS, + UC_X86_INS_SIDT, + UC_X86_INS_FSIN, + UC_X86_INS_SKINIT, + UC_X86_INS_SLDT, + UC_X86_INS_SMSW, + UC_X86_INS_SQRTPD, + UC_X86_INS_SQRTPS, + UC_X86_INS_SQRTSD, + UC_X86_INS_SQRTSS, + UC_X86_INS_FSQRT, + UC_X86_INS_STAC, + UC_X86_INS_STC, + UC_X86_INS_STD, + UC_X86_INS_STGI, + UC_X86_INS_STI, + UC_X86_INS_STMXCSR, + UC_X86_INS_STOSB, + UC_X86_INS_STOSD, + UC_X86_INS_STOSQ, + UC_X86_INS_STOSW, + UC_X86_INS_STR, + UC_X86_INS_FST, + UC_X86_INS_FSTP, + UC_X86_INS_FSTPNCE, + UC_X86_INS_FXCH, + UC_X86_INS_SUBPD, + UC_X86_INS_SUBPS, + UC_X86_INS_FSUBR, + UC_X86_INS_FISUBR, + UC_X86_INS_FSUBRP, + UC_X86_INS_SUBSD, + UC_X86_INS_SUBSS, + UC_X86_INS_FSUB, + UC_X86_INS_FISUB, + UC_X86_INS_FSUBP, + UC_X86_INS_SWAPGS, + UC_X86_INS_SYSCALL, + UC_X86_INS_SYSENTER, + UC_X86_INS_SYSEXIT, + UC_X86_INS_SYSRET, + UC_X86_INS_T1MSKC, + UC_X86_INS_TEST, + UC_X86_INS_UD2, + UC_X86_INS_FTST, + UC_X86_INS_TZCNT, + UC_X86_INS_TZMSK, + UC_X86_INS_FUCOMPI, + UC_X86_INS_FUCOMI, + UC_X86_INS_FUCOMPP, + UC_X86_INS_FUCOMP, + UC_X86_INS_FUCOM, + UC_X86_INS_UD2B, + UC_X86_INS_UNPCKHPD, + UC_X86_INS_UNPCKHPS, + UC_X86_INS_UNPCKLPD, + UC_X86_INS_UNPCKLPS, + UC_X86_INS_VADDPD, + UC_X86_INS_VADDPS, + UC_X86_INS_VADDSD, + UC_X86_INS_VADDSS, + UC_X86_INS_VADDSUBPD, + UC_X86_INS_VADDSUBPS, + UC_X86_INS_VAESDECLAST, + UC_X86_INS_VAESDEC, + UC_X86_INS_VAESENCLAST, + UC_X86_INS_VAESENC, + UC_X86_INS_VAESIMC, + UC_X86_INS_VAESKEYGENASSIST, + UC_X86_INS_VALIGND, + UC_X86_INS_VALIGNQ, + UC_X86_INS_VANDNPD, + UC_X86_INS_VANDNPS, + UC_X86_INS_VANDPD, + UC_X86_INS_VANDPS, + UC_X86_INS_VBLENDMPD, + UC_X86_INS_VBLENDMPS, + UC_X86_INS_VBLENDPD, + UC_X86_INS_VBLENDPS, + UC_X86_INS_VBLENDVPD, + UC_X86_INS_VBLENDVPS, + UC_X86_INS_VBROADCASTF128, + UC_X86_INS_VBROADCASTI32X4, + UC_X86_INS_VBROADCASTI64X4, + UC_X86_INS_VBROADCASTSD, + UC_X86_INS_VBROADCASTSS, + UC_X86_INS_VCMPPD, + UC_X86_INS_VCMPPS, + UC_X86_INS_VCMPSD, + UC_X86_INS_VCMPSS, + UC_X86_INS_VCOMPRESSPD, + UC_X86_INS_VCOMPRESSPS, + UC_X86_INS_VCVTDQ2PD, + UC_X86_INS_VCVTDQ2PS, + UC_X86_INS_VCVTPD2DQX, + UC_X86_INS_VCVTPD2DQ, + UC_X86_INS_VCVTPD2PSX, + UC_X86_INS_VCVTPD2PS, + UC_X86_INS_VCVTPD2UDQ, + UC_X86_INS_VCVTPH2PS, + UC_X86_INS_VCVTPS2DQ, + UC_X86_INS_VCVTPS2PD, + UC_X86_INS_VCVTPS2PH, + UC_X86_INS_VCVTPS2UDQ, + UC_X86_INS_VCVTSD2SI, + UC_X86_INS_VCVTSD2USI, + UC_X86_INS_VCVTSS2SI, + UC_X86_INS_VCVTSS2USI, + UC_X86_INS_VCVTTPD2DQX, + UC_X86_INS_VCVTTPD2DQ, + UC_X86_INS_VCVTTPD2UDQ, + UC_X86_INS_VCVTTPS2DQ, + UC_X86_INS_VCVTTPS2UDQ, + UC_X86_INS_VCVTUDQ2PD, + UC_X86_INS_VCVTUDQ2PS, + UC_X86_INS_VDIVPD, + UC_X86_INS_VDIVPS, + UC_X86_INS_VDIVSD, + UC_X86_INS_VDIVSS, + UC_X86_INS_VDPPD, + UC_X86_INS_VDPPS, + UC_X86_INS_VERR, + UC_X86_INS_VERW, + UC_X86_INS_VEXP2PD, + UC_X86_INS_VEXP2PS, + UC_X86_INS_VEXPANDPD, + UC_X86_INS_VEXPANDPS, + UC_X86_INS_VEXTRACTF128, + UC_X86_INS_VEXTRACTF32X4, + UC_X86_INS_VEXTRACTF64X4, + UC_X86_INS_VEXTRACTI128, + UC_X86_INS_VEXTRACTI32X4, + UC_X86_INS_VEXTRACTI64X4, + UC_X86_INS_VEXTRACTPS, + UC_X86_INS_VFMADD132PD, + UC_X86_INS_VFMADD132PS, + UC_X86_INS_VFMADDPD, + UC_X86_INS_VFMADD213PD, + UC_X86_INS_VFMADD231PD, + UC_X86_INS_VFMADDPS, + UC_X86_INS_VFMADD213PS, + UC_X86_INS_VFMADD231PS, + UC_X86_INS_VFMADDSD, + UC_X86_INS_VFMADD213SD, + UC_X86_INS_VFMADD132SD, + UC_X86_INS_VFMADD231SD, + UC_X86_INS_VFMADDSS, + UC_X86_INS_VFMADD213SS, + UC_X86_INS_VFMADD132SS, + UC_X86_INS_VFMADD231SS, + UC_X86_INS_VFMADDSUB132PD, + UC_X86_INS_VFMADDSUB132PS, + UC_X86_INS_VFMADDSUBPD, + UC_X86_INS_VFMADDSUB213PD, + UC_X86_INS_VFMADDSUB231PD, + UC_X86_INS_VFMADDSUBPS, + UC_X86_INS_VFMADDSUB213PS, + UC_X86_INS_VFMADDSUB231PS, + UC_X86_INS_VFMSUB132PD, + UC_X86_INS_VFMSUB132PS, + UC_X86_INS_VFMSUBADD132PD, + UC_X86_INS_VFMSUBADD132PS, + UC_X86_INS_VFMSUBADDPD, + UC_X86_INS_VFMSUBADD213PD, + UC_X86_INS_VFMSUBADD231PD, + UC_X86_INS_VFMSUBADDPS, + UC_X86_INS_VFMSUBADD213PS, + UC_X86_INS_VFMSUBADD231PS, + UC_X86_INS_VFMSUBPD, + UC_X86_INS_VFMSUB213PD, + UC_X86_INS_VFMSUB231PD, + UC_X86_INS_VFMSUBPS, + UC_X86_INS_VFMSUB213PS, + UC_X86_INS_VFMSUB231PS, + UC_X86_INS_VFMSUBSD, + UC_X86_INS_VFMSUB213SD, + UC_X86_INS_VFMSUB132SD, + UC_X86_INS_VFMSUB231SD, + UC_X86_INS_VFMSUBSS, + UC_X86_INS_VFMSUB213SS, + UC_X86_INS_VFMSUB132SS, + UC_X86_INS_VFMSUB231SS, + UC_X86_INS_VFNMADD132PD, + UC_X86_INS_VFNMADD132PS, + UC_X86_INS_VFNMADDPD, + UC_X86_INS_VFNMADD213PD, + UC_X86_INS_VFNMADD231PD, + UC_X86_INS_VFNMADDPS, + UC_X86_INS_VFNMADD213PS, + UC_X86_INS_VFNMADD231PS, + UC_X86_INS_VFNMADDSD, + UC_X86_INS_VFNMADD213SD, + UC_X86_INS_VFNMADD132SD, + UC_X86_INS_VFNMADD231SD, + UC_X86_INS_VFNMADDSS, + UC_X86_INS_VFNMADD213SS, + UC_X86_INS_VFNMADD132SS, + UC_X86_INS_VFNMADD231SS, + UC_X86_INS_VFNMSUB132PD, + UC_X86_INS_VFNMSUB132PS, + UC_X86_INS_VFNMSUBPD, + UC_X86_INS_VFNMSUB213PD, + UC_X86_INS_VFNMSUB231PD, + UC_X86_INS_VFNMSUBPS, + UC_X86_INS_VFNMSUB213PS, + UC_X86_INS_VFNMSUB231PS, + UC_X86_INS_VFNMSUBSD, + UC_X86_INS_VFNMSUB213SD, + UC_X86_INS_VFNMSUB132SD, + UC_X86_INS_VFNMSUB231SD, + UC_X86_INS_VFNMSUBSS, + UC_X86_INS_VFNMSUB213SS, + UC_X86_INS_VFNMSUB132SS, + UC_X86_INS_VFNMSUB231SS, + UC_X86_INS_VFRCZPD, + UC_X86_INS_VFRCZPS, + UC_X86_INS_VFRCZSD, + UC_X86_INS_VFRCZSS, + UC_X86_INS_VORPD, + UC_X86_INS_VORPS, + UC_X86_INS_VXORPD, + UC_X86_INS_VXORPS, + UC_X86_INS_VGATHERDPD, + UC_X86_INS_VGATHERDPS, + UC_X86_INS_VGATHERPF0DPD, + UC_X86_INS_VGATHERPF0DPS, + UC_X86_INS_VGATHERPF0QPD, + UC_X86_INS_VGATHERPF0QPS, + UC_X86_INS_VGATHERPF1DPD, + UC_X86_INS_VGATHERPF1DPS, + UC_X86_INS_VGATHERPF1QPD, + UC_X86_INS_VGATHERPF1QPS, + UC_X86_INS_VGATHERQPD, + UC_X86_INS_VGATHERQPS, + UC_X86_INS_VHADDPD, + UC_X86_INS_VHADDPS, + UC_X86_INS_VHSUBPD, + UC_X86_INS_VHSUBPS, + UC_X86_INS_VINSERTF128, + UC_X86_INS_VINSERTF32X4, + UC_X86_INS_VINSERTF32X8, + UC_X86_INS_VINSERTF64X2, + UC_X86_INS_VINSERTF64X4, + UC_X86_INS_VINSERTI128, + UC_X86_INS_VINSERTI32X4, + UC_X86_INS_VINSERTI32X8, + UC_X86_INS_VINSERTI64X2, + UC_X86_INS_VINSERTI64X4, + UC_X86_INS_VINSERTPS, + UC_X86_INS_VLDDQU, + UC_X86_INS_VLDMXCSR, + UC_X86_INS_VMASKMOVDQU, + UC_X86_INS_VMASKMOVPD, + UC_X86_INS_VMASKMOVPS, + UC_X86_INS_VMAXPD, + UC_X86_INS_VMAXPS, + UC_X86_INS_VMAXSD, + UC_X86_INS_VMAXSS, + UC_X86_INS_VMCALL, + UC_X86_INS_VMCLEAR, + UC_X86_INS_VMFUNC, + UC_X86_INS_VMINPD, + UC_X86_INS_VMINPS, + UC_X86_INS_VMINSD, + UC_X86_INS_VMINSS, + UC_X86_INS_VMLAUNCH, + UC_X86_INS_VMLOAD, + UC_X86_INS_VMMCALL, + UC_X86_INS_VMOVQ, + UC_X86_INS_VMOVDDUP, + UC_X86_INS_VMOVD, + UC_X86_INS_VMOVDQA32, + UC_X86_INS_VMOVDQA64, + UC_X86_INS_VMOVDQA, + UC_X86_INS_VMOVDQU16, + UC_X86_INS_VMOVDQU32, + UC_X86_INS_VMOVDQU64, + UC_X86_INS_VMOVDQU8, + UC_X86_INS_VMOVDQU, + UC_X86_INS_VMOVHLPS, + UC_X86_INS_VMOVHPD, + UC_X86_INS_VMOVHPS, + UC_X86_INS_VMOVLHPS, + UC_X86_INS_VMOVLPD, + UC_X86_INS_VMOVLPS, + UC_X86_INS_VMOVMSKPD, + UC_X86_INS_VMOVMSKPS, + UC_X86_INS_VMOVNTDQA, + UC_X86_INS_VMOVNTDQ, + UC_X86_INS_VMOVNTPD, + UC_X86_INS_VMOVNTPS, + UC_X86_INS_VMOVSD, + UC_X86_INS_VMOVSHDUP, + UC_X86_INS_VMOVSLDUP, + UC_X86_INS_VMOVSS, + UC_X86_INS_VMOVUPD, + UC_X86_INS_VMOVUPS, + UC_X86_INS_VMPSADBW, + UC_X86_INS_VMPTRLD, + UC_X86_INS_VMPTRST, + UC_X86_INS_VMREAD, + UC_X86_INS_VMRESUME, + UC_X86_INS_VMRUN, + UC_X86_INS_VMSAVE, + UC_X86_INS_VMULPD, + UC_X86_INS_VMULPS, + UC_X86_INS_VMULSD, + UC_X86_INS_VMULSS, + UC_X86_INS_VMWRITE, + UC_X86_INS_VMXOFF, + UC_X86_INS_VMXON, + UC_X86_INS_VPABSB, + UC_X86_INS_VPABSD, + UC_X86_INS_VPABSQ, + UC_X86_INS_VPABSW, + UC_X86_INS_VPACKSSDW, + UC_X86_INS_VPACKSSWB, + UC_X86_INS_VPACKUSDW, + UC_X86_INS_VPACKUSWB, + UC_X86_INS_VPADDB, + UC_X86_INS_VPADDD, + UC_X86_INS_VPADDQ, + UC_X86_INS_VPADDSB, + UC_X86_INS_VPADDSW, + UC_X86_INS_VPADDUSB, + UC_X86_INS_VPADDUSW, + UC_X86_INS_VPADDW, + UC_X86_INS_VPALIGNR, + UC_X86_INS_VPANDD, + UC_X86_INS_VPANDND, + UC_X86_INS_VPANDNQ, + UC_X86_INS_VPANDN, + UC_X86_INS_VPANDQ, + UC_X86_INS_VPAND, + UC_X86_INS_VPAVGB, + UC_X86_INS_VPAVGW, + UC_X86_INS_VPBLENDD, + UC_X86_INS_VPBLENDMB, + UC_X86_INS_VPBLENDMD, + UC_X86_INS_VPBLENDMQ, + UC_X86_INS_VPBLENDMW, + UC_X86_INS_VPBLENDVB, + UC_X86_INS_VPBLENDW, + UC_X86_INS_VPBROADCASTB, + UC_X86_INS_VPBROADCASTD, + UC_X86_INS_VPBROADCASTMB2Q, + UC_X86_INS_VPBROADCASTMW2D, + UC_X86_INS_VPBROADCASTQ, + UC_X86_INS_VPBROADCASTW, + UC_X86_INS_VPCLMULQDQ, + UC_X86_INS_VPCMOV, + UC_X86_INS_VPCMPB, + UC_X86_INS_VPCMPD, + UC_X86_INS_VPCMPEQB, + UC_X86_INS_VPCMPEQD, + UC_X86_INS_VPCMPEQQ, + UC_X86_INS_VPCMPEQW, + UC_X86_INS_VPCMPESTRI, + UC_X86_INS_VPCMPESTRM, + UC_X86_INS_VPCMPGTB, + UC_X86_INS_VPCMPGTD, + UC_X86_INS_VPCMPGTQ, + UC_X86_INS_VPCMPGTW, + UC_X86_INS_VPCMPISTRI, + UC_X86_INS_VPCMPISTRM, + UC_X86_INS_VPCMPQ, + UC_X86_INS_VPCMPUB, + UC_X86_INS_VPCMPUD, + UC_X86_INS_VPCMPUQ, + UC_X86_INS_VPCMPUW, + UC_X86_INS_VPCMPW, + UC_X86_INS_VPCOMB, + UC_X86_INS_VPCOMD, + UC_X86_INS_VPCOMPRESSD, + UC_X86_INS_VPCOMPRESSQ, + UC_X86_INS_VPCOMQ, + UC_X86_INS_VPCOMUB, + UC_X86_INS_VPCOMUD, + UC_X86_INS_VPCOMUQ, + UC_X86_INS_VPCOMUW, + UC_X86_INS_VPCOMW, + UC_X86_INS_VPCONFLICTD, + UC_X86_INS_VPCONFLICTQ, + UC_X86_INS_VPERM2F128, + UC_X86_INS_VPERM2I128, + UC_X86_INS_VPERMD, + UC_X86_INS_VPERMI2D, + UC_X86_INS_VPERMI2PD, + UC_X86_INS_VPERMI2PS, + UC_X86_INS_VPERMI2Q, + UC_X86_INS_VPERMIL2PD, + UC_X86_INS_VPERMIL2PS, + UC_X86_INS_VPERMILPD, + UC_X86_INS_VPERMILPS, + UC_X86_INS_VPERMPD, + UC_X86_INS_VPERMPS, + UC_X86_INS_VPERMQ, + UC_X86_INS_VPERMT2D, + UC_X86_INS_VPERMT2PD, + UC_X86_INS_VPERMT2PS, + UC_X86_INS_VPERMT2Q, + UC_X86_INS_VPEXPANDD, + UC_X86_INS_VPEXPANDQ, + UC_X86_INS_VPEXTRB, + UC_X86_INS_VPEXTRD, + UC_X86_INS_VPEXTRQ, + UC_X86_INS_VPEXTRW, + UC_X86_INS_VPGATHERDD, + UC_X86_INS_VPGATHERDQ, + UC_X86_INS_VPGATHERQD, + UC_X86_INS_VPGATHERQQ, + UC_X86_INS_VPHADDBD, + UC_X86_INS_VPHADDBQ, + UC_X86_INS_VPHADDBW, + UC_X86_INS_VPHADDDQ, + UC_X86_INS_VPHADDD, + UC_X86_INS_VPHADDSW, + UC_X86_INS_VPHADDUBD, + UC_X86_INS_VPHADDUBQ, + UC_X86_INS_VPHADDUBW, + UC_X86_INS_VPHADDUDQ, + UC_X86_INS_VPHADDUWD, + UC_X86_INS_VPHADDUWQ, + UC_X86_INS_VPHADDWD, + UC_X86_INS_VPHADDWQ, + UC_X86_INS_VPHADDW, + UC_X86_INS_VPHMINPOSUW, + UC_X86_INS_VPHSUBBW, + UC_X86_INS_VPHSUBDQ, + UC_X86_INS_VPHSUBD, + UC_X86_INS_VPHSUBSW, + UC_X86_INS_VPHSUBWD, + UC_X86_INS_VPHSUBW, + UC_X86_INS_VPINSRB, + UC_X86_INS_VPINSRD, + UC_X86_INS_VPINSRQ, + UC_X86_INS_VPINSRW, + UC_X86_INS_VPLZCNTD, + UC_X86_INS_VPLZCNTQ, + UC_X86_INS_VPMACSDD, + UC_X86_INS_VPMACSDQH, + UC_X86_INS_VPMACSDQL, + UC_X86_INS_VPMACSSDD, + UC_X86_INS_VPMACSSDQH, + UC_X86_INS_VPMACSSDQL, + UC_X86_INS_VPMACSSWD, + UC_X86_INS_VPMACSSWW, + UC_X86_INS_VPMACSWD, + UC_X86_INS_VPMACSWW, + UC_X86_INS_VPMADCSSWD, + UC_X86_INS_VPMADCSWD, + UC_X86_INS_VPMADDUBSW, + UC_X86_INS_VPMADDWD, + UC_X86_INS_VPMASKMOVD, + UC_X86_INS_VPMASKMOVQ, + UC_X86_INS_VPMAXSB, + UC_X86_INS_VPMAXSD, + UC_X86_INS_VPMAXSQ, + UC_X86_INS_VPMAXSW, + UC_X86_INS_VPMAXUB, + UC_X86_INS_VPMAXUD, + UC_X86_INS_VPMAXUQ, + UC_X86_INS_VPMAXUW, + UC_X86_INS_VPMINSB, + UC_X86_INS_VPMINSD, + UC_X86_INS_VPMINSQ, + UC_X86_INS_VPMINSW, + UC_X86_INS_VPMINUB, + UC_X86_INS_VPMINUD, + UC_X86_INS_VPMINUQ, + UC_X86_INS_VPMINUW, + UC_X86_INS_VPMOVDB, + UC_X86_INS_VPMOVDW, + UC_X86_INS_VPMOVM2B, + UC_X86_INS_VPMOVM2D, + UC_X86_INS_VPMOVM2Q, + UC_X86_INS_VPMOVM2W, + UC_X86_INS_VPMOVMSKB, + UC_X86_INS_VPMOVQB, + UC_X86_INS_VPMOVQD, + UC_X86_INS_VPMOVQW, + UC_X86_INS_VPMOVSDB, + UC_X86_INS_VPMOVSDW, + UC_X86_INS_VPMOVSQB, + UC_X86_INS_VPMOVSQD, + UC_X86_INS_VPMOVSQW, + UC_X86_INS_VPMOVSXBD, + UC_X86_INS_VPMOVSXBQ, + UC_X86_INS_VPMOVSXBW, + UC_X86_INS_VPMOVSXDQ, + UC_X86_INS_VPMOVSXWD, + UC_X86_INS_VPMOVSXWQ, + UC_X86_INS_VPMOVUSDB, + UC_X86_INS_VPMOVUSDW, + UC_X86_INS_VPMOVUSQB, + UC_X86_INS_VPMOVUSQD, + UC_X86_INS_VPMOVUSQW, + UC_X86_INS_VPMOVZXBD, + UC_X86_INS_VPMOVZXBQ, + UC_X86_INS_VPMOVZXBW, + UC_X86_INS_VPMOVZXDQ, + UC_X86_INS_VPMOVZXWD, + UC_X86_INS_VPMOVZXWQ, + UC_X86_INS_VPMULDQ, + UC_X86_INS_VPMULHRSW, + UC_X86_INS_VPMULHUW, + UC_X86_INS_VPMULHW, + UC_X86_INS_VPMULLD, + UC_X86_INS_VPMULLQ, + UC_X86_INS_VPMULLW, + UC_X86_INS_VPMULUDQ, + UC_X86_INS_VPORD, + UC_X86_INS_VPORQ, + UC_X86_INS_VPOR, + UC_X86_INS_VPPERM, + UC_X86_INS_VPROTB, + UC_X86_INS_VPROTD, + UC_X86_INS_VPROTQ, + UC_X86_INS_VPROTW, + UC_X86_INS_VPSADBW, + UC_X86_INS_VPSCATTERDD, + UC_X86_INS_VPSCATTERDQ, + UC_X86_INS_VPSCATTERQD, + UC_X86_INS_VPSCATTERQQ, + UC_X86_INS_VPSHAB, + UC_X86_INS_VPSHAD, + UC_X86_INS_VPSHAQ, + UC_X86_INS_VPSHAW, + UC_X86_INS_VPSHLB, + UC_X86_INS_VPSHLD, + UC_X86_INS_VPSHLQ, + UC_X86_INS_VPSHLW, + UC_X86_INS_VPSHUFB, + UC_X86_INS_VPSHUFD, + UC_X86_INS_VPSHUFHW, + UC_X86_INS_VPSHUFLW, + UC_X86_INS_VPSIGNB, + UC_X86_INS_VPSIGND, + UC_X86_INS_VPSIGNW, + UC_X86_INS_VPSLLDQ, + UC_X86_INS_VPSLLD, + UC_X86_INS_VPSLLQ, + UC_X86_INS_VPSLLVD, + UC_X86_INS_VPSLLVQ, + UC_X86_INS_VPSLLW, + UC_X86_INS_VPSRAD, + UC_X86_INS_VPSRAQ, + UC_X86_INS_VPSRAVD, + UC_X86_INS_VPSRAVQ, + UC_X86_INS_VPSRAW, + UC_X86_INS_VPSRLDQ, + UC_X86_INS_VPSRLD, + UC_X86_INS_VPSRLQ, + UC_X86_INS_VPSRLVD, + UC_X86_INS_VPSRLVQ, + UC_X86_INS_VPSRLW, + UC_X86_INS_VPSUBB, + UC_X86_INS_VPSUBD, + UC_X86_INS_VPSUBQ, + UC_X86_INS_VPSUBSB, + UC_X86_INS_VPSUBSW, + UC_X86_INS_VPSUBUSB, + UC_X86_INS_VPSUBUSW, + UC_X86_INS_VPSUBW, + UC_X86_INS_VPTESTMD, + UC_X86_INS_VPTESTMQ, + UC_X86_INS_VPTESTNMD, + UC_X86_INS_VPTESTNMQ, + UC_X86_INS_VPTEST, + UC_X86_INS_VPUNPCKHBW, + UC_X86_INS_VPUNPCKHDQ, + UC_X86_INS_VPUNPCKHQDQ, + UC_X86_INS_VPUNPCKHWD, + UC_X86_INS_VPUNPCKLBW, + UC_X86_INS_VPUNPCKLDQ, + UC_X86_INS_VPUNPCKLQDQ, + UC_X86_INS_VPUNPCKLWD, + UC_X86_INS_VPXORD, + UC_X86_INS_VPXORQ, + UC_X86_INS_VPXOR, + UC_X86_INS_VRCP14PD, + UC_X86_INS_VRCP14PS, + UC_X86_INS_VRCP14SD, + UC_X86_INS_VRCP14SS, + UC_X86_INS_VRCP28PD, + UC_X86_INS_VRCP28PS, + UC_X86_INS_VRCP28SD, + UC_X86_INS_VRCP28SS, + UC_X86_INS_VRCPPS, + UC_X86_INS_VRCPSS, + UC_X86_INS_VRNDSCALEPD, + UC_X86_INS_VRNDSCALEPS, + UC_X86_INS_VRNDSCALESD, + UC_X86_INS_VRNDSCALESS, + UC_X86_INS_VROUNDPD, + UC_X86_INS_VROUNDPS, + UC_X86_INS_VROUNDSD, + UC_X86_INS_VROUNDSS, + UC_X86_INS_VRSQRT14PD, + UC_X86_INS_VRSQRT14PS, + UC_X86_INS_VRSQRT14SD, + UC_X86_INS_VRSQRT14SS, + UC_X86_INS_VRSQRT28PD, + UC_X86_INS_VRSQRT28PS, + UC_X86_INS_VRSQRT28SD, + UC_X86_INS_VRSQRT28SS, + UC_X86_INS_VRSQRTPS, + UC_X86_INS_VRSQRTSS, + UC_X86_INS_VSCATTERDPD, + UC_X86_INS_VSCATTERDPS, + UC_X86_INS_VSCATTERPF0DPD, + UC_X86_INS_VSCATTERPF0DPS, + UC_X86_INS_VSCATTERPF0QPD, + UC_X86_INS_VSCATTERPF0QPS, + UC_X86_INS_VSCATTERPF1DPD, + UC_X86_INS_VSCATTERPF1DPS, + UC_X86_INS_VSCATTERPF1QPD, + UC_X86_INS_VSCATTERPF1QPS, + UC_X86_INS_VSCATTERQPD, + UC_X86_INS_VSCATTERQPS, + UC_X86_INS_VSHUFPD, + UC_X86_INS_VSHUFPS, + UC_X86_INS_VSQRTPD, + UC_X86_INS_VSQRTPS, + UC_X86_INS_VSQRTSD, + UC_X86_INS_VSQRTSS, + UC_X86_INS_VSTMXCSR, + UC_X86_INS_VSUBPD, + UC_X86_INS_VSUBPS, + UC_X86_INS_VSUBSD, + UC_X86_INS_VSUBSS, + UC_X86_INS_VTESTPD, + UC_X86_INS_VTESTPS, + UC_X86_INS_VUNPCKHPD, + UC_X86_INS_VUNPCKHPS, + UC_X86_INS_VUNPCKLPD, + UC_X86_INS_VUNPCKLPS, + UC_X86_INS_VZEROALL, + UC_X86_INS_VZEROUPPER, + UC_X86_INS_WAIT, + UC_X86_INS_WBINVD, + UC_X86_INS_WRFSBASE, + UC_X86_INS_WRGSBASE, + UC_X86_INS_WRMSR, + UC_X86_INS_XABORT, + UC_X86_INS_XACQUIRE, + UC_X86_INS_XBEGIN, + UC_X86_INS_XCHG, + UC_X86_INS_XCRYPTCBC, + UC_X86_INS_XCRYPTCFB, + UC_X86_INS_XCRYPTCTR, + UC_X86_INS_XCRYPTECB, + UC_X86_INS_XCRYPTOFB, + UC_X86_INS_XEND, + UC_X86_INS_XGETBV, + UC_X86_INS_XLATB, + UC_X86_INS_XRELEASE, + UC_X86_INS_XRSTOR, + UC_X86_INS_XRSTOR64, + UC_X86_INS_XRSTORS, + UC_X86_INS_XRSTORS64, + UC_X86_INS_XSAVE, + UC_X86_INS_XSAVE64, + UC_X86_INS_XSAVEC, + UC_X86_INS_XSAVEC64, + UC_X86_INS_XSAVEOPT, + UC_X86_INS_XSAVEOPT64, + UC_X86_INS_XSAVES, + UC_X86_INS_XSAVES64, + UC_X86_INS_XSETBV, + UC_X86_INS_XSHA1, + UC_X86_INS_XSHA256, + UC_X86_INS_XSTORE, + UC_X86_INS_XTEST, + UC_X86_INS_FDISI8087_NOP, + UC_X86_INS_FENI8087_NOP, - UC_X86_INS_ENDING, // mark the end of the list of insn + UC_X86_INS_ENDING, // mark the end of the list of insn } uc_x86_insn; #ifdef __cplusplus diff --git a/qemu/accel.c b/qemu/accel.c index a2172657..be1e87a7 100644 --- a/qemu/accel.c +++ b/qemu/accel.c @@ -59,13 +59,13 @@ static const TypeInfo accel_type = { static const TypeInfo tcg_accel_type = { TYPE_TCG_ACCEL, TYPE_ACCEL, - 0, - 0, - NULL, - NULL, - NULL, - NULL, - NULL, + 0, + 0, + NULL, + NULL, + NULL, + NULL, + NULL, tcg_accel_class_init, }; diff --git a/qemu/exec.c b/qemu/exec.c index 8eebf149..4f23aec6 100644 --- a/qemu/exec.c +++ b/qemu/exec.c @@ -636,7 +636,7 @@ void cpu_single_step(CPUState *cpu, int enabled) { #if defined(TARGET_HAS_ICE) if (cpu->singlestep_enabled != enabled) { - CPUArchState *env; + CPUArchState *env; cpu->singlestep_enabled = enabled; /* must flush all the translated code to avoid inconsistencies */ /* XXX: only flush what is necessary */ @@ -1316,8 +1316,8 @@ static const MemoryRegionOps subpage_ops = { subpage_write, DEVICE_NATIVE_ENDIAN, { - 0, 0, false, subpage_accepts, - }, + 0, 0, false, subpage_accepts, + }, }; static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, @@ -1375,11 +1375,11 @@ static bool notdirty_mem_accepts(void *opaque, hwaddr addr, static const MemoryRegionOps notdirty_mem_ops = { NULL, - notdirty_mem_write, + notdirty_mem_write, DEVICE_NATIVE_ENDIAN, - { - 0, 0, false, notdirty_mem_accepts, - }, + { + 0, 0, false, notdirty_mem_accepts, + }, }; static void io_mem_init(struct uc_struct* uc) @@ -1418,12 +1418,12 @@ static uint16_t dummy_section(PhysPageMap *map, AddressSpace *as, { MemoryRegionSection section = MemoryRegionSection_make( mr, as, 0, - int128_2_64(), - false, - 0 + int128_2_64(), + false, + 0 ); - assert(as); + assert(as); return phys_section_add(map, §ion); } @@ -1444,7 +1444,7 @@ static void mem_begin(MemoryListener *listener) AddressSpace *as = container_of(listener, AddressSpace, dispatch_listener); AddressSpaceDispatch *d = g_new0(AddressSpaceDispatch, 1); uint16_t n; - PhysPageEntry ppe = { 1, PHYS_MAP_NODE_NIL }; + PhysPageEntry ppe = { 1, PHYS_MAP_NODE_NIL }; struct uc_struct *uc = as->uc; n = dummy_section(&d->map, as, &uc->io_mem_unassigned); @@ -1493,12 +1493,12 @@ void address_space_init_dispatch(AddressSpace *as) mem_begin, mem_commit, mem_add, - NULL, + NULL, mem_add, - NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL, + NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL,NULL, 0, }; - as->dispatch = NULL; + as->dispatch = NULL; as->dispatch_listener = ml; memory_listener_register(as->uc, &as->dispatch_listener, as); } diff --git a/qemu/fpu/softfloat.c b/qemu/fpu/softfloat.c index f12ec3e9..f6cda3ea 100644 --- a/qemu/fpu/softfloat.c +++ b/qemu/fpu/softfloat.c @@ -1415,7 +1415,7 @@ float128 int64_to_float128(int64_t a STATUS_PARAM) float128 uint64_to_float128(uint64_t a STATUS_PARAM) { if (a == 0) { - float128 zero = {0}; + float128 zero = {0}; return zero; } return normalizeRoundAndPackFloat128(0, 0x406E, a, 0 STATUS_VAR); @@ -1641,7 +1641,7 @@ uint64 float32_to_uint64(float32 a STATUS_PARAM) uint64 float32_to_uint64_round_to_zero(float32 a STATUS_PARAM) { int64_t v; - signed char current_rounding_mode = STATUS(float_rounding_mode); + signed char current_rounding_mode = STATUS(float_rounding_mode); set_float_rounding_mode(float_round_to_zero STATUS_VAR); v = float32_to_uint64(a STATUS_VAR); set_float_rounding_mode(current_rounding_mode STATUS_VAR); @@ -7159,7 +7159,7 @@ uint64_t float64_to_uint64(float64 a STATUS_PARAM) uint64_t float64_to_uint64_round_to_zero (float64 a STATUS_PARAM) { int64_t v; - signed char current_rounding_mode = STATUS(float_rounding_mode); + signed char current_rounding_mode = STATUS(float_rounding_mode); set_float_rounding_mode(float_round_to_zero STATUS_VAR); v = float64_to_uint64(a STATUS_VAR); set_float_rounding_mode(current_rounding_mode STATUS_VAR); diff --git a/qemu/glib_compat.c b/qemu/glib_compat.c index 4da0765b..ab1d56d1 100644 --- a/qemu/glib_compat.c +++ b/qemu/glib_compat.c @@ -190,9 +190,9 @@ GList *g_list_remove_link(GList *list, GList *llink) // code copied from glib/glist.c, version 2.28.0 static GList *g_list_sort_merge(GList *l1, - GList *l2, - GFunc compare_func, - gpointer user_data) + GList *l2, + GFunc compare_func, + gpointer user_data) { GList list, *l, *lprev; gint cmp; @@ -206,13 +206,13 @@ static GList *g_list_sort_merge(GList *l1, if (cmp <= 0) { - l->next = l1; - l1 = l1->next; + l->next = l1; + l1 = l1->next; } else - { - l->next = l2; - l2 = l2->next; + { + l->next = l2; + l2 = l2->next; } l = l->next; l->prev = lprev; @@ -225,8 +225,8 @@ static GList *g_list_sort_merge(GList *l1, } static GList *g_list_sort_real(GList *list, - GFunc compare_func, - gpointer user_data) + GFunc compare_func, + gpointer user_data) { GList *l1, *l2; @@ -241,16 +241,16 @@ static GList *g_list_sort_real(GList *list, while ((l2 = l2->next) != NULL) { if ((l2 = l2->next) == NULL) - break; + break; l1 = l1->next; } l2 = l1->next; l1->next = NULL; return g_list_sort_merge (g_list_sort_real (list, compare_func, user_data), - g_list_sort_real (l2, compare_func, user_data), - compare_func, - user_data); + g_list_sort_real (l2, compare_func, user_data), + compare_func, + user_data); } /** @@ -1218,7 +1218,7 @@ void g_free(gpointer ptr) gpointer g_malloc(size_t size) { void *res; - if (size == 0) return NULL; + if (size == 0) return NULL; res = malloc(size); if (res == NULL) exit(1); return res; @@ -1254,9 +1254,9 @@ gpointer g_realloc(gpointer ptr, size_t size) char *g_strdup(const char *str) { #ifdef _MSC_VER - return str ? _strdup(str) : NULL; + return str ? _strdup(str) : NULL; #else - return str ? strdup(str) : NULL; + return str ? strdup(str) : NULL; #endif } @@ -1276,10 +1276,10 @@ char *g_strdup_vprintf(const char *format, va_list ap) #ifdef _MSC_VER int len = _vscprintf(format, ap); if( len < 0 ) - return NULL; + return NULL; str_res = (char *)malloc(len+1); if(str_res==NULL) - return NULL; + return NULL; vsnprintf(str_res, len+1, format, ap); #else vasprintf(&str_res, format, ap); diff --git a/qemu/hw/core/machine.c b/qemu/hw/core/machine.c index 8e53263b..6320fd60 100644 --- a/qemu/hw/core/machine.c +++ b/qemu/hw/core/machine.c @@ -26,19 +26,19 @@ static const TypeInfo machine_info = { sizeof(MachineClass), sizeof(MachineState), - NULL, + NULL, machine_initfn, - NULL, + NULL, machine_finalize, - - NULL, + + NULL, - NULL, - NULL, - NULL, + NULL, + NULL, + NULL, - true, + true, }; void machine_register_types(struct uc_struct *uc) diff --git a/qemu/hw/core/qdev.c b/qemu/hw/core/qdev.c index 17b3fe7d..ca75d19d 100644 --- a/qemu/hw/core/qdev.c +++ b/qemu/hw/core/qdev.c @@ -284,20 +284,20 @@ static const TypeInfo device_type_info = { TYPE_OBJECT, sizeof(DeviceClass), - sizeof(DeviceState), + sizeof(DeviceState), NULL, - - device_initfn, + + device_initfn, device_post_init, device_finalize, - NULL, + NULL, device_class_init, - device_class_base_init, - NULL, + device_class_base_init, + NULL, - true, + true, }; static void qbus_initfn(struct uc_struct *uc, Object *obj, void *opaque) @@ -321,20 +321,20 @@ static const TypeInfo bus_info = { TYPE_OBJECT, sizeof(BusClass), - sizeof(BusState), + sizeof(BusState), NULL, - + qbus_initfn, NULL, - qbus_finalize, - - NULL, + qbus_finalize, + + NULL, bus_class_init, - NULL, - NULL, - - true, + NULL, + NULL, + + true, }; void qdev_register_types(struct uc_struct *uc) diff --git a/qemu/hw/i386/pc.c b/qemu/hw/i386/pc.c index e245703b..d5f3ac1e 100644 --- a/qemu/hw/i386/pc.c +++ b/qemu/hw/i386/pc.c @@ -154,25 +154,25 @@ static const TypeInfo pc_machine_info = { sizeof(PCMachineClass), sizeof(PCMachineState), - NULL, + NULL, pc_machine_initfn, - NULL, - NULL, + NULL, + NULL, - NULL, - - pc_machine_class_init, - NULL, - NULL, - - true, + NULL, - NULL, - NULL, - - // should this be added somehow? - //.interfaces = (InterfaceInfo[]) { { } }, + pc_machine_class_init, + NULL, + NULL, + + true, + + NULL, + NULL, + + // should this be added somehow? + //.interfaces = (InterfaceInfo[]) { { } }, }; void pc_machine_register_types(struct uc_struct *uc) diff --git a/qemu/hw/i386/pc_piix.c b/qemu/hw/i386/pc_piix.c index 43ec6962..a5ea8628 100644 --- a/qemu/hw/i386/pc_piix.c +++ b/qemu/hw/i386/pc_piix.c @@ -47,12 +47,12 @@ static int pc_init_pci(struct uc_struct *uc, MachineState *machine) } static QEMUMachine pc_i440fx_machine_v2_2 = { - "pc_piix", + "pc_piix", "pc-i440fx-2.2", pc_init_pci, NULL, - 255, - 1, + 255, + 1, UC_ARCH_X86, // X86 }; diff --git a/qemu/hw/intc/apic.c b/qemu/hw/intc/apic.c index bab714ef..957a66eb 100644 --- a/qemu/hw/intc/apic.c +++ b/qemu/hw/intc/apic.c @@ -203,28 +203,28 @@ static void apic_class_init(struct uc_struct *uc, ObjectClass *klass, void *data k->vapic_base_update = apic_vapic_base_update; k->pre_save = apic_pre_save; k->post_load = apic_post_load; - //printf("... init apic class\n"); + //printf("... init apic class\n"); } static const TypeInfo apic_info = { "apic", - TYPE_APIC_COMMON, + TYPE_APIC_COMMON, - 0, + 0, sizeof(APICCommonState), NULL, - NULL, - NULL, - NULL, + NULL, + NULL, + NULL, - NULL, + NULL, - apic_class_init, + apic_class_init, }; void apic_register_types(struct uc_struct *uc) { - //printf("... register apic types\n"); + //printf("... register apic types\n"); type_register_static(uc, &apic_info); } diff --git a/qemu/hw/intc/apic_common.c b/qemu/hw/intc/apic_common.c index 8f181591..f80b7351 100644 --- a/qemu/hw/intc/apic_common.c +++ b/qemu/hw/intc/apic_common.c @@ -164,8 +164,8 @@ void apic_init_reset(struct uc_struct *uc, DeviceState *dev) void apic_designate_bsp(struct uc_struct *uc, DeviceState *dev) { APICCommonState *s; - - if (dev == NULL) { + + if (dev == NULL) { return; } @@ -243,7 +243,7 @@ static void apic_common_class_init(struct uc_struct *uc, ObjectClass *klass, voi * x86_cpu_apic_create() */ dc->cannot_instantiate_with_device_add_yet = true; - //printf("... init apic common class\n"); + //printf("... init apic common class\n"); } static const TypeInfo apic_common_type = { @@ -251,24 +251,24 @@ static const TypeInfo apic_common_type = { TYPE_DEVICE, sizeof(APICCommonClass), - sizeof(APICCommonState), + sizeof(APICCommonState), NULL, - NULL, - NULL, - NULL, - - NULL, - - apic_common_class_init, - NULL, - NULL, + NULL, + NULL, + NULL, - true, + NULL, + + apic_common_class_init, + NULL, + NULL, + + true, }; void apic_common_register_types(struct uc_struct *uc) { - //printf("... register apic common\n"); + //printf("... register apic common\n"); type_register_static(uc, &apic_common_type); } diff --git a/qemu/hw/mips/cputimer.c b/qemu/hw/mips/cputimer.c index 6e34c8c4..3807a715 100644 --- a/qemu/hw/mips/cputimer.c +++ b/qemu/hw/mips/cputimer.c @@ -50,7 +50,7 @@ static void cpu_mips_timer_update(CPUMIPSState *env) now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); wait = env->CP0_Compare - env->CP0_Count - - (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); + (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); next = now + muldiv64(wait, get_ticks_per_sec(), TIMER_FREQ); timer_mod(env->timer, next); #endif diff --git a/qemu/include/elf.h b/qemu/include/elf.h index d153cfb5..3eeb6001 100644 --- a/qemu/include/elf.h +++ b/qemu/include/elf.h @@ -444,7 +444,7 @@ #define R_X86_64_JUMP_SLOT 7 /* Create PLT entry */ #define R_X86_64_RELATIVE 8 /* Adjust by program base */ #define R_X86_64_GOTPCREL 9 /* 32 bit signed pc relative - offset to GOT */ + offset to GOT */ #define R_X86_64_32 10 /* Direct 32 bit zero extended */ #define R_X86_64_32S 11 /* Direct 32 bit sign extended */ #define R_X86_64_16 12 /* Direct 16 bit zero extended */ diff --git a/qemu/include/exec/cpu-defs.h b/qemu/include/exec/cpu-defs.h index 2d19f2a8..07dcf667 100644 --- a/qemu/include/exec/cpu-defs.h +++ b/qemu/include/exec/cpu-defs.h @@ -95,9 +95,9 @@ typedef struct CPUTLBEntry { uintptr_t addend; /* padding to get a power of two size */ #if defined(_MSC_VER) && defined(_WIN64) - // dummy would be size 0 which isnt supported by msvc, so we remove it + // dummy would be size 0 which isnt supported by msvc, so we remove it #else - uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - + uint8_t dummy[(1 << CPU_TLB_ENTRY_BITS) - (sizeof(target_ulong) * 3 + (((-(int)sizeof(target_ulong)) * 3) & (sizeof(uintptr_t) - 1)) + sizeof(uintptr_t))]; diff --git a/qemu/include/exec/exec-all.h b/qemu/include/exec/exec-all.h index 41496951..e839825f 100644 --- a/qemu/include/exec/exec-all.h +++ b/qemu/include/exec/exec-all.h @@ -196,7 +196,7 @@ static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc) target_ulong tmp; tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)); return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK) - | (tmp & TB_JMP_ADDR_MASK)); + | (tmp & TB_JMP_ADDR_MASK)); } static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc) diff --git a/qemu/include/exec/memory.h b/qemu/include/exec/memory.h index b86f684a..844a3308 100644 --- a/qemu/include/exec/memory.h +++ b/qemu/include/exec/memory.h @@ -241,14 +241,14 @@ struct MemoryRegionSection { static inline MemoryRegionSection MemoryRegionSection_make(MemoryRegion *mr, AddressSpace *address_space, hwaddr offset_within_region, Int128 size, hwaddr offset_within_address_space, bool readonly) { - MemoryRegionSection section; - section.mr = mr; - section.address_space = address_space; - section.offset_within_region = offset_within_region; - section.size = size; - section.offset_within_address_space = offset_within_address_space; - section.readonly = readonly; - return section; + MemoryRegionSection section; + section.mr = mr; + section.address_space = address_space; + section.offset_within_region = offset_within_region; + section.size = size; + section.offset_within_address_space = offset_within_address_space; + section.readonly = readonly; + return section; } /** diff --git a/qemu/include/qemu/aes.h b/qemu/include/qemu/aes.h index a006da22..63438adb 100644 --- a/qemu/include/qemu/aes.h +++ b/qemu/include/qemu/aes.h @@ -20,17 +20,17 @@ typedef struct aes_key_st AES_KEY; #endif int AES_set_encrypt_key(const unsigned char *userKey, const int bits, - AES_KEY *key); + AES_KEY *key); int AES_set_decrypt_key(const unsigned char *userKey, const int bits, - AES_KEY *key); + AES_KEY *key); void AES_encrypt(const unsigned char *in, unsigned char *out, - const AES_KEY *key); + const AES_KEY *key); void AES_decrypt(const unsigned char *in, unsigned char *out, - const AES_KEY *key); + const AES_KEY *key); void AES_cbc_encrypt(const unsigned char *in, unsigned char *out, - const unsigned long length, const AES_KEY *key, - unsigned char *ivec, const int enc); + const unsigned long length, const AES_KEY *key, + unsigned char *ivec, const int enc); extern const uint8_t AES_sbox[256]; extern const uint8_t AES_isbox[256]; diff --git a/qemu/include/qemu/bitops.h b/qemu/include/qemu/bitops.h index bbd1413e..4ae468e3 100644 --- a/qemu/include/qemu/bitops.h +++ b/qemu/include/qemu/bitops.h @@ -32,10 +32,10 @@ */ static inline void set_bit(long nr, unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); + unsigned long mask = BIT_MASK(nr); unsigned long *p = addr + BIT_WORD(nr); - *p |= mask; + *p |= mask; } /** @@ -45,10 +45,10 @@ static inline void set_bit(long nr, unsigned long *addr) */ static inline void clear_bit(long nr, unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); + unsigned long mask = BIT_MASK(nr); unsigned long *p = addr + BIT_WORD(nr); - *p &= ~mask; + *p &= ~mask; } /** @@ -58,10 +58,10 @@ static inline void clear_bit(long nr, unsigned long *addr) */ static inline void change_bit(long nr, unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); + unsigned long mask = BIT_MASK(nr); unsigned long *p = addr + BIT_WORD(nr); - *p ^= mask; + *p ^= mask; } /** @@ -71,12 +71,12 @@ static inline void change_bit(long nr, unsigned long *addr) */ static inline int test_and_set_bit(long nr, unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); + unsigned long mask = BIT_MASK(nr); unsigned long *p = addr + BIT_WORD(nr); - unsigned long old = *p; + unsigned long old = *p; - *p = old | mask; - return (old & mask) != 0; + *p = old | mask; + return (old & mask) != 0; } /** @@ -86,12 +86,12 @@ static inline int test_and_set_bit(long nr, unsigned long *addr) */ static inline int test_and_clear_bit(long nr, unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); + unsigned long mask = BIT_MASK(nr); unsigned long *p = addr + BIT_WORD(nr); - unsigned long old = *p; + unsigned long old = *p; - *p = old & ~mask; - return (old & mask) != 0; + *p = old & ~mask; + return (old & mask) != 0; } /** @@ -101,12 +101,12 @@ static inline int test_and_clear_bit(long nr, unsigned long *addr) */ static inline int test_and_change_bit(long nr, unsigned long *addr) { - unsigned long mask = BIT_MASK(nr); + unsigned long mask = BIT_MASK(nr); unsigned long *p = addr + BIT_WORD(nr); - unsigned long old = *p; + unsigned long old = *p; - *p = old ^ mask; - return (old & mask) != 0; + *p = old ^ mask; + return (old & mask) != 0; } /** @@ -116,7 +116,7 @@ static inline int test_and_change_bit(long nr, unsigned long *addr) */ static inline int test_bit(long nr, const unsigned long *addr) { - return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); + return 1UL & (addr[BIT_WORD(nr)] >> (nr & (BITS_PER_LONG-1))); } /** @@ -126,7 +126,7 @@ static inline int test_bit(long nr, const unsigned long *addr) * @size: The bitmap size in bits */ unsigned long find_next_bit(const unsigned long *addr, - unsigned long size, unsigned long offset); + unsigned long size, unsigned long offset); /** * find_next_zero_bit - find the next cleared bit in a memory region diff --git a/qemu/include/qemu/compiler.h b/qemu/include/qemu/compiler.h index fe50eccd..acfb2d33 100644 --- a/qemu/include/qemu/compiler.h +++ b/qemu/include/qemu/compiler.h @@ -17,7 +17,7 @@ static double rint( double x ) { - return floor(x < 0 ? x - 0.5 : x + 0.5); + return floor(x < 0 ? x - 0.5 : x + 0.5); } union MSVC_FLOAT_HACK diff --git a/qemu/include/qemu/int128.h b/qemu/include/qemu/int128.h index 4fad1354..f4352100 100644 --- a/qemu/include/qemu/int128.h +++ b/qemu/include/qemu/int128.h @@ -13,7 +13,7 @@ struct Int128 { static inline Int128 int128_make64(uint64_t a) { - Int128 i128 = { a, 0 }; + Int128 i128 = { a, 0 }; return i128; } @@ -35,19 +35,19 @@ static inline Int128 int128_one(void) static inline Int128 int128_2_64(void) { - Int128 i128 = { 0, 1 }; + Int128 i128 = { 0, 1 }; return i128; } static inline Int128 int128_exts64(int64_t a) { - Int128 i128 = { a, (a < 0) ? -1 : 0 }; + Int128 i128 = { a, (a < 0) ? -1 : 0 }; return i128; } static inline Int128 int128_and(Int128 a, Int128 b) { - Int128 i128 = { a.lo & b.lo, a.hi & b.hi }; + Int128 i128 = { a.lo & b.lo, a.hi & b.hi }; return i128; } @@ -59,11 +59,11 @@ static inline Int128 int128_rshift(Int128 a, int n) } h = a.hi >> (n & 63); if (n >= 64) { - Int128 i128 = { h, h >> 63 }; - return i128; + Int128 i128 = { h, h >> 63 }; + return i128; } else { - Int128 i128 = { (a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h }; - return i128; + Int128 i128 = { (a.lo >> n) | ((uint64_t)a.hi << (64 - n)), h }; + return i128; } } @@ -77,21 +77,21 @@ static inline Int128 int128_add(Int128 a, Int128 b) * * So the carry is lo < a.lo. */ - Int128 i128 = { lo, (uint64_t)a.hi + b.hi + (lo < a.lo) }; - return i128; + Int128 i128 = { lo, (uint64_t)a.hi + b.hi + (lo < a.lo) }; + return i128; } static inline Int128 int128_neg(Int128 a) { uint64_t lo = 0-a.lo; - Int128 i128 = { lo, ~(uint64_t)a.hi + !lo }; - return i128; + Int128 i128 = { lo, ~(uint64_t)a.hi + !lo }; + return i128; } static inline Int128 int128_sub(Int128 a, Int128 b) { - Int128 i128 = { a.lo - b.lo, (uint64_t)a.hi - b.hi - (a.lo < b.lo) }; - return i128; + Int128 i128 = { a.lo - b.lo, (uint64_t)a.hi - b.hi - (a.lo < b.lo) }; + return i128; } static inline bool int128_nonneg(Int128 a) diff --git a/qemu/include/qemu/timer.h b/qemu/include/qemu/timer.h index e918e364..28b3794e 100644 --- a/qemu/include/qemu/timer.h +++ b/qemu/include/qemu/timer.h @@ -229,7 +229,7 @@ static inline int64_t cpu_get_real_ticks(void) static inline int64_t cpu_get_real_ticks(void) { #ifdef _MSC_VER - return __rdtsc(); + return __rdtsc(); #else int64_t val; asm volatile ("rdtsc" : "=A" (val)); @@ -242,7 +242,7 @@ static inline int64_t cpu_get_real_ticks(void) static inline int64_t cpu_get_real_ticks(void) { #ifdef _MSC_VER - return __rdtsc(); + return __rdtsc(); #else uint32_t low,high; int64_t val; diff --git a/qemu/memory.c b/qemu/memory.c index 277a3c80..36b8fc19 100644 --- a/qemu/memory.c +++ b/qemu/memory.c @@ -140,9 +140,9 @@ struct AddrRange { static AddrRange addrrange_make(Int128 start, Int128 size) { AddrRange ar; - ar.start = start; - ar.size = size; - return ar; + ar.start = start; + ar.size = size; + return ar; } static bool addrrange_equal(AddrRange r1, AddrRange r2) @@ -243,9 +243,9 @@ static bool memory_listener_match(MemoryListener *listener, /* No need to ref/unref .mr, the FlatRange keeps it alive. */ #define MEMORY_LISTENER_UPDATE_REGION(fr, as, dir, callback) \ - do { MemoryRegionSection _mrs = MemoryRegionSection_make((fr)->mr, as, (fr)->offset_in_region, \ - (fr)->addr.size, int128_get64((fr)->addr.start), (fr)->readonly); \ - MEMORY_LISTENER_CALL(callback, dir, &_mrs); } while(0); + do { MemoryRegionSection _mrs = MemoryRegionSection_make((fr)->mr, as, (fr)->offset_in_region, \ + (fr)->addr.size, int128_get64((fr)->addr.start), (fr)->readonly); \ + MEMORY_LISTENER_CALL(callback, dir, &_mrs); } while(0); /* MEMORY_LISTENER_CALL(callback, dir, (&(MemoryRegionSection) { \ @@ -272,12 +272,12 @@ struct MemoryRegionIoeventfd { static MemoryRegionIoeventfd MemoryRegionIoeventfd_make(AddrRange addr, bool match_data, uint64_t data, EventNotifier *e) { - MemoryRegionIoeventfd mrfd; - mrfd.addr = addr; + MemoryRegionIoeventfd mrfd; + mrfd.addr = addr; mrfd.match_data = match_data; mrfd.data = data; mrfd.e = e; - return mrfd; + return mrfd; } static bool memory_region_ioeventfd_before(MemoryRegionIoeventfd a, @@ -392,7 +392,7 @@ static void flatview_destroy(FlatView *view) static void flatview_ref(FlatView *view) { - atomic_inc(&view->ref); + atomic_inc(&view->ref); } static void flatview_unref(FlatView *view) @@ -1093,12 +1093,12 @@ static bool unassigned_mem_accepts(void *opaque, hwaddr addr, } const MemoryRegionOps unassigned_mem_ops = { - NULL, - NULL, + NULL, + NULL, DEVICE_NATIVE_ENDIAN, - - {0,0,false,unassigned_mem_accepts}, + + {0,0,false,unassigned_mem_accepts}, }; bool memory_region_access_valid(MemoryRegion *mr, @@ -1473,7 +1473,7 @@ void memory_region_add_eventfd(MemoryRegion *mr, EventNotifier *e) { MemoryRegionIoeventfd mrfd = MemoryRegionIoeventfd_make( - addrrange_make(int128_make64(addr), int128_make64(size)), + addrrange_make(int128_make64(addr), int128_make64(size)), match_data, data, e); unsigned i; @@ -1502,7 +1502,7 @@ void memory_region_del_eventfd(MemoryRegion *mr, EventNotifier *e) { MemoryRegionIoeventfd mrfd = MemoryRegionIoeventfd_make( - addrrange_make(int128_make64(addr), int128_make64(size)), + addrrange_make(int128_make64(addr), int128_make64(size)), match_data, data, e); unsigned i; @@ -1876,13 +1876,13 @@ static const TypeInfo memory_region_info = { TYPE_MEMORY_REGION, TYPE_OBJECT, - 0, - sizeof(MemoryRegion), - NULL, + 0, + sizeof(MemoryRegion), + NULL, memory_region_initfn, NULL, - memory_region_finalize, + memory_region_finalize, }; void memory_register_types(struct uc_struct *uc) diff --git a/qemu/qom/container.c b/qemu/qom/container.c index 131fa38f..e0e18f75 100644 --- a/qemu/qom/container.c +++ b/qemu/qom/container.c @@ -17,7 +17,7 @@ static const TypeInfo container_info = { "container", TYPE_OBJECT, - 0, + 0, sizeof(Object), }; diff --git a/qemu/qom/cpu.c b/qemu/qom/cpu.c index a7cc20b7..cea48afc 100644 --- a/qemu/qom/cpu.c +++ b/qemu/qom/cpu.c @@ -261,21 +261,21 @@ static const TypeInfo cpu_type_info = { TYPE_CPU, TYPE_DEVICE, - sizeof(CPUClass), + sizeof(CPUClass), sizeof(CPUState), - NULL, + NULL, - cpu_common_initfn, - NULL, - NULL, - - NULL, + cpu_common_initfn, + NULL, + NULL, + + NULL, cpu_class_init, - NULL, - NULL, - - true, + NULL, + NULL, + + true, }; void cpu_register_types(struct uc_struct *uc) diff --git a/qemu/qom/object.c b/qemu/qom/object.c index 1ab41da9..0e3db373 100644 --- a/qemu/qom/object.c +++ b/qemu/qom/object.c @@ -1646,44 +1646,44 @@ void register_types_object(struct uc_struct *uc) { static TypeInfo interface_info = { TYPE_INTERFACE, // name - NULL, + NULL, sizeof(InterfaceClass), // class_size - 0, - NULL, + 0, + NULL, - NULL, - NULL, - NULL, + NULL, + NULL, + NULL, - NULL, + NULL, - NULL, - NULL, - NULL, + NULL, + NULL, + NULL, true, // abstract }; static TypeInfo object_info = { TYPE_OBJECT, - NULL, + NULL, 0, - sizeof(Object), + sizeof(Object), NULL, - object_instance_init, + object_instance_init, + NULL, NULL, - NULL, - NULL, + NULL, - NULL, - NULL, - NULL, + NULL, + NULL, + NULL, - true, + true, }; uc->type_interface = type_register_internal(uc, &interface_info); diff --git a/qemu/softmmu_template.h b/qemu/softmmu_template.h index a7373d57..6903e7d1 100644 --- a/qemu/softmmu_template.h +++ b/qemu/softmmu_template.h @@ -134,12 +134,12 @@ License along with this library; if not, see . */ #define victim_tlb_hit_funcs static inline bool victim_tlb_hit_read(CPUArchState *env, target_ulong addr, int mmu_idx, int index) { - VICTIM_TLB_HIT(ADDR_READ); + VICTIM_TLB_HIT(ADDR_READ); } static inline bool victim_tlb_hit_write(CPUArchState *env, target_ulong addr, int mmu_idx, int index) { - VICTIM_TLB_HIT(addr_write); + VICTIM_TLB_HIT(addr_write); } #endif // victim_tlb_hit_funcs @@ -179,7 +179,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, int error_code; struct hook *hook; bool handled; - HOOK_FOREACH_VAR_DECLARE; + HOOK_FOREACH_VAR_DECLARE; struct uc_struct *uc = env->uc; MemoryRegion *mr = memory_mapping(uc, addr); @@ -293,7 +293,7 @@ WORD_TYPE helper_le_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, return 0; } #endif - if (!victim_tlb_hit_read(env, addr, mmu_idx, index)) { + if (!victim_tlb_hit_read(env, addr, mmu_idx, index)) { tlb_fill(ENV_GET_CPU(env), addr, READ_ACCESS_TYPE, mmu_idx, retaddr); } @@ -407,7 +407,7 @@ WORD_TYPE helper_be_ld_name(CPUArchState *env, target_ulong addr, int mmu_idx, int error_code; struct hook *hook; bool handled; - HOOK_FOREACH_VAR_DECLARE; + HOOK_FOREACH_VAR_DECLARE; struct uc_struct *uc = env->uc; MemoryRegion *mr = memory_mapping(uc, addr); @@ -672,7 +672,7 @@ void helper_le_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, uintptr_t haddr; struct hook *hook; bool handled; - HOOK_FOREACH_VAR_DECLARE; + HOOK_FOREACH_VAR_DECLARE; struct uc_struct *uc = env->uc; MemoryRegion *mr = memory_mapping(uc, addr); @@ -831,7 +831,7 @@ void helper_be_st_name(CPUArchState *env, target_ulong addr, DATA_TYPE val, uintptr_t haddr; struct hook *hook; bool handled; - HOOK_FOREACH_VAR_DECLARE; + HOOK_FOREACH_VAR_DECLARE; struct uc_struct *uc = env->uc; MemoryRegion *mr = memory_mapping(uc, addr); diff --git a/qemu/target-arm/helper-a64.c b/qemu/target-arm/helper-a64.c index 63f62b42..1d976c17 100644 --- a/qemu/target-arm/helper-a64.c +++ b/qemu/target-arm/helper-a64.c @@ -424,7 +424,7 @@ uint64_t HELPER(crc32_64)(uint64_t acc, uint64_t val, uint32_t bytes) /* zlib crc32 converts the accumulator and output to one's complement. */ // return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff; - return 0; // FIXME + return 0; // FIXME } uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index f041247b..69f7cbea 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -4110,13 +4110,13 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, *page_size = 1024 * 1024; } else { /* Lookup l2 entry. */ - if (type == 1) { - /* Coarse pagetable. */ - table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - } else { - /* Fine pagetable. */ - table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); - } + if (type == 1) { + /* Coarse pagetable. */ + table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); + } else { + /* Fine pagetable. */ + table = (desc & 0xfffff000) | ((address >> 8) & 0xffc); + } desc = ldl_phys(cs->as, table); switch (desc & 3) { case 0: /* Page translation fault. */ @@ -4133,17 +4133,17 @@ static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type, *page_size = 0x1000; break; case 3: /* 1k page. */ - if (type == 1) { - if (arm_feature(env, ARM_FEATURE_XSCALE)) { - phys_addr = (desc & 0xfffff000) | (address & 0xfff); - } else { - /* Page translation fault. */ - code = 7; - goto do_fault; - } - } else { - phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); - } + if (type == 1) { + if (arm_feature(env, ARM_FEATURE_XSCALE)) { + phys_addr = (desc & 0xfffff000) | (address & 0xfff); + } else { + /* Page translation fault. */ + code = 7; + goto do_fault; + } + } else { + phys_addr = (desc & 0xfffffc00) | (address & 0x3ff); + } ap = (desc >> 4) & 3; *page_size = 0x400; break; @@ -4516,18 +4516,18 @@ static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, *phys_ptr = address; for (n = 7; n >= 0; n--) { - base = env->cp15.c6_region[n]; - if ((base & 1) == 0) - continue; - mask = 1 << ((base >> 1) & 0x1f); - /* Keep this shift separate from the above to avoid an - (undefined) << 32. */ - mask = (mask << 1) - 1; - if (((base ^ address) & ~mask) == 0) - break; + base = env->cp15.c6_region[n]; + if ((base & 1) == 0) + continue; + mask = 1 << ((base >> 1) & 0x1f); + /* Keep this shift separate from the above to avoid an + (undefined) << 32. */ + mask = (mask << 1) - 1; + if (((base ^ address) & ~mask) == 0) + break; } if (n < 0) - return 2; + return 2; if (access_type == 2) { mask = env->cp15.pmsav5_insn_ap; @@ -4537,31 +4537,31 @@ static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, mask = (mask >> (n * 4)) & 0xf; switch (mask) { case 0: - return 1; + return 1; case 1: - if (is_user) - return 1; - *prot = PAGE_READ | PAGE_WRITE; - break; + if (is_user) + return 1; + *prot = PAGE_READ | PAGE_WRITE; + break; case 2: - *prot = PAGE_READ; - if (!is_user) - *prot |= PAGE_WRITE; - break; + *prot = PAGE_READ; + if (!is_user) + *prot |= PAGE_WRITE; + break; case 3: - *prot = PAGE_READ | PAGE_WRITE; - break; + *prot = PAGE_READ | PAGE_WRITE; + break; case 5: - if (is_user) - return 1; - *prot = PAGE_READ; - break; + if (is_user) + return 1; + *prot = PAGE_READ; + break; case 6: - *prot = PAGE_READ; - break; + *prot = PAGE_READ; + break; default: - /* Bad permission. */ - return 1; + /* Bad permission. */ + return 1; } *prot |= PAGE_EXEC; return 0; @@ -4607,8 +4607,8 @@ static inline int get_phys_addr(CPUARMState *env, target_ulong address, return 0; } else if (arm_feature(env, ARM_FEATURE_MPU)) { *page_size = TARGET_PAGE_SIZE; - return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, - prot); + return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr, + prot); } else if (extended_addresses_enabled(env)) { return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr, prot, page_size); diff --git a/qemu/target-i386/cpu.c b/qemu/target-i386/cpu.c index 4661c228..895366cb 100644 --- a/qemu/target-i386/cpu.c +++ b/qemu/target-i386/cpu.c @@ -310,24 +310,24 @@ typedef struct FeatureWordInfo { static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { #ifdef _MSC_VER - // FEAT_1_EDX - { + // FEAT_1_EDX + { feature_name, 1, - false,0, - R_EDX, + false,0, + R_EDX, TCG_FEATURES, }, // FEAT_1_ECX - { + { ext_feature_name, 1, - false,0, - R_ECX, + false,0, + R_ECX, TCG_EXT_FEATURES, }, // FEAT_7_0_EBX - { + { cpuid_7_0_ebx_feature_name, 7, true, 0, @@ -335,44 +335,44 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { TCG_7_0_EBX_FEATURES, }, // FEAT_8000_0001_EDX - { + { ext2_feature_name, 0x80000001, - false,0, - R_EDX, + false,0, + R_EDX, TCG_EXT2_FEATURES, }, // FEAT_8000_0001_ECX - { + { ext3_feature_name, 0x80000001, - false,0, - R_ECX, + false,0, + R_ECX, TCG_EXT3_FEATURES, }, // FEAT_8000_0007_EDX - { + { cpuid_apm_edx_feature_name, 0x80000007, - false,0, + false,0, R_EDX, TCG_APM_FEATURES, CPUID_APM_INVTSC, }, // FEAT_C000_0001_EDX - { + { ext4_feature_name, 0xC0000001, - false,0, - R_EDX, + false,0, + R_EDX, TCG_EXT4_FEATURES, }, - // FEAT_KVM - {0}, - // FEAT_SVM - {0}, + // FEAT_KVM + {0}, + // FEAT_SVM + {0}, #else - [FEAT_1_EDX] = { + [FEAT_1_EDX] = { .feat_names = feature_name, .cpuid_eax = 1, .cpuid_reg = R_EDX, .tcg_features = TCG_FEATURES, @@ -458,7 +458,7 @@ void host_cpuid(uint32_t function, uint32_t count, uint32_t vec[4]; #ifdef _MSC_VER - __cpuidex((int*)vec, function, count); + __cpuidex((int*)vec, function, count); #else #ifdef __x86_64__ asm volatile("cpuid" @@ -619,61 +619,61 @@ static X86CPUDefinition builtin_x86_defs[] = { 4, 0x8000000A, 0, CPUID_VENDOR_AMD, 6, 6, 3, - { - // FEAT_1_EDX + { + // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, - // FEAT_1_ECX + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, - // FEAT_7_0_EBX - 0, - // FEAT_8000_0001_EDX + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, - // FEAT_8000_0001_ECX + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, - }, + }, }, { "phenom", 5, 0x8000001A, 0, CPUID_VENDOR_AMD, 16, 2, 3, - { - /* Missing: CPUID_HT */ - // FEAT_1_EDX + { + /* Missing: CPUID_HT */ + // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36 | CPUID_VME, - // FEAT_1_ECX + // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, - // FEAT_7_0_EBX - 0, - // FEAT_8000_0001_EDX + // FEAT_7_0_EBX + 0, + // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT | CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP, - /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, - CPUID_EXT3_CR8LEG, - CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, - CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ - // FEAT_8000_0001_ECX + /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC, + CPUID_EXT3_CR8LEG, + CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH, + CPUID_EXT3_OSVW, CPUID_EXT3_IBS */ + // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, - // FEAT_8000_0007_EDX - 0, - // FEAT_C000_0001_EDX - 0, - // FEAT_KVM - 0, - /* Missing: CPUID_SVM_LBRV */ - // FEAT_SVM + // FEAT_8000_0007_EDX + 0, + // FEAT_C000_0001_EDX + 0, + // FEAT_KVM + 0, + /* Missing: CPUID_SVM_LBRV */ + // FEAT_SVM CPUID_SVM_NPT, - }, + }, "AMD Phenom(tm) 9550 Quad-Core Processor", }, { @@ -681,7 +681,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 10, 0x80000008, 0, CPUID_VENDOR_INTEL, 6, 15, 11, - { + { /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ // FEAT_1_EDX PPRO_FEATURES | @@ -692,13 +692,13 @@ static X86CPUDefinition builtin_x86_defs[] = { // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - }, + }, "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz", }, { @@ -706,7 +706,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 5, 0x80000008, 0, CPUID_VENDOR_INTEL, 15, 6, 1, - { + { /* Missing: CPUID_VME, CPUID_HT */ // FEAT_1_EDX PPRO_FEATURES | @@ -715,8 +715,8 @@ static X86CPUDefinition builtin_x86_defs[] = { /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */ // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_CX16, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */ // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | @@ -727,7 +727,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */ // FEAT_8000_0001_ECX 0, - }, + }, "Common KVM processor", }, { @@ -735,31 +735,31 @@ static X86CPUDefinition builtin_x86_defs[] = { 4, 0x80000004, 0, CPUID_VENDOR_INTEL, 6, 6, 3, - { + { // FEAT_1_EDX PPRO_FEATURES, // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_POPCNT, - }, + }, }, { "kvm32", 5, 0x80000008, 0, CPUID_VENDOR_INTEL, 15, 6, 1, - { + { // FEAT_1_EDX PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36, // FEAT_1_ECX CPUID_EXT_SSE3, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES, // FEAT_8000_0001_ECX 0, - }, + }, "Common 32-bit KVM processor", }, { @@ -767,7 +767,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 10, 0x80000008, 0, CPUID_VENDOR_INTEL, 6, 14, 8, - { + { /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ // FEAT_1_EDX PPRO_FEATURES | CPUID_VME | @@ -777,11 +777,11 @@ static X86CPUDefinition builtin_x86_defs[] = { * CPUID_EXT_PDCM, CPUID_EXT_VMX */ // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX CPUID_EXT2_NX, - }, + }, "Genuine Intel(R) CPU T2600 @ 2.16GHz", }, { @@ -789,58 +789,58 @@ static X86CPUDefinition builtin_x86_defs[] = { 1, 0, 0, CPUID_VENDOR_INTEL, 4, 8, 0, - { + { // FEAT_1_EDX I486_FEATURES, - }, + }, }, { "pentium", 1, 0, 0, CPUID_VENDOR_INTEL, 5, 4, 3, - { + { // FEAT_1_EDX PENTIUM_FEATURES, - }, + }, }, { "pentium2", 2, 0, 0, CPUID_VENDOR_INTEL, 6, 5, 2, - { + { // FEAT_1_EDX PENTIUM2_FEATURES, - }, + }, }, { "pentium3", 2, 0, 0, CPUID_VENDOR_INTEL, 6, 7, 3, - { + { // FEAT_1_EDX PENTIUM3_FEATURES, - }, + }, }, { "athlon", 2, 0x80000008, 0, CPUID_VENDOR_AMD, 6, 2, 3, - { + { // FEAT_1_EDX PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR | CPUID_MCA, - // FEAT_1_ECX - 0, - // FEAT_7_0_EBX - 0, + // FEAT_1_ECX + 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT, - }, + }, }, { "n270", @@ -848,7 +848,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 5, 0x8000000A, 0, CPUID_VENDOR_INTEL, 6, 28, 2, - { + { /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ // FEAT_1_EDX PPRO_FEATURES | @@ -860,14 +860,14 @@ static X86CPUDefinition builtin_x86_defs[] = { // FEAT_1_ECX CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_MOVBE, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | CPUID_EXT2_NX, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - }, + }, "Intel(R) Atom(TM) CPU N270 @ 1.60GHz", }, { @@ -875,7 +875,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 4, 0x8000000A, 0, CPUID_VENDOR_INTEL, 6, 15, 3, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -884,13 +884,13 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_DE | CPUID_FP87, // FEAT_1_ECX CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - }, + }, "Intel Celeron_4x0 (Conroe/Merom Class Core 2)", }, { @@ -898,7 +898,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 4, 0x8000000A, 0, CPUID_VENDOR_INTEL, 6, 23, 3, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -908,13 +908,13 @@ static X86CPUDefinition builtin_x86_defs[] = { // FEAT_1_ECX CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - }, + }, "Intel Core 2 Duo P9xxx (Penryn Class Core 2)", }, { @@ -922,7 +922,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 4, 0x8000000A, 0, CPUID_VENDOR_INTEL, 6, 26, 3, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -932,13 +932,13 @@ static X86CPUDefinition builtin_x86_defs[] = { // FEAT_1_ECX CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - }, + }, "Intel Core i7 9xx (Nehalem Class Core i7)", }, { @@ -946,7 +946,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 11, 0x8000000A, 0, CPUID_VENDOR_INTEL, 6, 44, 1, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -957,13 +957,13 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - }, + }, "Westmere E56xx/L56xx/X56xx (Nehalem-C)", }, { @@ -971,7 +971,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 0xd, 0x8000000A, 0, CPUID_VENDOR_INTEL, 6, 42, 1, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -984,14 +984,14 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, - // FEAT_7_0_EBX - 0, + // FEAT_7_0_EBX + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - }, + }, "Intel Xeon E312xx (Sandy Bridge)", }, { @@ -999,7 +999,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 0xd, 0x8000000A, 0, CPUID_VENDOR_INTEL, 6, 60, 1, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -1013,7 +1013,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 | CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE | CPUID_EXT_PCID, - // FEAT_7_0_EBX + // FEAT_7_0_EBX CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID | @@ -1023,7 +1023,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_SYSCALL, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM, - }, + }, "Intel Core Processor (Haswell)", }, { @@ -1031,7 +1031,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 0xd, 0x8000000A, 0, CPUID_VENDOR_INTEL, 6, 61, 2, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -1056,7 +1056,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_SYSCALL, // FEAT_8000_0001_ECX CPUID_EXT3_LAHF_LM | CPUID_EXT3_3DNOWPREFETCH, - }, + }, "Intel Core Processor (Broadwell)", }, { @@ -1064,7 +1064,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 5, 0x80000008, 0, CPUID_VENDOR_AMD, 15, 6, 1, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -1074,7 +1074,7 @@ static X86CPUDefinition builtin_x86_defs[] = { // FEAT_1_ECX CPUID_EXT_SSE3, // FEAT_7_0_EBX - 0, + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT | @@ -1082,7 +1082,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU, - }, + }, "AMD Opteron 240 (Gen 1 Class Opteron)", }, { @@ -1090,7 +1090,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 5, 0x80000008, 0, CPUID_VENDOR_AMD, 15, 6, 1, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -1100,7 +1100,7 @@ static X86CPUDefinition builtin_x86_defs[] = { // FEAT_1_ECX CPUID_EXT_CX16 | CPUID_EXT_SSE3, // FEAT_7_0_EBX - 0, + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | @@ -1111,7 +1111,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT2_DE | CPUID_EXT2_FPU, // FEAT_8000_0001_ECX CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, - }, + }, "AMD Opteron 22xx (Gen 2 Class Opteron)", }, { @@ -1119,7 +1119,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 5, 0x80000008, 0, CPUID_VENDOR_AMD, 15, 6, 1, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -1130,7 +1130,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR | CPUID_EXT_SSE3, // FEAT_7_0_EBX - 0, + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 | @@ -1142,7 +1142,7 @@ static X86CPUDefinition builtin_x86_defs[] = { // FEAT_8000_0001_ECX CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, - }, + }, "AMD Opteron 23xx (Gen 3 Class Opteron)", }, { @@ -1150,7 +1150,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 0xd, 0x8000001A, 0, CPUID_VENDOR_AMD, 21, 1, 2, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -1163,7 +1163,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, // FEAT_7_0_EBX - 0, + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | @@ -1177,7 +1177,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, - }, + }, "AMD Opteron 62xx class CPU", }, { @@ -1185,7 +1185,7 @@ static X86CPUDefinition builtin_x86_defs[] = { 0xd, 0x8000001A, 0, CPUID_VENDOR_AMD, 21, 2, 0, - { + { // FEAT_1_EDX CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX | CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA | @@ -1198,7 +1198,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3, // FEAT_7_0_EBX - 0, + 0, // FEAT_8000_0001_EDX CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX | @@ -1212,7 +1212,7 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM, - }, + }, "AMD Opteron 63xx class CPU", }, }; @@ -1562,8 +1562,8 @@ static void x86_cpu_get_feature_words(struct uc_struct *uc, Object *obj, Visitor uint32_t *array = (uint32_t *)opaque; FeatureWord w; Error *err = NULL; - // These all get setup below, so no need to initialise them here. - X86CPUFeatureWordInfo word_infos[FEATURE_WORDS]; + // These all get setup below, so no need to initialise them here. + X86CPUFeatureWordInfo word_infos[FEATURE_WORDS]; X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS]; X86CPUFeatureWordInfoList *list = NULL; @@ -1844,16 +1844,16 @@ static void x86_register_cpudef_type(struct uc_struct *uc, X86CPUDefinition *def TYPE_X86_CPU, 0, - 0, - NULL, + 0, + NULL, - NULL, - NULL, - NULL, - - def, - - x86_cpu_cpudef_class_init, + NULL, + NULL, + NULL, + + def, + + x86_cpu_cpudef_class_init, }; type_register(uc, &ti); @@ -2459,7 +2459,7 @@ uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index) static void x86_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque) { - //printf("... X86 initialize (object)\n"); + //printf("... X86 initialize (object)\n"); CPUState *cs = CPU(obj); X86CPU *cpu = X86_CPU(cs->uc, obj); X86CPUClass *xcc = X86_CPU_GET_CLASS(uc, obj); @@ -2563,7 +2563,7 @@ static bool x86_cpu_has_work(CPUState *cs) static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, void *data) { - //printf("... init X86 cpu common class\n"); + //printf("... init X86 cpu common class\n"); X86CPUClass *xcc = X86_CPU_CLASS(uc, oc); CPUClass *cc = CPU_CLASS(uc, oc); DeviceClass *dc = DEVICE_CLASS(uc, oc); @@ -2601,33 +2601,33 @@ static void x86_cpu_common_class_init(struct uc_struct *uc, ObjectClass *oc, voi void x86_cpu_register_types(void *opaque) { - const TypeInfo x86_cpu_type_info = { - TYPE_X86_CPU, - TYPE_CPU, - - sizeof(X86CPUClass), - sizeof(X86CPU), - opaque, - - x86_cpu_initfn, - NULL, - NULL, - - NULL, + const TypeInfo x86_cpu_type_info = { + TYPE_X86_CPU, + TYPE_CPU, + + sizeof(X86CPUClass), + sizeof(X86CPU), + opaque, + + x86_cpu_initfn, + NULL, + NULL, + + NULL, - x86_cpu_common_class_init, - NULL, - NULL, - - true, - }; + x86_cpu_common_class_init, + NULL, + NULL, + + true, + }; - //printf("... register X86 cpu\n"); + //printf("... register X86 cpu\n"); int i; type_register_static(opaque, &x86_cpu_type_info); for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) { x86_register_cpudef_type(opaque, &builtin_x86_defs[i]); } - //printf("... END OF register X86 cpu\n"); + //printf("... END OF register X86 cpu\n"); } diff --git a/qemu/target-i386/cpu.h b/qemu/target-i386/cpu.h index b0686884..d88ae9d3 100644 --- a/qemu/target-i386/cpu.h +++ b/qemu/target-i386/cpu.h @@ -870,7 +870,7 @@ typedef struct CPUX86State { /* Beginning of state preserved by INIT (dummy marker). */ //struct {} start_init_save; - int start_init_save; + int start_init_save; /* FPU state */ unsigned int fpstt; /* top of stack index */ @@ -939,7 +939,7 @@ typedef struct CPUX86State { /* End of state preserved by INIT (dummy marker). */ //struct {} end_init_save; - int end_init_save; + int end_init_save; uint64_t system_time_msr; uint64_t wall_clock_msr; @@ -986,7 +986,7 @@ typedef struct CPUX86State { #if CPU_VTLB_SIZE == 0 #error CPU_VTLB_SIZE is zero #endif - CPU_COMMON + CPU_COMMON /* Fields from here on are preserved across CPU reset. */ diff --git a/qemu/target-i386/fpu_helper.c b/qemu/target-i386/fpu_helper.c index 9ef803d6..53381901 100644 --- a/qemu/target-i386/fpu_helper.c +++ b/qemu/target-i386/fpu_helper.c @@ -490,56 +490,56 @@ void helper_fabs_ST0(CPUX86State *env) void helper_fld1_ST0(CPUX86State *env) { //ST0 = floatx80_one; - floatx80 one = { 0x8000000000000000LL, 0x3fff }; - ST0 = one; + floatx80 one = { 0x8000000000000000LL, 0x3fff }; + ST0 = one; } void helper_fldl2t_ST0(CPUX86State *env) { //ST0 = floatx80_l2t; - floatx80 l2t = { 0xd49a784bcd1b8afeLL, 0x4000 }; + floatx80 l2t = { 0xd49a784bcd1b8afeLL, 0x4000 }; ST0 = l2t; } void helper_fldl2e_ST0(CPUX86State *env) { //ST0 = floatx80_l2e; - floatx80 l2e = { 0xb8aa3b295c17f0bcLL, 0x3fff }; + floatx80 l2e = { 0xb8aa3b295c17f0bcLL, 0x3fff }; ST0 = l2e; } void helper_fldpi_ST0(CPUX86State *env) { //ST0 = floatx80_pi; - floatx80 pi = { 0xc90fdaa22168c235LL, 0x4000 }; + floatx80 pi = { 0xc90fdaa22168c235LL, 0x4000 }; ST0 = pi; } void helper_fldlg2_ST0(CPUX86State *env) { //ST0 = floatx80_lg2; - floatx80 lg2 = { 0x9a209a84fbcff799LL, 0x3ffd }; + floatx80 lg2 = { 0x9a209a84fbcff799LL, 0x3ffd }; ST0 = lg2; } void helper_fldln2_ST0(CPUX86State *env) { //ST0 = floatx80_ln2; - floatx80 ln2 = { 0xb17217f7d1cf79acLL, 0x3ffe }; + floatx80 ln2 = { 0xb17217f7d1cf79acLL, 0x3ffe }; ST0 = ln2; } void helper_fldz_ST0(CPUX86State *env) { //ST0 = floatx80_zero; - floatx80 zero = { 0x0000000000000000LL, 0x0000 }; + floatx80 zero = { 0x0000000000000000LL, 0x0000 }; ST0 = zero; } void helper_fldz_FT0(CPUX86State *env) { //FT0 = floatx80_zero; - floatx80 zero = { 0x0000000000000000LL, 0x0000 }; + floatx80 zero = { 0x0000000000000000LL, 0x0000 }; ST0 = zero; } @@ -702,8 +702,8 @@ void helper_fptan(CPUX86State *env) if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) { env->fpus |= 0x400; } else { - floatx80 one = { 0x8000000000000000LL, 0x3fff }; - fptemp = tan(fptemp); + floatx80 one = { 0x8000000000000000LL, 0x3fff }; + fptemp = tan(fptemp); ST0 = double_to_floatx80(env, fptemp); fpush(env); ST0 = one; @@ -730,8 +730,8 @@ void helper_fxtract(CPUX86State *env) if (floatx80_is_zero(ST0)) { /* Easy way to generate -inf and raising division by 0 exception */ - floatx80 zero = { 0x0000000000000000LL, 0x0000 }; - floatx80 one = { 0x8000000000000000LL, 0x3fff }; + floatx80 zero = { 0x0000000000000000LL, 0x0000 }; + floatx80 one = { 0x8000000000000000LL, 0x3fff }; ST0 = floatx80_div(floatx80_chs(one), zero, &env->fp_status); fpush(env); @@ -760,7 +760,7 @@ void helper_fprem1(CPUX86State *env) if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) { - ST0 = double_to_floatx80(env, NAN); /* NaN */ + ST0 = double_to_floatx80(env, NAN); /* NaN */ env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */ return; } diff --git a/qemu/target-i386/svm.h b/qemu/target-i386/svm.h index c84ff47f..188aa280 100644 --- a/qemu/target-i386/svm.h +++ b/qemu/target-i386/svm.h @@ -131,92 +131,92 @@ #define SVM_CR0_SELECTIVE_MASK (1 << 3 | 1) /* TS and MP */ QEMU_PACK( struct vmcb_control_area { - uint16_t intercept_cr_read; - uint16_t intercept_cr_write; - uint16_t intercept_dr_read; - uint16_t intercept_dr_write; - uint32_t intercept_exceptions; - uint64_t intercept; - uint8_t reserved_1[44]; - uint64_t iopm_base_pa; - uint64_t msrpm_base_pa; - uint64_t tsc_offset; - uint32_t asid; - uint8_t tlb_ctl; - uint8_t reserved_2[3]; - uint32_t int_ctl; - uint32_t int_vector; - uint32_t int_state; - uint8_t reserved_3[4]; - uint64_t exit_code; - uint64_t exit_info_1; - uint64_t exit_info_2; - uint32_t exit_int_info; - uint32_t exit_int_info_err; - uint64_t nested_ctl; - uint8_t reserved_4[16]; - uint32_t event_inj; - uint32_t event_inj_err; - uint64_t nested_cr3; - uint64_t lbr_ctl; - uint8_t reserved_5[832]; + uint16_t intercept_cr_read; + uint16_t intercept_cr_write; + uint16_t intercept_dr_read; + uint16_t intercept_dr_write; + uint32_t intercept_exceptions; + uint64_t intercept; + uint8_t reserved_1[44]; + uint64_t iopm_base_pa; + uint64_t msrpm_base_pa; + uint64_t tsc_offset; + uint32_t asid; + uint8_t tlb_ctl; + uint8_t reserved_2[3]; + uint32_t int_ctl; + uint32_t int_vector; + uint32_t int_state; + uint8_t reserved_3[4]; + uint64_t exit_code; + uint64_t exit_info_1; + uint64_t exit_info_2; + uint32_t exit_int_info; + uint32_t exit_int_info_err; + uint64_t nested_ctl; + uint8_t reserved_4[16]; + uint32_t event_inj; + uint32_t event_inj_err; + uint64_t nested_cr3; + uint64_t lbr_ctl; + uint8_t reserved_5[832]; }); QEMU_PACK( struct vmcb_seg { - uint16_t selector; - uint16_t attrib; - uint32_t limit; - uint64_t base; + uint16_t selector; + uint16_t attrib; + uint32_t limit; + uint64_t base; }); QEMU_PACK( struct vmcb_save_area { - struct vmcb_seg es; - struct vmcb_seg cs; - struct vmcb_seg ss; - struct vmcb_seg ds; - struct vmcb_seg fs; - struct vmcb_seg gs; - struct vmcb_seg gdtr; - struct vmcb_seg ldtr; - struct vmcb_seg idtr; - struct vmcb_seg tr; - uint8_t reserved_1[43]; - uint8_t cpl; - uint8_t reserved_2[4]; - uint64_t efer; - uint8_t reserved_3[112]; - uint64_t cr4; - uint64_t cr3; - uint64_t cr0; - uint64_t dr7; - uint64_t dr6; - uint64_t rflags; - uint64_t rip; - uint8_t reserved_4[88]; - uint64_t rsp; - uint8_t reserved_5[24]; - uint64_t rax; - uint64_t star; - uint64_t lstar; - uint64_t cstar; - uint64_t sfmask; - uint64_t kernel_gs_base; - uint64_t sysenter_cs; - uint64_t sysenter_esp; - uint64_t sysenter_eip; - uint64_t cr2; - uint8_t reserved_6[32]; - uint64_t g_pat; - uint64_t dbgctl; - uint64_t br_from; - uint64_t br_to; - uint64_t last_excp_from; - uint64_t last_excp_to; + struct vmcb_seg es; + struct vmcb_seg cs; + struct vmcb_seg ss; + struct vmcb_seg ds; + struct vmcb_seg fs; + struct vmcb_seg gs; + struct vmcb_seg gdtr; + struct vmcb_seg ldtr; + struct vmcb_seg idtr; + struct vmcb_seg tr; + uint8_t reserved_1[43]; + uint8_t cpl; + uint8_t reserved_2[4]; + uint64_t efer; + uint8_t reserved_3[112]; + uint64_t cr4; + uint64_t cr3; + uint64_t cr0; + uint64_t dr7; + uint64_t dr6; + uint64_t rflags; + uint64_t rip; + uint8_t reserved_4[88]; + uint64_t rsp; + uint8_t reserved_5[24]; + uint64_t rax; + uint64_t star; + uint64_t lstar; + uint64_t cstar; + uint64_t sfmask; + uint64_t kernel_gs_base; + uint64_t sysenter_cs; + uint64_t sysenter_esp; + uint64_t sysenter_eip; + uint64_t cr2; + uint8_t reserved_6[32]; + uint64_t g_pat; + uint64_t dbgctl; + uint64_t br_from; + uint64_t br_to; + uint64_t last_excp_from; + uint64_t last_excp_to; }); QEMU_PACK( struct vmcb { - struct vmcb_control_area control; - struct vmcb_save_area save; + struct vmcb_control_area control; + struct vmcb_save_area save; }); #endif diff --git a/qemu/target-i386/svm_helper.c b/qemu/target-i386/svm_helper.c index 4d415cd8..00e7db3a 100644 --- a/qemu/target-i386/svm_helper.c +++ b/qemu/target-i386/svm_helper.c @@ -490,23 +490,23 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, if (env->intercept_cr_read & (1 << (type - SVM_EXIT_READ_CR0))) { helper_vmexit(env, type, param); } - } else if( type >= SVM_EXIT_WRITE_CR0 && type <= SVM_EXIT_WRITE_CR0 + 8 ) { + } else if( type >= SVM_EXIT_WRITE_CR0 && type <= SVM_EXIT_WRITE_CR0 + 8 ) { if (env->intercept_cr_write & (1 << (type - SVM_EXIT_WRITE_CR0))) { helper_vmexit(env, type, param); } - } else if( type >= SVM_EXIT_READ_DR0 && type <= SVM_EXIT_READ_DR0 + 7 ) { + } else if( type >= SVM_EXIT_READ_DR0 && type <= SVM_EXIT_READ_DR0 + 7 ) { if (env->intercept_dr_read & (1 << (type - SVM_EXIT_READ_DR0))) { helper_vmexit(env, type, param); } - } else if( type >= SVM_EXIT_WRITE_DR0 && type <= SVM_EXIT_WRITE_DR0 + 7 ) { + } else if( type >= SVM_EXIT_WRITE_DR0 && type <= SVM_EXIT_WRITE_DR0 + 7 ) { if (env->intercept_dr_write & (1 << (type - SVM_EXIT_WRITE_DR0))) { helper_vmexit(env, type, param); } - } else if( type >= SVM_EXIT_EXCP_BASE && type <= SVM_EXIT_EXCP_BASE + 31 ) { + } else if( type >= SVM_EXIT_EXCP_BASE && type <= SVM_EXIT_EXCP_BASE + 31 ) { if (env->intercept_exceptions & (1 << (type - SVM_EXIT_EXCP_BASE))) { helper_vmexit(env, type, param); } - } else if( type == SVM_EXIT_MSR ) { + } else if( type == SVM_EXIT_MSR ) { if (env->intercept & (1ULL << (SVM_EXIT_MSR - SVM_EXIT_INTR))) { /* FIXME: this should be read in at vmrun (faster this way?) */ uint64_t addr = ldq_phys(cs->as, env->vm_vmcb + @@ -515,10 +515,10 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, uint32_t t0, t1; uint32_t ecx = (uint32_t)env->regs[R_ECX]; - if( (int32_t)ecx >= 0 && ecx <= 0x1fff ) { + if( (int32_t)ecx >= 0 && ecx <= 0x1fff ) { t0 = (env->regs[R_ECX] * 2) % 8; t1 = (env->regs[R_ECX] * 2) / 8; - } else if( ecx >= 0xc0000000 && ecx <= 0xc0001fff ) { + } else if( ecx >= 0xc0000000 && ecx <= 0xc0001fff ) { t0 = (8192 + env->regs[R_ECX] - 0xc0000000) * 2; t1 = (t0 / 8); t0 %= 8; @@ -526,7 +526,7 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, t0 = (16384 + env->regs[R_ECX] - 0xc0010000) * 2; t1 = (t0 / 8); t0 %= 8; - } else { + } else { helper_vmexit(env, type, param); t0 = 0; t1 = 0; @@ -535,11 +535,11 @@ void helper_svm_check_intercept_param(CPUX86State *env, uint32_t type, helper_vmexit(env, type, param); } } - } else { + } else { if (env->intercept & (1ULL << (type - SVM_EXIT_INTR))) { helper_vmexit(env, type, param); } - } + } } void cpu_svm_check_intercept_param(CPUX86State *env, uint32_t type, diff --git a/qemu/target-i386/translate.c b/qemu/target-i386/translate.c index 269b3a51..65f75564 100644 --- a/qemu/target-i386/translate.c +++ b/qemu/target-i386/translate.c @@ -174,71 +174,71 @@ enum { /* Bit set if the global variable is live after setting CC_OP to X. */ static const uint8_t cc_op_live[CC_OP_NB] = { #ifdef _MSC_VER - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ - USES_CC_SRC, // CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_DYNAMIC, /* must use dynamic code to get cc_op */ + USES_CC_SRC, // CC_OP_EFLAGS, /* all cc are explicitly computed, CC_SRC = flags */ - USES_CC_DST | USES_CC_SRC, // CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ - USES_CC_DST | USES_CC_SRC, // CC_OP_MULW, - USES_CC_DST | USES_CC_SRC, // CC_OP_MULL, - USES_CC_DST | USES_CC_SRC, // CC_OP_MULQ, + USES_CC_DST | USES_CC_SRC, // CC_OP_MULB, /* modify all flags, C, O = (CC_SRC != 0) */ + USES_CC_DST | USES_CC_SRC, // CC_OP_MULW, + USES_CC_DST | USES_CC_SRC, // CC_OP_MULL, + USES_CC_DST | USES_CC_SRC, // CC_OP_MULQ, - USES_CC_DST | USES_CC_SRC, // CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ - USES_CC_DST | USES_CC_SRC, // CC_OP_ADDW, - USES_CC_DST | USES_CC_SRC, // CC_OP_ADDL, - USES_CC_DST | USES_CC_SRC, // CC_OP_ADDQ, + USES_CC_DST | USES_CC_SRC, // CC_OP_ADDB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ + USES_CC_DST | USES_CC_SRC, // CC_OP_ADDW, + USES_CC_DST | USES_CC_SRC, // CC_OP_ADDL, + USES_CC_DST | USES_CC_SRC, // CC_OP_ADDQ, - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCW, - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCL, - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCQ, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCW, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCL, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCQ, - USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ - USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBW, - USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBL, - USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBQ, + USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBW, + USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBL, + USES_CC_DST | USES_CC_SRC | USES_CC_SRCT, // CC_OP_SUBQ, - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBW, - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBL, - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBQ, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBB, /* modify all flags, CC_DST = res, CC_SRC = src1 */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBW, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBL, + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_SBBQ, - USES_CC_DST, // CC_OP_LOGICB, /* modify all flags, CC_DST = res */ - USES_CC_DST, // CC_OP_LOGICW, - USES_CC_DST, // CC_OP_LOGICL, - USES_CC_DST, // CC_OP_LOGICQ, + USES_CC_DST, // CC_OP_LOGICB, /* modify all flags, CC_DST = res */ + USES_CC_DST, // CC_OP_LOGICW, + USES_CC_DST, // CC_OP_LOGICL, + USES_CC_DST, // CC_OP_LOGICQ, - USES_CC_DST | USES_CC_SRC, // CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ - USES_CC_DST | USES_CC_SRC, // CC_OP_INCW, - USES_CC_DST | USES_CC_SRC, // CC_OP_INCL, - USES_CC_DST | USES_CC_SRC, // CC_OP_INCQ, + USES_CC_DST | USES_CC_SRC, // CC_OP_INCB, /* modify all flags except, CC_DST = res, CC_SRC = C */ + USES_CC_DST | USES_CC_SRC, // CC_OP_INCW, + USES_CC_DST | USES_CC_SRC, // CC_OP_INCL, + USES_CC_DST | USES_CC_SRC, // CC_OP_INCQ, - USES_CC_DST | USES_CC_SRC, // CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ - USES_CC_DST | USES_CC_SRC, // CC_OP_DECW, - USES_CC_DST | USES_CC_SRC, // CC_OP_DECL, - USES_CC_DST | USES_CC_SRC, // CC_OP_DECQ, + USES_CC_DST | USES_CC_SRC, // CC_OP_DECB, /* modify all flags except, CC_DST = res, CC_SRC = C */ + USES_CC_DST | USES_CC_SRC, // CC_OP_DECW, + USES_CC_DST | USES_CC_SRC, // CC_OP_DECL, + USES_CC_DST | USES_CC_SRC, // CC_OP_DECQ, - USES_CC_DST | USES_CC_SRC, // CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ - USES_CC_DST | USES_CC_SRC, // CC_OP_SHLW, - USES_CC_DST | USES_CC_SRC, // CC_OP_SHLL, - USES_CC_DST | USES_CC_SRC, // CC_OP_SHLQ, + USES_CC_DST | USES_CC_SRC, // CC_OP_SHLB, /* modify all flags, CC_DST = res, CC_SRC.msb = C */ + USES_CC_DST | USES_CC_SRC, // CC_OP_SHLW, + USES_CC_DST | USES_CC_SRC, // CC_OP_SHLL, + USES_CC_DST | USES_CC_SRC, // CC_OP_SHLQ, - USES_CC_DST | USES_CC_SRC, // CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ - USES_CC_DST | USES_CC_SRC, // CC_OP_SARW, - USES_CC_DST | USES_CC_SRC, // CC_OP_SARL, - USES_CC_DST | USES_CC_SRC, // CC_OP_SARQ, + USES_CC_DST | USES_CC_SRC, // CC_OP_SARB, /* modify all flags, CC_DST = res, CC_SRC.lsb = C */ + USES_CC_DST | USES_CC_SRC, // CC_OP_SARW, + USES_CC_DST | USES_CC_SRC, // CC_OP_SARL, + USES_CC_DST | USES_CC_SRC, // CC_OP_SARQ, - USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ - USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGW, - USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGL, - USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGQ, + USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGB, /* Z,S via CC_DST, C = SRC==0; O=0; P,A undefined */ + USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGW, + USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGL, + USES_CC_DST | USES_CC_SRC, // CC_OP_BMILGQ, - USES_CC_DST | USES_CC_SRC, // CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ - USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ - USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ + USES_CC_DST | USES_CC_SRC, // CC_OP_ADCX, /* CC_DST = C, CC_SRC = rest. */ + USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADOX, /* CC_DST = O, CC_SRC = rest. */ + USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, // CC_OP_ADCOX, /* CC_DST = C, CC_SRC2 = O, CC_SRC = rest. */ - 0, // CC_OP_CLR, /* Z set, all other flags clear. */ + 0, // CC_OP_CLR, /* Z set, all other flags clear. */ #else - [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, + [CC_OP_DYNAMIC] = USES_CC_DST | USES_CC_SRC | USES_CC_SRC2, [CC_OP_EFLAGS] = USES_CC_SRC, [CC_OP_MULB ... CC_OP_MULQ] = USES_CC_DST | USES_CC_SRC, [CC_OP_ADDB ... CC_OP_ADDQ] = USES_CC_DST | USES_CC_SRC, @@ -316,7 +316,7 @@ static void gen_update_cc_op(DisasContext *s) static void fpu_update_ip(CPUX86State *env, target_ulong pc) { - env->fpip = pc; + env->fpip = pc; } #ifdef TARGET_X86_64 @@ -952,7 +952,7 @@ static void gen_compute_eflags(DisasContext *s) } typedef struct CCPrepare { - TCGCond cond; + TCGCond cond; TCGv reg; TCGv reg2; target_ulong imm; @@ -962,18 +962,18 @@ typedef struct CCPrepare { } CCPrepare; static inline CCPrepare ccprepare_make(TCGCond cond, - TCGv reg, TCGv reg2, - target_ulong imm, target_ulong mask, - bool use_reg2, bool no_setcond) + TCGv reg, TCGv reg2, + target_ulong imm, target_ulong mask, + bool use_reg2, bool no_setcond) { - CCPrepare cc = { cond, reg, reg2, imm, mask, use_reg2, no_setcond }; - return cc; + CCPrepare cc = { cond, reg, reg2, imm, mask, use_reg2, no_setcond }; + return cc; } /* compute eflags.C to reg */ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) { - TCGv t0, t1; + TCGv t0, t1; int size, shift; TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 cpu_cc_op = tcg_ctx->cpu_cc_op; @@ -984,43 +984,43 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) TCGv cpu_tmp0 = *(TCGv *)tcg_ctx->cpu_tmp0; switch (s->cc_op) { - case CC_OP_SUBB: case CC_OP_SUBW: case CC_OP_SUBL: case CC_OP_SUBQ: - /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ - size = s->cc_op - CC_OP_SUBB; - t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); - /* If no temporary was used, be careful not to alias t1 and t0. */ - t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg; - tcg_gen_mov_tl(tcg_ctx, t0, cpu_cc_srcT); - gen_extu(tcg_ctx, size, t0); - goto add_sub; + case CC_OP_SUBB: case CC_OP_SUBW: case CC_OP_SUBL: case CC_OP_SUBQ: + /* (DATA_TYPE)CC_SRCT < (DATA_TYPE)CC_SRC */ + size = s->cc_op - CC_OP_SUBB; + t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); + /* If no temporary was used, be careful not to alias t1 and t0. */ + t0 = TCGV_EQUAL(t1, cpu_cc_src) ? cpu_tmp0 : reg; + tcg_gen_mov_tl(tcg_ctx, t0, cpu_cc_srcT); + gen_extu(tcg_ctx, size, t0); + goto add_sub; - case CC_OP_ADDB: case CC_OP_ADDW: case CC_OP_ADDL: case CC_OP_ADDQ: - /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ - size = s->cc_op - CC_OP_ADDB; - t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); - t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, false); - add_sub: - return ccprepare_make(TCG_COND_LTU, t0,t1, 0,-1, true,false); + case CC_OP_ADDB: case CC_OP_ADDW: case CC_OP_ADDL: case CC_OP_ADDQ: + /* (DATA_TYPE)CC_DST < (DATA_TYPE)CC_SRC */ + size = s->cc_op - CC_OP_ADDB; + t1 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); + t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, false); + add_sub: + return ccprepare_make(TCG_COND_LTU, t0,t1, 0,-1, true,false); - case CC_OP_LOGICB: case CC_OP_LOGICW: case CC_OP_LOGICL: case CC_OP_LOGICQ: + case CC_OP_LOGICB: case CC_OP_LOGICW: case CC_OP_LOGICL: case CC_OP_LOGICQ: case CC_OP_CLR: - return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false); + return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false); - case CC_OP_INCB: case CC_OP_INCW: case CC_OP_INCL: case CC_OP_INCQ: - case CC_OP_DECB: case CC_OP_DECW: case CC_OP_DECL: case CC_OP_DECQ: - return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,-1, false,true ); + case CC_OP_INCB: case CC_OP_INCW: case CC_OP_INCL: case CC_OP_INCQ: + case CC_OP_DECB: case CC_OP_DECW: case CC_OP_DECL: case CC_OP_DECQ: + return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,-1, false,true ); - case CC_OP_SHLB: case CC_OP_SHLW: case CC_OP_SHLL: case CC_OP_SHLQ: + case CC_OP_SHLB: case CC_OP_SHLW: case CC_OP_SHLL: case CC_OP_SHLQ: /* (CC_SRC >> (DATA_BITS - 1)) & 1 */ - size = s->cc_op - CC_OP_SHLB; + size = s->cc_op - CC_OP_SHLB; shift = (8 << size) - 1; return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,(target_ulong)(1 << shift), false,false); - case CC_OP_MULB: case CC_OP_MULW: case CC_OP_MULL: case CC_OP_MULQ: + case CC_OP_MULB: case CC_OP_MULW: case CC_OP_MULL: case CC_OP_MULQ: return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,-1, false,false ); - case CC_OP_BMILGB: case CC_OP_BMILGW: case CC_OP_BMILGL: case CC_OP_BMILGQ: - size = s->cc_op - CC_OP_BMILGB; + case CC_OP_BMILGB: case CC_OP_BMILGW: case CC_OP_BMILGL: case CC_OP_BMILGQ: + size = s->cc_op - CC_OP_BMILGB; t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_src, size, false); return ccprepare_make(TCG_COND_EQ, t0,0, 0,-1, false,false); @@ -1029,17 +1029,17 @@ static CCPrepare gen_prepare_eflags_c(DisasContext *s, TCGv reg) return ccprepare_make(TCG_COND_NE, cpu_cc_dst,0, 0,-1, false,true); case CC_OP_EFLAGS: - case CC_OP_SARB: case CC_OP_SARW: case CC_OP_SARL: case CC_OP_SARQ: + case CC_OP_SARB: case CC_OP_SARW: case CC_OP_SARL: case CC_OP_SARQ: /* CC_SRC & 1 */ - return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_C, false,false); + return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_C, false,false); default: - /* The need to compute only C from CC_OP_DYNAMIC is important - in efficiently implementing e.g. INC at the start of a TB. */ - gen_update_cc_op(s); - gen_helper_cc_compute_c(tcg_ctx, reg, cpu_cc_dst, cpu_cc_src, - cpu_cc_src2, cpu_cc_op); - return ccprepare_make(TCG_COND_NE, reg,0, 0,-1, false,true); + /* The need to compute only C from CC_OP_DYNAMIC is important + in efficiently implementing e.g. INC at the start of a TB. */ + gen_update_cc_op(s); + gen_helper_cc_compute_c(tcg_ctx, reg, cpu_cc_dst, cpu_cc_src, + cpu_cc_src2, cpu_cc_op); + return ccprepare_make(TCG_COND_NE, reg,0, 0,-1, false,true); } } @@ -1068,14 +1068,14 @@ static CCPrepare gen_prepare_eflags_s(DisasContext *s, TCGv reg) case CC_OP_ADCX: case CC_OP_ADOX: case CC_OP_ADCOX: - return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_S, false,false); + return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_S, false,false); case CC_OP_CLR: - return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false); + return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false); default: { TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3; TCGv t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, true); - return ccprepare_make(TCG_COND_LT, t0,0, 0,-1, false,false); + return ccprepare_make(TCG_COND_LT, t0,0, 0,-1, false,false); } } } @@ -1092,9 +1092,9 @@ static CCPrepare gen_prepare_eflags_o(DisasContext *s, TCGv reg) case CC_OP_ADCOX: return ccprepare_make(TCG_COND_NE, cpu_cc_src2,0, 0,-1, false,true); case CC_OP_CLR: - return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false); + return ccprepare_make(TCG_COND_NEVER, 0,0, 0,-1, false,false); default: - gen_compute_eflags(s); + gen_compute_eflags(s); return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_O, false,false ); } } @@ -1114,15 +1114,15 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) case CC_OP_ADCX: case CC_OP_ADOX: case CC_OP_ADCOX: - return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_Z, false,false); + return ccprepare_make(TCG_COND_NE, cpu_cc_src,0, 0,CC_Z, false,false); case CC_OP_CLR: - return ccprepare_make(TCG_COND_ALWAYS, 0,0, 0,-1, false,false); + return ccprepare_make(TCG_COND_ALWAYS, 0,0, 0,-1, false,false); default: - { + { TCGMemOp size = (s->cc_op - CC_OP_ADDB) & 3; TCGv t0 = gen_ext_tl(tcg_ctx, reg, cpu_cc_dst, size, false); return ccprepare_make(TCG_COND_EQ, t0,0, 0,-1, false,false); - } + } } } @@ -1130,7 +1130,7 @@ static CCPrepare gen_prepare_eflags_z(DisasContext *s, TCGv reg) value 'b'. In the fast case, T0 is guaranted not to be used. */ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) { - int inv, jcc_op, cond; + int inv, jcc_op, cond; TCGMemOp size; CCPrepare cc; TCGv t0; @@ -1144,10 +1144,10 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) jcc_op = (b >> 1) & 7; switch (s->cc_op) { - case CC_OP_SUBB: - case CC_OP_SUBW: - case CC_OP_SUBL: - case CC_OP_SUBQ: + case CC_OP_SUBB: + case CC_OP_SUBW: + case CC_OP_SUBL: + case CC_OP_SUBQ: /* We optimize relational operators for the cmp/jcc case. */ size = s->cc_op - CC_OP_SUBB; switch (jcc_op) { @@ -1155,7 +1155,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) tcg_gen_mov_tl(tcg_ctx, cpu_tmp4, cpu_cc_srcT); gen_extu(tcg_ctx, size, cpu_tmp4); t0 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, false); - cc = ccprepare_make(TCG_COND_LEU, cpu_tmp4,t0, 0,-1, true,false); + cc = ccprepare_make(TCG_COND_LEU, cpu_tmp4,t0, 0,-1, true,false); break; case JCC_L: @@ -1167,7 +1167,7 @@ static CCPrepare gen_prepare_cc(DisasContext *s, int b, TCGv reg) tcg_gen_mov_tl(tcg_ctx, cpu_tmp4, cpu_cc_srcT); gen_exts(tcg_ctx, size, cpu_tmp4); t0 = gen_ext_tl(tcg_ctx, cpu_tmp0, cpu_cc_src, size, true); - cc = ccprepare_make(cond, cpu_tmp4,t0, 0,-1, true,false); + cc = ccprepare_make(cond, cpu_tmp4,t0, 0,-1, true,false); break; default: @@ -3018,9 +3018,9 @@ typedef void (*SSEFunc_0_eppt)(TCGContext *s, TCGv_ptr env, TCGv_ptr reg_a, TCGv static const SSEFunc_0_epp sse_op_table1[256][4] = { // filler: 0x00 - 0x0e - {0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}, - - /* 3DNow! extensions */ + {0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0},{0}, + + /* 3DNow! extensions */ { SSE_DUMMY }, /* femms */ { SSE_DUMMY }, /* pf. . . */ @@ -3033,12 +3033,12 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = { { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm }, { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */ { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */ - - // filler: 0x18 - 0x27 - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - /* pure SSE operations */ - { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ + // filler: 0x18 - 0x27 + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + + /* pure SSE operations */ + { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */ { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */ { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */ @@ -3047,19 +3047,19 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = { { gen_helper_ucomiss, gen_helper_ucomisd }, { gen_helper_comiss, gen_helper_comisd }, - // filler: 0x30 - 0x37 - {0},{0},{0},{0},{0},{0},{0},{0}, + // filler: 0x30 - 0x37 + {0},{0},{0},{0},{0},{0},{0},{0}, /* SSSE3, SSE4, MOVBE, CRC32, BMI1, BMI2, ADX. */ { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, - {0}, // filler: 0x39 + {0}, // filler: 0x39 { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, - - // filler: 0x3b - 0x4f - {0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - /* pure SSE operations */ - { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ + // filler: 0x3b - 0x4f + {0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + + /* pure SSE operations */ + { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */ SSE_FOP(sqrt), { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL }, { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL }, @@ -3107,35 +3107,35 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = { { SSE_DUMMY }, /* emms */ { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */ { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r }, - {0},{0}, // filler: 0x7a - 0x7b + {0},{0}, // filler: 0x7a - 0x7b { NULL, gen_helper_haddpd, NULL, gen_helper_haddps }, { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps }, { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */ { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */ - - // filler: 0x80 - 0xc1 - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + + // filler: 0x80 - 0xc1 + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0}, - SSE_FOP(cmpeq), + SSE_FOP(cmpeq), - // filler: 0xc3 - {0}, + // filler: 0xc3 + {0}, /* MMX ops and their SSE extensions */ - { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ + { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */ { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */ - - { (SSEFunc_0_epp)gen_helper_shufps, + + { (SSEFunc_0_epp)gen_helper_shufps, (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */ - // filler: 0xc7 - 0xcf - {0}, {0},{0},{0},{0},{0},{0},{0},{0}, + // filler: 0xc7 - 0xcf + {0}, {0},{0},{0},{0},{0},{0},{0},{0}, - /* MMX ops and their SSE extensions */ + /* MMX ops and their SSE extensions */ { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps }, MMX_OP2(psrlw), MMX_OP2(psrld), @@ -3185,32 +3185,32 @@ static const SSEFunc_0_epp sse_op_table1[256][4] = { MMX_OP2(paddw), MMX_OP2(paddl), - // filler: 0xff - {0}, + // filler: 0xff + {0}, }; static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = { #ifdef _MSC_VER - {0},{0}, - MMX_OP2(psrlw), + {0},{0}, + MMX_OP2(psrlw), {0}, - MMX_OP2(psraw), + MMX_OP2(psraw), {0}, - MMX_OP2(psllw), + MMX_OP2(psllw), {0},{0},{0}, - MMX_OP2(psrld), + MMX_OP2(psrld), + {0}, + MMX_OP2(psrad), {0}, - MMX_OP2(psrad), - {0}, MMX_OP2(pslld), - {0},{0},{0}, + {0},{0},{0}, MMX_OP2(psrlq), { NULL, gen_helper_psrldq_xmm }, - {0},{0}, + {0},{0}, MMX_OP2(psllq), { NULL, gen_helper_pslldq_xmm }, #else - [0 + 2] = MMX_OP2(psrlw), + [0 + 2] = MMX_OP2(psrlw), [0 + 4] = MMX_OP2(psraw), [0 + 6] = MMX_OP2(psllw), [8 + 2] = MMX_OP2(psrld), @@ -3264,64 +3264,64 @@ static const SSEFunc_0_epp sse_op_table4[8][4] = { static const SSEFunc_0_epp sse_op_table5[256] = { #ifdef _MSC_VER - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0}, // filler: 0x00 - 0x0b - gen_helper_pi2fw, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0}, // filler: 0x00 - 0x0b + gen_helper_pi2fw, gen_helper_pi2fd, - {0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0}, // filler: 0x0e - 0x01b - gen_helper_pf2iw, + {0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0}, // filler: 0x0e - 0x01b + gen_helper_pf2iw, gen_helper_pf2id, - // filler: 0x1e - 0x89 - {0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0}, - gen_helper_pfnacc, - {0},{0},{0}, // filler: 0x8b - 0x8d + // filler: 0x1e - 0x89 + {0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0}, + gen_helper_pfnacc, + {0},{0},{0}, // filler: 0x8b - 0x8d gen_helper_pfpnacc, - {0}, // filler: 0x8f + {0}, // filler: 0x8f gen_helper_pfcmpge, - {0},{0},{0}, // filler: 0x91 - 0x93 + {0},{0},{0}, // filler: 0x91 - 0x93 gen_helper_pfmin, - {0}, // filler: 0x95 + {0}, // filler: 0x95 gen_helper_pfrcp, gen_helper_pfrsqrt, - {0},{0}, // filler: 0x98 - 0x99 + {0},{0}, // filler: 0x98 - 0x99 gen_helper_pfsub, - {0},{0},{0}, // filler: 0x9b - 0x9d + {0},{0},{0}, // filler: 0x9b - 0x9d gen_helper_pfadd, - {0}, // filler: 0x9f + {0}, // filler: 0x9f gen_helper_pfcmpgt, - {0},{0},{0}, // filler: 0xa1 - 0xa3 + {0},{0},{0}, // filler: 0xa1 - 0xa3 gen_helper_pfmax, - {0}, // filler: 0xa5 + {0}, // filler: 0xa5 gen_helper_movq, /* pfrcpit1; no need to actually increase precision */ gen_helper_movq, /* pfrsqit1 */ {0},{0}, // filler: 0xa8 - 0xa9 - gen_helper_pfsubr, - {0},{0},{0}, // filler: 0xab - 0xad + gen_helper_pfsubr, + {0},{0},{0}, // filler: 0xab - 0xad gen_helper_pfacc, - {0}, // filler: 0xaf + {0}, // filler: 0xaf gen_helper_pfcmpeq, - {0},{0},{0}, // filler: 0xb1 - 0xb3 + {0},{0},{0}, // filler: 0xb1 - 0xb3 gen_helper_pfmul, - {0}, // filler: 0xb5 + {0}, // filler: 0xb5 gen_helper_movq, /* pfrcpit2 */ gen_helper_pmulhrw_mmx, - {0},{0},{0}, // filler: 0xb8 - 0xba + {0},{0},{0}, // filler: 0xb8 - 0xba gen_helper_pswapd, - {0},{0},{0}, // filler: 0xbc - 0xbe + {0},{0},{0}, // filler: 0xbc - 0xbe gen_helper_pavgb_mmx, /* pavgusb */ - // filler: 0xc0 - 0xff - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, - {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + // filler: 0xc0 - 0xff + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, + {0},{0},{0},{0},{0},{0},{0},{0}, {0},{0},{0},{0},{0},{0},{0},{0}, #else - [0x0c] = gen_helper_pi2fw, + [0x0c] = gen_helper_pi2fw, [0x0d] = gen_helper_pi2fd, [0x1c] = gen_helper_pf2iw, [0x1d] = gen_helper_pf2id, @@ -3379,37 +3379,37 @@ static const struct SSEOpHelper_epp sse_op_table6[256] = { SSSE3_OP(psignw), SSSE3_OP(psignd), SSSE3_OP(pmulhrsw), - {{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x0c - 0x0f - SSE41_OP(pblendvb), - {{0},0},{{0},0},{{0},0}, // filler: 0x11 - 0x13 + {{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x0c - 0x0f + SSE41_OP(pblendvb), + {{0},0},{{0},0},{{0},0}, // filler: 0x11 - 0x13 SSE41_OP(blendvps), SSE41_OP(blendvpd), - {{0},0}, // filler: 0x16 + {{0},0}, // filler: 0x16 SSE41_OP(ptest), - {{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x18 - 0x1b + {{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x18 - 0x1b SSSE3_OP(pabsb), SSSE3_OP(pabsw), SSSE3_OP(pabsd), - {{0},0}, // filler: 0x1f + {{0},0}, // filler: 0x1f SSE41_OP(pmovsxbw), SSE41_OP(pmovsxbd), SSE41_OP(pmovsxbq), SSE41_OP(pmovsxwd), SSE41_OP(pmovsxwq), SSE41_OP(pmovsxdq), - {{0},0},{{0},0}, // filler: 0x26 - 0x27 + {{0},0},{{0},0}, // filler: 0x26 - 0x27 SSE41_OP(pmuldq), SSE41_OP(pcmpeqq), SSE41_SPECIAL, /* movntqda */ SSE41_OP(packusdw), - {{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x2c - 0x2f + {{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x2c - 0x2f SSE41_OP(pmovzxbw), SSE41_OP(pmovzxbd), SSE41_OP(pmovzxbq), SSE41_OP(pmovzxwd), SSE41_OP(pmovzxwq), SSE41_OP(pmovzxdq), - {{0},0}, // filler: 0x36 + {{0},0}, // filler: 0x36 SSE42_OP(pcmpgtq), SSE41_OP(pminsb), SSE41_OP(pminsd), @@ -3421,31 +3421,31 @@ static const struct SSEOpHelper_epp sse_op_table6[256] = { SSE41_OP(pmaxud), SSE41_OP(pmulld), SSE41_OP(phminposuw), - // filler: 0x42 - 0xda - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0}, + // filler: 0x42 - 0xda + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0}, AESNI_OP(aesimc), AESNI_OP(aesenc), AESNI_OP(aesenclast), AESNI_OP(aesdec), AESNI_OP(aesdeclast), - // filler: 0xe0 - 0xff - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + // filler: 0xe0 - 0xff + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, }; static const struct SSEOpHelper_eppi sse_op_table7[256] = { #ifdef _MSC_VER - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x00 - 0x07 - SSE41_OP(roundps), + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x00 - 0x07 + SSE41_OP(roundps), SSE41_OP(roundpd), SSE41_OP(roundss), SSE41_OP(roundsd), @@ -3453,45 +3453,45 @@ static const struct SSEOpHelper_eppi sse_op_table7[256] = { SSE41_OP(blendpd), SSE41_OP(pblendw), SSSE3_OP(palignr), - {{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x10 - 0x13 + {{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x10 - 0x13 SSE41_SPECIAL, /* pextrb */ SSE41_SPECIAL, /* pextrw */ SSE41_SPECIAL, /* pextrd/pextrq */ SSE41_SPECIAL, /* extractps */ {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, // filler: 0x18 - 0x1f - SSE41_SPECIAL, /* pinsrb */ + SSE41_SPECIAL, /* pinsrb */ SSE41_SPECIAL, /* insertps */ SSE41_SPECIAL, /* pinsrd/pinsrq */ - // filler: 0x23 - 0x3f - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + // filler: 0x23 - 0x3f + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, SSE41_OP(dpps), SSE41_OP(dppd), SSE41_OP(mpsadbw), - {{0},0}, // filler: 0x43 + {{0},0}, // filler: 0x43 PCLMULQDQ_OP(pclmulqdq), // filler: 0x45 - 0x5f - {{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, SSE42_OP(pcmpestrm), SSE42_OP(pcmpestri), SSE42_OP(pcmpistrm), SSE42_OP(pcmpistri), // filler: 0x64 - 0xde - {{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, AESNI_OP(aeskeygenassist), - // filler: 0xe0 - 0xff - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, - {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + // filler: 0xe0 - 0xff + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, + {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, {{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0},{{0},0}, #else - [0x08] = SSE41_OP(roundps), + [0x08] = SSE41_OP(roundps), [0x09] = SSE41_OP(roundpd), [0x0a] = SSE41_OP(roundss), [0x0b] = SSE41_OP(roundsd), @@ -4850,19 +4850,19 @@ static void gen_sse(CPUX86State *env, DisasContext *s, int b, op2_offset = offsetof(CPUX86State,xmm_t0); if( (b >= 0x50 && b <= 0x5a) || - (b >= 0x5c && b <= 0x5f) || - b == 0xc2 ) - { + (b >= 0x5c && b <= 0x5f) || + b == 0xc2 ) + { /* Most sse scalar operations. */ if (b1 == 2) { sz = 2; } else if (b1 == 3) { sz = 3; } - } - else if( b == 0x2e || /* ucomis[sd] */ - b == 0x2f ) /* comis[sd] */ - { + } + else if( b == 0x2e || /* ucomis[sd] */ + b == 0x2f ) /* comis[sd] */ + { if (b1 == 0) { sz = 2; } else { @@ -5092,22 +5092,22 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, prefixes |= PREFIX_ADR; goto next_byte; #ifdef TARGET_X86_64 - case 0x40: - case 0x41: - case 0x42: - case 0x43: - case 0x44: - case 0x45: - case 0x46: - case 0x47: - case 0x48: - case 0x49: - case 0x4a: - case 0x4b: - case 0x4c: - case 0x4d: - case 0x4e: - case 0x4f: + case 0x40: + case 0x41: + case 0x42: + case 0x43: + case 0x44: + case 0x45: + case 0x46: + case 0x47: + case 0x48: + case 0x49: + case 0x4a: + case 0x4b: + case 0x4c: + case 0x4d: + case 0x4e: + case 0x4f: if (CODE64(s)) { /* REX prefix */ rex_w = (b >> 3) & 1; @@ -5220,14 +5220,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /**************************/ /* arith & logic */ - case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: //case 0x00 ... 0x05: - case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: //case 0x08 ... 0x0d: - case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: //case 0x10 ... 0x15: - case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: //case 0x18 ... 0x1d: - case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: //case 0x20 ... 0x25: - case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: //case 0x28 ... 0x2d: - case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: //case 0x30 ... 0x35: - case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: //case 0x38 ... 0x3d: + case 0x00: case 0x01: case 0x02: case 0x03: case 0x04: case 0x05: //case 0x00 ... 0x05: + case 0x08: case 0x09: case 0x0a: case 0x0b: case 0x0c: case 0x0d: //case 0x08 ... 0x0d: + case 0x10: case 0x11: case 0x12: case 0x13: case 0x14: case 0x15: //case 0x10 ... 0x15: + case 0x18: case 0x19: case 0x1a: case 0x1b: case 0x1c: case 0x1d: //case 0x18 ... 0x1d: + case 0x20: case 0x21: case 0x22: case 0x23: case 0x24: case 0x25: //case 0x20 ... 0x25: + case 0x28: case 0x29: case 0x2a: case 0x2b: case 0x2c: case 0x2d: //case 0x28 ... 0x2d: + case 0x30: case 0x31: case 0x32: case 0x33: case 0x34: case 0x35: //case 0x30 ... 0x35: + case 0x38: case 0x39: case 0x3a: case 0x3b: case 0x3c: case 0x3d: //case 0x38 ... 0x3d: { int op, f, val; op = (b >> 3) & 7; @@ -5326,13 +5326,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /**************************/ /* inc, dec, and other misc arith */ - case 0x40: case 0x41: case 0x42: case 0x43: - case 0x44: case 0x45: case 0x46: case 0x47: //case 0x40 ... 0x47: /* inc Gv */ + case 0x40: case 0x41: case 0x42: case 0x43: + case 0x44: case 0x45: case 0x46: case 0x47: //case 0x40 ... 0x47: /* inc Gv */ ot = dflag; gen_inc(s, ot, OR_EAX + (b & 7), 1); break; - case 0x48: case 0x49: case 0x4a: case 0x4b: - case 0x4c: case 0x4d: case 0x4e: case 0x4f: //case 0x48 ... 0x4f: /* dec Gv */ + case 0x48: case 0x49: case 0x4a: case 0x4b: + case 0x4c: case 0x4d: case 0x4e: case 0x4f: //case 0x48 ... 0x4f: /* dec Gv */ ot = dflag; gen_inc(s, ot, OR_EAX + (b & 7), -1); break; @@ -5873,13 +5873,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /**************************/ /* push/pop */ - case 0x50: case 0x51: case 0x52: case 0x53: - case 0x54: case 0x55: case 0x56: case 0x57: //case 0x50 ... 0x57: /* push */ + case 0x50: case 0x51: case 0x52: case 0x53: + case 0x54: case 0x55: case 0x56: case 0x57: //case 0x50 ... 0x57: /* push */ gen_op_mov_v_reg(tcg_ctx, MO_32, *cpu_T[0], (b & 7) | REX_B(s)); gen_push_v(s, *cpu_T[0]); break; - case 0x58: case 0x59: case 0x5a: case 0x5b: - case 0x5c: case 0x5d: case 0x5e: case 0x5f: //case 0x58 ... 0x5f: /* pop */ + case 0x58: case 0x59: case 0x5a: case 0x5b: + case 0x5c: case 0x5d: case 0x5e: case 0x5f: //case 0x58 ... 0x5f: /* pop */ ot = gen_pop_T0(s); /* NOTE: order is important for pop %sp */ gen_pop_update(s, ot); @@ -6163,14 +6163,14 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_op_ld_v(s, MO_8, *cpu_T[0], cpu_A0); gen_op_mov_reg_v(tcg_ctx, MO_8, R_EAX, *cpu_T[0]); break; - case 0xb0: case 0xb1: case 0xb2: case 0xb3: - case 0xb4: case 0xb5: case 0xb6: case 0xb7: //case 0xb0 ... 0xb7: /* mov R, Ib */ + case 0xb0: case 0xb1: case 0xb2: case 0xb3: + case 0xb4: case 0xb5: case 0xb6: case 0xb7: //case 0xb0 ... 0xb7: /* mov R, Ib */ val = insn_get(env, s, MO_8); tcg_gen_movi_tl(tcg_ctx, *cpu_T[0], val); gen_op_mov_reg_v(tcg_ctx, MO_8, (b & 7) | REX_B(s), *cpu_T[0]); break; - case 0xb8: case 0xb9: case 0xba: case 0xbb: - case 0xbc: case 0xbd: case 0xbe: case 0xbf: //case 0xb8 ... 0xbf: /* mov R, Iv */ + case 0xb8: case 0xb9: case 0xba: case 0xbb: + case 0xbc: case 0xbd: case 0xbe: case 0xbf: //case 0xb8 ... 0xbf: /* mov R, Iv */ #ifdef TARGET_X86_64 if (dflag == MO_64) { uint64_t tmp; @@ -6191,8 +6191,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } break; - case 0x91: case 0x92: case 0x93: - case 0x94: case 0x95: case 0x96: case 0x97: //case 0x91 ... 0x97: /* xchg R, EAX */ + case 0x91: case 0x92: case 0x93: + case 0x94: case 0x95: case 0x96: case 0x97: //case 0x91 ... 0x97: /* xchg R, EAX */ do_xchg_reg_eax: ot = dflag; reg = (b & 7) | REX_B(s); @@ -6346,8 +6346,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /************************/ /* floats */ - case 0xd8: case 0xd9: case 0xda: case 0xdb: - case 0xdc: case 0xdd: case 0xde: case 0xdf: //case 0xd8 ... 0xdf: + case 0xd8: case 0xd9: case 0xda: case 0xdb: + case 0xdc: case 0xdd: case 0xde: case 0xdf: //case 0xd8 ... 0xdf: if (s->flags & (HF_EM_MASK | HF_TS_MASK)) { /* if CR0.EM or CR0.TS are set, generate an FPU exception */ /* XXX: what to do if illegal op ? */ @@ -6362,10 +6362,10 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, /* memory op */ gen_lea_modrm(env, s, modrm); - if( (op >= 0x00 && op <= 0x07) || /* fxxxs */ - (op >= 0x10 && op <= 0x17) || /* fixxxl */ - (op >= 0x20 && op <= 0x27) || /* fxxxl */ - (op >= 0x30 && op <= 0x37) ) /* fixxx */ + if( (op >= 0x00 && op <= 0x07) || /* fxxxs */ + (op >= 0x10 && op <= 0x17) || /* fixxxl */ + (op >= 0x20 && op <= 0x27) || /* fxxxl */ + (op >= 0x30 && op <= 0x37) ) /* fixxx */ { int op1; op1 = op & 7; @@ -6401,13 +6401,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } fpu_update_ip(env, pc_start); } - else if((op == 0x08) || /* flds */ - (op == 0x0a) || /* fsts */ - (op == 0x0b) || /* fstps */ - (op >= 0x18 && op <= 0x1b) || /* fildl, fisttpl, fistl, fistpl */ - (op >= 0x28 && op <= 0x2b) || /* fldl, fisttpll, fstl, fstpl */ - (op >= 0x38 && op <= 0x3b) ) /* filds, fisttps, fists, fistps */ - { + else if((op == 0x08) || /* flds */ + (op == 0x0a) || /* fsts */ + (op == 0x0b) || /* fstps */ + (op >= 0x18 && op <= 0x1b) || /* fildl, fisttpl, fistl, fistpl */ + (op >= 0x28 && op <= 0x2b) || /* fldl, fisttpll, fstl, fstpl */ + (op >= 0x38 && op <= 0x3b) ) /* filds, fisttps, fists, fistps */ + { switch(op & 7) { case 0: switch(op >> 4) { @@ -6485,94 +6485,94 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; } fpu_update_ip(env, pc_start); - } - else if(op == 0x0c) /* fldenv mem */ - { + } + else if(op == 0x0c) /* fldenv mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fldenv(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1)); - } - else if(op == 0x0d) /* fldcw mem */ - { + } + else if(op == 0x0d) /* fldcw mem */ + { tcg_gen_qemu_ld_i32(s->uc, cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUW); gen_helper_fldcw(tcg_ctx, cpu_env, cpu_tmp2_i32); - } - else if(op == 0x0e) /* fnstenv mem */ - { + } + else if(op == 0x0e) /* fnstenv mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fstenv(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1)); - } - else if(op == 0x0f) /* fnstcw mem */ - { + } + else if(op == 0x0f) /* fnstcw mem */ + { gen_helper_fnstcw(tcg_ctx, cpu_tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUW); - } - else if(op == 0x1d) /* fldt mem */ - { + } + else if(op == 0x1d) /* fldt mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fldt_ST0(tcg_ctx, cpu_env, cpu_A0); fpu_update_ip(env, pc_start); - } - else if(op == 0x1f) /* fstpt mem */ - { + } + else if(op == 0x1f) /* fstpt mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fstt_ST0(tcg_ctx, cpu_env, cpu_A0); gen_helper_fpop(tcg_ctx, cpu_env); fpu_update_ip(env, pc_start); - } - else if(op == 0x2c) /* frstor mem */ - { + } + else if(op == 0x2c) /* frstor mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_frstor(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1)); - } - else if(op == 0x2e) /* fnsave mem */ - { + } + else if(op == 0x2e) /* fnsave mem */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fsave(tcg_ctx, cpu_env, cpu_A0, tcg_const_i32(tcg_ctx, dflag - 1)); - } - else if(op == 0x2f) /* fnstsw mem */ - { + } + else if(op == 0x2f) /* fnstsw mem */ + { gen_helper_fnstsw(tcg_ctx, cpu_tmp2_i32, cpu_env); tcg_gen_qemu_st_i32(s->uc, cpu_tmp2_i32, cpu_A0, s->mem_index, MO_LEUW); - } - else if(op == 0x3c) /* fbld */ - { + } + else if(op == 0x3c) /* fbld */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fbld_ST0(tcg_ctx, cpu_env, cpu_A0); fpu_update_ip(env, pc_start); - } - else if(op == 0x3e) /* fbstp */ - { + } + else if(op == 0x3e) /* fbstp */ + { gen_update_cc_op(s); gen_jmp_im(s, pc_start - s->cs_base); gen_helper_fbst_ST0(tcg_ctx, cpu_env, cpu_A0); gen_helper_fpop(tcg_ctx, cpu_env); fpu_update_ip(env, pc_start); - } - else if(op == 0x3d) /* fildll */ - { + } + else if(op == 0x3d) /* fildll */ + { tcg_gen_qemu_ld_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); gen_helper_fildll_ST0(tcg_ctx, cpu_env, cpu_tmp1_i64); fpu_update_ip(env, pc_start); - } - else if(op == 0x3f) /* fistpll */ - { + } + else if(op == 0x3f) /* fistpll */ + { gen_helper_fistll_ST0(tcg_ctx, cpu_tmp1_i64, cpu_env); tcg_gen_qemu_st_i64(s->uc, cpu_tmp1_i64, cpu_A0, s->mem_index, MO_LEQ); gen_helper_fpop(tcg_ctx, cpu_env); fpu_update_ip(env, pc_start); - } - else - { + } + else + { goto illegal_op; } } else { @@ -6715,8 +6715,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; } break; - case 0x00: case 0x01: case 0x04: case 0x05: case 0x06: case 0x07: /* fxxx st, sti */ - case 0x20: case 0x21: case 0x24: case 0x25: case 0x26: case 0x27: /* fxxx sti, st */ + case 0x00: case 0x01: case 0x04: case 0x05: case 0x06: case 0x07: /* fxxx st, sti */ + case 0x20: case 0x21: case 0x24: case 0x25: case 0x26: case 0x27: /* fxxx sti, st */ case 0x30: case 0x31: case 0x34: case 0x35: case 0x36: case 0x37: /* fxxxp sti, st */ { int op1; @@ -6861,8 +6861,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_fpop(tcg_ctx, cpu_env); set_cc_op(s, CC_OP_EFLAGS); break; - case 0x10: case 0x11: case 0x12: case 0x13: /* fcmovxx */ - case 0x18: case 0x19: case 0x1a: case 0x1b: + case 0x10: case 0x11: case 0x12: case 0x13: /* fcmovxx */ + case 0x18: case 0x19: case 0x1a: case 0x1b: { int op1, l1; static const uint8_t fcmov_cc[8] = { @@ -7155,13 +7155,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_jmp(s, tval); break; //case 0x70 ... 0x7f: /* jcc Jb */ - case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: - case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: + case 0x70: case 0x71: case 0x72: case 0x73: case 0x74: case 0x75: case 0x76: case 0x77: + case 0x78: case 0x79: case 0x7a: case 0x7b: case 0x7c: case 0x7d: case 0x7e: case 0x7f: tval = (int8_t)insn_get(env, s, MO_8); goto do_jcc; //case 0x180 ... 0x18f: /* jcc Jv */ - case 0x180: case 0x181: case 0x182: case 0x183: case 0x184: case 0x185: case 0x186: case 0x187: - case 0x188: case 0x189: case 0x18a: case 0x18b: case 0x18c: case 0x18d: case 0x18e: case 0x18f: + case 0x180: case 0x181: case 0x182: case 0x183: case 0x184: case 0x185: case 0x186: case 0x187: + case 0x188: case 0x189: case 0x18a: case 0x18b: case 0x18c: case 0x18d: case 0x18e: case 0x18f: if (dflag != MO_16) { tval = (int32_t)insn_get(env, s, MO_32); } else { @@ -7177,15 +7177,15 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, break; //case 0x190 ... 0x19f: /* setcc Gv */ - case 0x190: case 0x191: case 0x192: case 0x193: case 0x194: case 0x195: case 0x196: case 0x197: - case 0x198: case 0x199: case 0x19a: case 0x19b: case 0x19c: case 0x19d: case 0x19e: case 0x19f: + case 0x190: case 0x191: case 0x192: case 0x193: case 0x194: case 0x195: case 0x196: case 0x197: + case 0x198: case 0x199: case 0x19a: case 0x19b: case 0x19c: case 0x19d: case 0x19e: case 0x19f: modrm = cpu_ldub_code(env, s->pc++); gen_setcc1(s, b, *cpu_T[0]); gen_ldst_modrm(env, s, modrm, MO_8, OR_TMP0, 1); break; //case 0x140 ... 0x14f: /* cmov Gv, Ev */ - case 0x140: case 0x141: case 0x142: case 0x143: case 0x144: case 0x145: case 0x146: case 0x147: - case 0x148: case 0x149: case 0x14a: case 0x14b: case 0x14c: case 0x14d: case 0x14e: case 0x14f: + case 0x140: case 0x141: case 0x142: case 0x143: case 0x144: case 0x145: case 0x146: case 0x147: + case 0x148: case 0x149: case 0x14a: case 0x14b: case 0x14c: case 0x14d: case 0x14e: case 0x14f: if (!(s->cpuid_features & CPUID_CMOV)) { goto illegal_op; } @@ -7393,13 +7393,13 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, case CC_OP_ADDB: case CC_OP_ADDW: case CC_OP_ADDL: case CC_OP_ADDQ: //case CC_OP_ADDB ... CC_OP_ADDQ: case CC_OP_ADCB: case CC_OP_ADCW: case CC_OP_ADCL: case CC_OP_ADCQ: //case CC_OP_ADCB ... CC_OP_ADCQ: case CC_OP_SUBB: case CC_OP_SUBW: case CC_OP_SUBL: case CC_OP_SUBQ: //case CC_OP_SUBB ... CC_OP_SUBQ: - case CC_OP_SBBB: case CC_OP_SBBW: case CC_OP_SBBL: case CC_OP_SBBQ: //case CC_OP_SBBB ... CC_OP_SBBQ: - case CC_OP_LOGICB: case CC_OP_LOGICW: case CC_OP_LOGICL: case CC_OP_LOGICQ: //case CC_OP_LOGICB ... CC_OP_LOGICQ: - case CC_OP_INCB: case CC_OP_INCW: case CC_OP_INCL: case CC_OP_INCQ: //case CC_OP_INCB ... CC_OP_INCQ: - case CC_OP_DECB: case CC_OP_DECW: case CC_OP_DECL: case CC_OP_DECQ: //case CC_OP_DECB ... CC_OP_DECQ: - case CC_OP_SHLB: case CC_OP_SHLW: case CC_OP_SHLL: case CC_OP_SHLQ: //case CC_OP_SHLB ... CC_OP_SHLQ: - case CC_OP_SARB: case CC_OP_SARW: case CC_OP_SARL: case CC_OP_SARQ: //case CC_OP_SARB ... CC_OP_SARQ: - case CC_OP_BMILGB: case CC_OP_BMILGW: case CC_OP_BMILGL: case CC_OP_BMILGQ: //case CC_OP_BMILGB ... CC_OP_BMILGQ: + case CC_OP_SBBB: case CC_OP_SBBW: case CC_OP_SBBL: case CC_OP_SBBQ: //case CC_OP_SBBB ... CC_OP_SBBQ: + case CC_OP_LOGICB: case CC_OP_LOGICW: case CC_OP_LOGICL: case CC_OP_LOGICQ: //case CC_OP_LOGICB ... CC_OP_LOGICQ: + case CC_OP_INCB: case CC_OP_INCW: case CC_OP_INCL: case CC_OP_INCQ: //case CC_OP_INCB ... CC_OP_INCQ: + case CC_OP_DECB: case CC_OP_DECW: case CC_OP_DECL: case CC_OP_DECQ: //case CC_OP_DECB ... CC_OP_DECQ: + case CC_OP_SHLB: case CC_OP_SHLW: case CC_OP_SHLL: case CC_OP_SHLQ: //case CC_OP_SHLB ... CC_OP_SHLQ: + case CC_OP_SARB: case CC_OP_SARW: case CC_OP_SARL: case CC_OP_SARQ: //case CC_OP_SARB ... CC_OP_SARQ: + case CC_OP_BMILGB: case CC_OP_BMILGW: case CC_OP_BMILGL: case CC_OP_BMILGQ: //case CC_OP_BMILGB ... CC_OP_BMILGQ: /* Z was going to be computed from the non-zero status of CC_DST. We can get that same Z value (and the new C value) by leaving CC_DST alone, setting CC_SRC, and using a CC_OP_SAR of the @@ -7632,8 +7632,8 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, gen_helper_boundl(tcg_ctx, cpu_env, cpu_A0, cpu_tmp2_i32); } break; - case 0x1c8: case 0x1c9: case 0x1ca: case 0x1cb: - case 0x1cc: case 0x1cd: case 0x1ce: case 0x1cf: /* bswap reg */ + case 0x1c8: case 0x1c9: case 0x1ca: case 0x1cb: + case 0x1cc: case 0x1cd: case 0x1ce: case 0x1cf: /* bswap reg */ reg = (b & 7) | REX_B(s); #ifdef TARGET_X86_64 if (dflag == MO_64) { @@ -8239,7 +8239,7 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, } break; //case 0x119 ... 0x11f: /* nop (multi byte) */ - case 0x119: case 0x11a: case 0x11b: case 0x11c: case 0x11d: case 0x11e: case 0x11f: + case 0x119: case 0x11a: case 0x11b: case 0x11c: case 0x11d: case 0x11e: case 0x11f: modrm = cpu_ldub_code(env, s->pc++); gen_nop_modrm(env, s, modrm); break; @@ -8456,30 +8456,30 @@ static target_ulong disas_insn(CPUX86State *env, DisasContext *s, set_cc_op(s, CC_OP_EFLAGS); break; - case 0x10e: case 0x10f: + case 0x10e: case 0x10f: /* 3DNow! instructions, ignore prefixes */ s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA); case 0x110: case 0x111: case 0x112: case 0x113: case 0x114: case 0x115: case 0x116: case 0x117: //case 0x110 ... 0x117: case 0x128: case 0x129: case 0x12a: case 0x12b: case 0x12c: case 0x12d: case 0x12e: case 0x12f: //case 0x128 ... 0x12f: - case 0x138: case 0x139: case 0x13a: - // case 0x150 ... 0x179: - case 0x150: case 0x151: case 0x152: case 0x153: case 0x154: case 0x155: case 0x156: case 0x157: - case 0x158: case 0x159: case 0x15a: case 0x15b: case 0x15c: case 0x15d: case 0x15e: case 0x15f: - case 0x160: case 0x161: case 0x162: case 0x163: case 0x164: case 0x165: case 0x166: case 0x167: - case 0x168: case 0x169: case 0x16a: case 0x16b: case 0x16c: case 0x16d: case 0x16e: case 0x16f: - case 0x170: case 0x171: case 0x172: case 0x173: case 0x174: case 0x175: case 0x176: case 0x177: - case 0x178: case 0x179: + case 0x138: case 0x139: case 0x13a: + // case 0x150 ... 0x179: + case 0x150: case 0x151: case 0x152: case 0x153: case 0x154: case 0x155: case 0x156: case 0x157: + case 0x158: case 0x159: case 0x15a: case 0x15b: case 0x15c: case 0x15d: case 0x15e: case 0x15f: + case 0x160: case 0x161: case 0x162: case 0x163: case 0x164: case 0x165: case 0x166: case 0x167: + case 0x168: case 0x169: case 0x16a: case 0x16b: case 0x16c: case 0x16d: case 0x16e: case 0x16f: + case 0x170: case 0x171: case 0x172: case 0x173: case 0x174: case 0x175: case 0x176: case 0x177: + case 0x178: case 0x179: // case 0x17c ... 0x17f: - case 0x17c: case 0x17d: case 0x17e: case 0x17f: + case 0x17c: case 0x17d: case 0x17e: case 0x17f: case 0x1c2: - case 0x1c4: case 0x1c5: case 0x1c6: + case 0x1c4: case 0x1c5: case 0x1c6: //case 0x1d0 ... 0x1fe: - case 0x1d0: case 0x1d1: case 0x1d2: case 0x1d3: case 0x1d4: case 0x1d5: case 0x1d6: case 0x1d7: - case 0x1d8: case 0x1d9: case 0x1da: case 0x1db: case 0x1dc: case 0x1dd: case 0x1de: case 0x1df: - case 0x1e0: case 0x1e1: case 0x1e2: case 0x1e3: case 0x1e4: case 0x1e5: case 0x1e6: case 0x1e7: - case 0x1e8: case 0x1e9: case 0x1ea: case 0x1eb: case 0x1ec: case 0x1ed: case 0x1ee: case 0x1ef: - case 0x1f0: case 0x1f1: case 0x1f2: case 0x1f3: case 0x1f4: case 0x1f5: case 0x1f6: case 0x1f7: - case 0x1f8: case 0x1f9: case 0x1fa: case 0x1fb: case 0x1fc: case 0x1fd: case 0x1fe: + case 0x1d0: case 0x1d1: case 0x1d2: case 0x1d3: case 0x1d4: case 0x1d5: case 0x1d6: case 0x1d7: + case 0x1d8: case 0x1d9: case 0x1da: case 0x1db: case 0x1dc: case 0x1dd: case 0x1de: case 0x1df: + case 0x1e0: case 0x1e1: case 0x1e2: case 0x1e3: case 0x1e4: case 0x1e5: case 0x1e6: case 0x1e7: + case 0x1e8: case 0x1e9: case 0x1ea: case 0x1eb: case 0x1ec: case 0x1ed: case 0x1ee: case 0x1ef: + case 0x1f0: case 0x1f1: case 0x1f2: case 0x1f3: case 0x1f4: case 0x1f5: case 0x1f6: case 0x1f7: + case 0x1f8: case 0x1f9: case 0x1fa: case 0x1fb: case 0x1fc: case 0x1fd: case 0x1fe: gen_sse(env, s, b, pc_start, rex_r); break; default: diff --git a/qemu/target-i386/unicorn.c b/qemu/target-i386/unicorn.c index 45838697..c261f200 100644 --- a/qemu/target-i386/unicorn.c +++ b/qemu/target-i386/unicorn.c @@ -150,14 +150,14 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun switch(regid) { default: break; - case UC_X86_REG_FP0: - case UC_X86_REG_FP1: - case UC_X86_REG_FP2: - case UC_X86_REG_FP3: - case UC_X86_REG_FP4: - case UC_X86_REG_FP5: - case UC_X86_REG_FP6: - case UC_X86_REG_FP7: + case UC_X86_REG_FP0: + case UC_X86_REG_FP1: + case UC_X86_REG_FP2: + case UC_X86_REG_FP3: + case UC_X86_REG_FP4: + case UC_X86_REG_FP5: + case UC_X86_REG_FP6: + case UC_X86_REG_FP7: { floatx80 reg = X86_CPU(uc, mycpu)->env.fpregs[regid - UC_X86_REG_FP0].d; cpu_get_fp80(value, (uint16_t*)((char*)value+sizeof(uint64_t)), reg); @@ -204,14 +204,14 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun *(uint16_t*) value = fptag; } continue; - case UC_X86_REG_XMM0: - case UC_X86_REG_XMM1: - case UC_X86_REG_XMM2: - case UC_X86_REG_XMM3: - case UC_X86_REG_XMM4: - case UC_X86_REG_XMM5: - case UC_X86_REG_XMM6: - case UC_X86_REG_XMM7: + case UC_X86_REG_XMM0: + case UC_X86_REG_XMM1: + case UC_X86_REG_XMM2: + case UC_X86_REG_XMM3: + case UC_X86_REG_XMM4: + case UC_X86_REG_XMM5: + case UC_X86_REG_XMM6: + case UC_X86_REG_XMM7: { float64 *dst = (float64*)value; XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0]; @@ -248,21 +248,21 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun switch(regid) { default: break; - case UC_X86_REG_CR0: - case UC_X86_REG_CR1: - case UC_X86_REG_CR2: - case UC_X86_REG_CR3: - case UC_X86_REG_CR4: + case UC_X86_REG_CR0: + case UC_X86_REG_CR1: + case UC_X86_REG_CR2: + case UC_X86_REG_CR3: + case UC_X86_REG_CR4: *(int32_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0]; break; - case UC_X86_REG_DR0: - case UC_X86_REG_DR1: - case UC_X86_REG_DR2: - case UC_X86_REG_DR3: - case UC_X86_REG_DR4: - case UC_X86_REG_DR5: - case UC_X86_REG_DR6: - case UC_X86_REG_DR7: + case UC_X86_REG_DR0: + case UC_X86_REG_DR1: + case UC_X86_REG_DR2: + case UC_X86_REG_DR3: + case UC_X86_REG_DR4: + case UC_X86_REG_DR5: + case UC_X86_REG_DR6: + case UC_X86_REG_DR7: *(int32_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0]; break; case UC_X86_REG_EFLAGS: @@ -392,21 +392,21 @@ int x86_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int coun switch(regid) { default: break; - case UC_X86_REG_CR0: - case UC_X86_REG_CR1: - case UC_X86_REG_CR2: - case UC_X86_REG_CR3: - case UC_X86_REG_CR4: + case UC_X86_REG_CR0: + case UC_X86_REG_CR1: + case UC_X86_REG_CR2: + case UC_X86_REG_CR3: + case UC_X86_REG_CR4: *(int64_t *)value = X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0]; break; - case UC_X86_REG_DR0: - case UC_X86_REG_DR1: - case UC_X86_REG_DR2: - case UC_X86_REG_DR3: - case UC_X86_REG_DR4: - case UC_X86_REG_DR5: - case UC_X86_REG_DR6: - case UC_X86_REG_DR7: + case UC_X86_REG_DR0: + case UC_X86_REG_DR1: + case UC_X86_REG_DR2: + case UC_X86_REG_DR3: + case UC_X86_REG_DR4: + case UC_X86_REG_DR5: + case UC_X86_REG_DR6: + case UC_X86_REG_DR7: *(int64_t *)value = X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0]; break; case UC_X86_REG_EFLAGS: @@ -683,14 +683,14 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i switch(regid) { default: break; - case UC_X86_REG_FP0: - case UC_X86_REG_FP1: - case UC_X86_REG_FP2: - case UC_X86_REG_FP3: - case UC_X86_REG_FP4: - case UC_X86_REG_FP5: - case UC_X86_REG_FP6: - case UC_X86_REG_FP7: + case UC_X86_REG_FP0: + case UC_X86_REG_FP1: + case UC_X86_REG_FP2: + case UC_X86_REG_FP3: + case UC_X86_REG_FP4: + case UC_X86_REG_FP5: + case UC_X86_REG_FP6: + case UC_X86_REG_FP7: { uint64_t mant = *(uint64_t*) value; uint16_t upper = *(uint16_t*) ((char*)value + sizeof(uint64_t)); @@ -719,14 +719,14 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i continue; } break; - case UC_X86_REG_XMM0: - case UC_X86_REG_XMM1: - case UC_X86_REG_XMM2: - case UC_X86_REG_XMM3: - case UC_X86_REG_XMM4: - case UC_X86_REG_XMM5: - case UC_X86_REG_XMM6: - case UC_X86_REG_XMM7: + case UC_X86_REG_XMM0: + case UC_X86_REG_XMM1: + case UC_X86_REG_XMM2: + case UC_X86_REG_XMM3: + case UC_X86_REG_XMM4: + case UC_X86_REG_XMM5: + case UC_X86_REG_XMM6: + case UC_X86_REG_XMM7: { float64 *src = (float64*)value; XMMReg *reg = &X86_CPU(uc, mycpu)->env.xmm_regs[regid - UC_X86_REG_XMM0]; @@ -764,21 +764,21 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i switch(regid) { default: break; - case UC_X86_REG_CR0: - case UC_X86_REG_CR1: - case UC_X86_REG_CR2: - case UC_X86_REG_CR3: - case UC_X86_REG_CR4: + case UC_X86_REG_CR0: + case UC_X86_REG_CR1: + case UC_X86_REG_CR2: + case UC_X86_REG_CR3: + case UC_X86_REG_CR4: X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint32_t *)value; break; - case UC_X86_REG_DR0: - case UC_X86_REG_DR1: - case UC_X86_REG_DR2: - case UC_X86_REG_DR3: - case UC_X86_REG_DR4: - case UC_X86_REG_DR5: - case UC_X86_REG_DR6: - case UC_X86_REG_DR7: + case UC_X86_REG_DR0: + case UC_X86_REG_DR1: + case UC_X86_REG_DR2: + case UC_X86_REG_DR3: + case UC_X86_REG_DR4: + case UC_X86_REG_DR5: + case UC_X86_REG_DR6: + case UC_X86_REG_DR7: X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint32_t *)value; break; case UC_X86_REG_EFLAGS: @@ -915,21 +915,21 @@ int x86_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, i switch(regid) { default: break; - case UC_X86_REG_CR0: - case UC_X86_REG_CR1: - case UC_X86_REG_CR2: - case UC_X86_REG_CR3: - case UC_X86_REG_CR4: + case UC_X86_REG_CR0: + case UC_X86_REG_CR1: + case UC_X86_REG_CR2: + case UC_X86_REG_CR3: + case UC_X86_REG_CR4: X86_CPU(uc, mycpu)->env.cr[regid - UC_X86_REG_CR0] = *(uint64_t *)value; break; - case UC_X86_REG_DR0: - case UC_X86_REG_DR1: - case UC_X86_REG_DR2: - case UC_X86_REG_DR3: - case UC_X86_REG_DR4: - case UC_X86_REG_DR5: - case UC_X86_REG_DR6: - case UC_X86_REG_DR7: + case UC_X86_REG_DR0: + case UC_X86_REG_DR1: + case UC_X86_REG_DR2: + case UC_X86_REG_DR3: + case UC_X86_REG_DR4: + case UC_X86_REG_DR5: + case UC_X86_REG_DR6: + case UC_X86_REG_DR7: X86_CPU(uc, mycpu)->env.dr[regid - UC_X86_REG_DR0] = *(uint64_t *)value; break; case UC_X86_REG_EFLAGS: diff --git a/qemu/target-mips/cpu.h b/qemu/target-mips/cpu.h index 9a26f366..1c192cef 100644 --- a/qemu/target-mips/cpu.h +++ b/qemu/target-mips/cpu.h @@ -763,7 +763,7 @@ int mips_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra); hwaddr cpu_mips_translate_address (CPUMIPSState *env, target_ulong address, - int rw); + int rw); #endif target_ulong exception_resume_pc (CPUMIPSState *env); diff --git a/qemu/tcg/i386/tcg-target.c b/qemu/tcg/i386/tcg-target.c index 741b957a..7ffad8e9 100644 --- a/qemu/tcg/i386/tcg-target.c +++ b/qemu/tcg/i386/tcg-target.c @@ -78,12 +78,12 @@ static const int tcg_target_call_iarg_regs[] = { TCG_REG_R9, #else /* 32 bit mode uses stack based calling convention (GCC default). - We add a dummy value here for MSVC compatibility for the error: - "error C2466: cannot allocate an array of constant size 0" - The "tcg_target_call_iarg_regs" array is not accessed when - TCG_TARGET_REG_BITS == 32 - */ - 0, + We add a dummy value here for MSVC compatibility for the error: + "error C2466: cannot allocate an array of constant size 0" + The "tcg_target_call_iarg_regs" array is not accessed when + TCG_TARGET_REG_BITS == 32 + */ + 0, #endif }; @@ -411,24 +411,24 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type, static const uint8_t tcg_cond_to_jcc[] = { #ifdef _MSC_VER - 0, // TCG_COND_NEVER - 0, // TCG_COND_ALWAYS - JCC_JL, // TCG_COND_LT - JCC_JGE, // TCG_COND_GE - JCC_JB, // TCG_COND_LTU - JCC_JAE, // TCG_COND_GEU - 0, // n/a - 0, // n/a - JCC_JE, // TCG_COND_EQ - JCC_JNE, // TCG_COND_NE - JCC_JLE, // TCG_COND_LE - JCC_JG, // TCG_COND_GT - JCC_JBE, // TCG_COND_LEU - JCC_JA, // TCG_COND_GTU - 0, // n/a - 0, // n/a + 0, // TCG_COND_NEVER + 0, // TCG_COND_ALWAYS + JCC_JL, // TCG_COND_LT + JCC_JGE, // TCG_COND_GE + JCC_JB, // TCG_COND_LTU + JCC_JAE, // TCG_COND_GEU + 0, // n/a + 0, // n/a + JCC_JE, // TCG_COND_EQ + JCC_JNE, // TCG_COND_NE + JCC_JLE, // TCG_COND_LE + JCC_JG, // TCG_COND_GT + JCC_JBE, // TCG_COND_LEU + JCC_JA, // TCG_COND_GTU + 0, // n/a + 0, // n/a #else - [TCG_COND_EQ] = JCC_JE, + [TCG_COND_EQ] = JCC_JE, [TCG_COND_NE] = JCC_JNE, [TCG_COND_LT] = JCC_JL, [TCG_COND_GE] = JCC_JGE, @@ -1155,43 +1155,43 @@ static void tcg_out_jmp(TCGContext *s, tcg_insn_unit *dest) */ static void * const qemu_ld_helpers[16] = { #ifdef _MSC_VER - helper_ret_ldub_mmu, // MO_UB + helper_ret_ldub_mmu, // MO_UB # ifdef HOST_WORDS_BIGENDIAN - helper_be_lduw_mmu, // MO_BEUW - helper_be_ldul_mmu, // MO_BEUL - helper_be_ldq_mmu, // MO_BEQ - 0, // MO_SB - 0, // MO_BESW - 0, // MO_BESL - 0, // n/a - 0, // n/a - helper_le_lduw_mmu, // MO_LEUW - helper_le_ldul_mmu, // MO_LEUL - helper_le_ldq_mmu, // MO_LEQ - 0, // n/a - 0, // MO_LESW - 0, // MO_LESL - 0, // n/a + helper_be_lduw_mmu, // MO_BEUW + helper_be_ldul_mmu, // MO_BEUL + helper_be_ldq_mmu, // MO_BEQ + 0, // MO_SB + 0, // MO_BESW + 0, // MO_BESL + 0, // n/a + 0, // n/a + helper_le_lduw_mmu, // MO_LEUW + helper_le_ldul_mmu, // MO_LEUL + helper_le_ldq_mmu, // MO_LEQ + 0, // n/a + 0, // MO_LESW + 0, // MO_LESL + 0, // n/a # else // !HOST_WORDS_BIGENDIAN - helper_le_lduw_mmu, // MO_LEUW - helper_le_ldul_mmu, // MO_LEUL - helper_le_ldq_mmu, // MO_LEQ - 0, // MO_SB - 0, // MO_LESW - 0, // MO_LESL - 0, // n/a - 0, // n/a - helper_be_lduw_mmu, // MO_BEUW - helper_be_ldul_mmu, // MO_BEUL - helper_be_ldq_mmu, // MO_BEQ - 0, // n/a - 0, // MO_BESW - 0, // MO_BESL - 0, // n/a + helper_le_lduw_mmu, // MO_LEUW + helper_le_ldul_mmu, // MO_LEUL + helper_le_ldq_mmu, // MO_LEQ + 0, // MO_SB + 0, // MO_LESW + 0, // MO_LESL + 0, // n/a + 0, // n/a + helper_be_lduw_mmu, // MO_BEUW + helper_be_ldul_mmu, // MO_BEUL + helper_be_ldq_mmu, // MO_BEQ + 0, // n/a + 0, // MO_BESW + 0, // MO_BESL + 0, // n/a # endif // HOST_WORDS_BIGENDIAN #else //_MSC_VER - [MO_UB] = helper_ret_ldub_mmu, + [MO_UB] = helper_ret_ldub_mmu, [MO_LEUW] = helper_le_lduw_mmu, [MO_LEUL] = helper_le_ldul_mmu, [MO_LEQ] = helper_le_ldq_mmu, @@ -1206,39 +1206,39 @@ static void * const qemu_ld_helpers[16] = { */ static void * const qemu_st_helpers[16] = { #ifdef _MSC_VER - helper_ret_stb_mmu, // MO_UB + helper_ret_stb_mmu, // MO_UB # ifdef HOST_WORDS_BIGENDIAN - helper_be_stw_mmu, // MO_BEUW - helper_be_stl_mmu, // MO_BEUL - helper_be_stq_mmu, // MO_BEQ - 0, // MO_SB - 0, // MO_BESW - 0, // MO_BESL - 0, // n/a - 0, // n/a - helper_le_stw_mmu, // MO_LEUW - helper_le_stl_mmu, // MO_LEUL - helper_le_stq_mmu, // MO_LEQ - 0, // n/a - 0, // MO_LESW - 0, // MO_LESL - 0, // n/a + helper_be_stw_mmu, // MO_BEUW + helper_be_stl_mmu, // MO_BEUL + helper_be_stq_mmu, // MO_BEQ + 0, // MO_SB + 0, // MO_BESW + 0, // MO_BESL + 0, // n/a + 0, // n/a + helper_le_stw_mmu, // MO_LEUW + helper_le_stl_mmu, // MO_LEUL + helper_le_stq_mmu, // MO_LEQ + 0, // n/a + 0, // MO_LESW + 0, // MO_LESL + 0, // n/a # else // !HOST_WORDS_BIGENDIAN - helper_le_stw_mmu, // MO_LEUW - helper_le_stl_mmu, // MO_LEUL - helper_le_stq_mmu, // MO_LEQ - 0, // MO_SB - 0, // MO_LESW - 0, // MO_LESL - 0, // n/a - 0, // n/a - helper_be_stw_mmu, // MO_BEUW - helper_be_stl_mmu, // MO_BEUL - helper_be_stq_mmu, // MO_BEQ - 0, // n/a - 0, // MO_BESW - 0, // MO_BESL - 0, // n/a + helper_le_stw_mmu, // MO_LEUW + helper_le_stl_mmu, // MO_LEUL + helper_le_stq_mmu, // MO_LEQ + 0, // MO_SB + 0, // MO_LESW + 0, // MO_LESL + 0, // n/a + 0, // n/a + helper_be_stw_mmu, // MO_BEUW + helper_be_stl_mmu, // MO_BEUL + helper_be_stq_mmu, // MO_BEQ + 0, // n/a + 0, // MO_BESW + 0, // MO_BESL + 0, // n/a # endif // HOST_WORDS_BIGENDIAN #else //_MSC_VER @@ -2356,8 +2356,8 @@ static void tcg_target_qemu_prologue(TCGContext *s) tcg_out_addi(s, TCG_REG_ESP, -stack_addend); /* jmp *tb. */ tcg_out_modrm_offset(s, OPC_GRP5, EXT5_JMPN_Ev, TCG_REG_ESP, - (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 - + stack_addend); + (ARRAY_SIZE(tcg_target_callee_save_regs) + 2) * 4 + + stack_addend); #else tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); tcg_out_addi(s, TCG_REG_ESP, -stack_addend); @@ -2387,12 +2387,12 @@ static void tcg_target_init(TCGContext *s) { #ifdef CONFIG_CPUID_H unsigned a, b, c, d; - int max; + int max; #ifdef _MSC_VER int cpu_info[4]; __cpuid(cpu_info, 0); - max = cpu_info[0]; + max = cpu_info[0]; #else max = __get_cpuid_max(0, 0); #endif diff --git a/qemu/tcg/sparc/tcg-target.c b/qemu/tcg/sparc/tcg-target.c index a768be89..3fcdcad4 100644 --- a/qemu/tcg/sparc/tcg-target.c +++ b/qemu/tcg/sparc/tcg-target.c @@ -405,7 +405,7 @@ static inline void tcg_out_arithi(TCGContext *s, TCGReg rd, TCGReg rs1, } static void tcg_out_arithc(TCGContext *s, TCGReg rd, TCGReg rs1, - int32_t val2, int val2const, int op) + int32_t val2, int val2const, int op) { tcg_out32(s, op | INSN_RD(rd) | INSN_RS1(rs1) | (val2const ? INSN_IMM13(val2) : INSN_RS2(val2))); @@ -682,7 +682,7 @@ static void tcg_out_setcond_i32(TCGContext *s, TCGCond cond, TCGReg ret, } c1 = TCG_REG_G0, c2const = 0; cond = (cond == TCG_COND_EQ ? TCG_COND_GEU : TCG_COND_LTU); - break; + break; case TCG_COND_GTU: case TCG_COND_LEU: @@ -783,16 +783,16 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, } tcg_out_arith(s, rh, ah, bh, ARITH_ADDXC); } else if (bh == TCG_REG_G0) { - /* If we have a zero, we can perform the operation in two insns, + /* If we have a zero, we can perform the operation in two insns, with the arithmetic first, and a conditional move into place. */ - if (rh == ah) { + if (rh == ah) { tcg_out_arithi(s, TCG_REG_T2, ah, 1, - is_sub ? ARITH_SUB : ARITH_ADD); + is_sub ? ARITH_SUB : ARITH_ADD); tcg_out_movcc(s, TCG_COND_LTU, MOVCC_XCC, rh, TCG_REG_T2, 0); - } else { + } else { tcg_out_arithi(s, rh, ah, 1, is_sub ? ARITH_SUB : ARITH_ADD); - tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); - } + tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, rh, ah, 0); + } } else { /* Otherwise adjust BH as if there is carry into T2 ... */ if (bhconst) { @@ -803,7 +803,7 @@ static void tcg_out_addsub2_i64(TCGContext *s, TCGReg rl, TCGReg rh, } /* ... smoosh T2 back to original BH if carry is clear ... */ tcg_out_movcc(s, TCG_COND_GEU, MOVCC_XCC, TCG_REG_T2, bh, bhconst); - /* ... and finally perform the arithmetic with the new operand. */ + /* ... and finally perform the arithmetic with the new operand. */ tcg_out_arith(s, rh, ah, TCG_REG_T2, is_sub ? ARITH_SUB : ARITH_ADD); } @@ -1315,11 +1315,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, goto gen_arith; OP_32_64(neg): - c = ARITH_SUB; - goto gen_arith1; + c = ARITH_SUB; + goto gen_arith1; OP_32_64(not): - c = ARITH_ORN; - goto gen_arith1; + c = ARITH_ORN; + goto gen_arith1; case INDEX_op_div_i32: tcg_out_div32(s, a0, a1, a2, c2, 0); @@ -1445,8 +1445,8 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, break; gen_arith1: - tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); - break; + tcg_out_arithc(s, a0, TCG_REG_G0, a1, const_args[1], c); + break; case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ case INDEX_op_mov_i64: diff --git a/qemu/tcg/sparc/tcg-target.h b/qemu/tcg/sparc/tcg-target.h index f24dad04..b1b2265c 100644 --- a/qemu/tcg/sparc/tcg-target.h +++ b/qemu/tcg/sparc/tcg-target.h @@ -152,12 +152,12 @@ extern bool use_vis3_instructions; #include static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { - FlushInstructionCache(GetCurrentProcess(), (const void*)start, stop-start); + FlushInstructionCache(GetCurrentProcess(), (const void*)start, stop-start); } #else static inline void flush_icache_range(uintptr_t start, uintptr_t stop) { - uintptr_t p; + uintptr_t p; for (p = start & -8; p < ((stop + 7) & -8); p += 8) { __asm__ __volatile__("flush\t%0" : : "r" (p)); } diff --git a/qemu/tcg/tcg.c b/qemu/tcg/tcg.c index a1549993..56e1da4b 100644 --- a/qemu/tcg/tcg.c +++ b/qemu/tcg/tcg.c @@ -70,7 +70,7 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type, /* The CIE and FDE header definitions will be common to all hosts. */ typedef struct { //uint32_t QEMU_ALIGN(sizeof(void *), len); - uint32_t QEMU_ALIGN(8, len); + uint32_t QEMU_ALIGN(8, len); uint32_t id; uint8_t version; char augmentation[1]; @@ -81,7 +81,7 @@ typedef struct { QEMU_PACK( typedef struct { // uint32_t QEMU_ALIGN(sizeof(void *), len); - uint32_t QEMU_ALIGN(8, len); + uint32_t QEMU_ALIGN(8, len); uint32_t cie_offset; uintptr_t func_start; uintptr_t func_len; @@ -1100,22 +1100,22 @@ static inline const char *tcg_find_helper(TCGContext *s, uintptr_t val) static const char * const cond_name[] = { #ifdef _MSC_VER - "never", // TCG_COND_NEVER - "always", // TCG_COND_ALWAYS - "lt", // TCG_COND_LT - "ge", // TCG_COND_GE - "ltu", // TCG_COND_LTU - "geu", // TCG_COND_GEU - NULL, // n/a - NULL, // n/a - "eq", // TCG_COND_EQ - "ne", // TCG_COND_NE - "le", // TCG_COND_LE - "gt", // TCG_COND_GT - "leu", // TCG_COND_LEU - "gtu", // TCG_COND_GTU - NULL, // n/a - NULL, // n/a + "never", // TCG_COND_NEVER + "always", // TCG_COND_ALWAYS + "lt", // TCG_COND_LT + "ge", // TCG_COND_GE + "ltu", // TCG_COND_LTU + "geu", // TCG_COND_GEU + NULL, // n/a + NULL, // n/a + "eq", // TCG_COND_EQ + "ne", // TCG_COND_NE + "le", // TCG_COND_LE + "gt", // TCG_COND_GT + "leu", // TCG_COND_LEU + "gtu", // TCG_COND_GTU + NULL, // n/a + NULL, // n/a #else [TCG_COND_NEVER] = "never", [TCG_COND_ALWAYS] = "always", @@ -1135,43 +1135,43 @@ static const char * const cond_name[] = static const char * const ldst_name[] = { #ifdef _MSC_VER - "ub", // MO_UB + "ub", // MO_UB # ifdef HOST_WORDS_BIGENDIAN - "beuw", // MO_BEUW - "beul", // MO_BEUL - "beq", // MO_BEQ - "sb", // MO_SB - "besw", // MO_BESW - "besl", // MO_BESL - NULL, // n/a - NULL, // n/a - "leuw", // MO_LEUW - "leul", // MO_LEUL - "leq", // MO_LEQ - NULL, // n/a - "lesw", // MO_LESW - "lesl", // MO_LESL - NULL, // n/a + "beuw", // MO_BEUW + "beul", // MO_BEUL + "beq", // MO_BEQ + "sb", // MO_SB + "besw", // MO_BESW + "besl", // MO_BESL + NULL, // n/a + NULL, // n/a + "leuw", // MO_LEUW + "leul", // MO_LEUL + "leq", // MO_LEQ + NULL, // n/a + "lesw", // MO_LESW + "lesl", // MO_LESL + NULL, // n/a # else // !HOST_WORDS_BIGENDIAN - "leuw", // MO_LEUW - "leul", // MO_LEUL - "leq", // MO_LEQ - "sb", // MO_SB - "lesw", // MO_LESW - "lesl", // MO_LESL - NULL, // n/a - NULL, // n/a - "beuw", // MO_BEUW - "beul", // MO_BEUL - "beq", // MO_BEQ - NULL, // n/a - "besw", // MO_BESW - "besl", // MO_BESL - NULL, // n/a + "leuw", // MO_LEUW + "leul", // MO_LEUL + "leq", // MO_LEQ + "sb", // MO_SB + "lesw", // MO_LESW + "lesl", // MO_LESL + NULL, // n/a + NULL, // n/a + "beuw", // MO_BEUW + "beul", // MO_BEUL + "beq", // MO_BEQ + NULL, // n/a + "besw", // MO_BESW + "besl", // MO_BESL + NULL, // n/a # endif // HOST_WORDS_BIGENDIAN #else //_MSC_VER - [MO_UB] = "ub", + [MO_UB] = "ub", [MO_SB] = "sb", [MO_LEUW] = "leuw", [MO_LESW] = "lesw", @@ -2376,10 +2376,10 @@ static int tcg_reg_alloc_call(TCGContext *s, const TCGOpDef *def, nb_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); #if TCG_TARGET_REG_BITS == 32 - // do this because msvc cannot have arrays with 0 entries. - nb_regs = 0; + // do this because msvc cannot have arrays with 0 entries. + nb_regs = 0; #endif - if (nb_regs > nb_params) { + if (nb_regs > nb_params) { nb_regs = nb_params; } diff --git a/qemu/util/bitops.c b/qemu/util/bitops.c index 626855d4..f1641bf8 100644 --- a/qemu/util/bitops.c +++ b/qemu/util/bitops.c @@ -19,7 +19,7 @@ * Find the next set bit in a memory region. */ unsigned long find_next_bit(const unsigned long *addr, unsigned long size, - unsigned long offset) + unsigned long offset) { const unsigned long *p = addr + BITOP_WORD(offset); unsigned long result = offset & ~(BITS_PER_LONG-1); @@ -84,7 +84,7 @@ found_middle: * Linus' asm-alpha/bitops.h. */ unsigned long find_next_zero_bit(const unsigned long *addr, unsigned long size, - unsigned long offset) + unsigned long offset) { const unsigned long *p = addr + BITOP_WORD(offset); unsigned long result = offset & ~(BITS_PER_LONG-1); diff --git a/samples/mem_apis.c b/samples/mem_apis.c index c9028a97..d79378c8 100644 --- a/samples/mem_apis.c +++ b/samples/mem_apis.c @@ -359,7 +359,7 @@ static void unmap_test() int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); @@ -370,7 +370,7 @@ int main(int argc, char **argv, char **envp) } #endif - nx_test(); + nx_test(); perms_test(); unmap_test(); @@ -379,5 +379,5 @@ int main(int argc, char **argv, char **envp) uc_dyn_free(); #endif - return 0; + return 0; } diff --git a/samples/sample_arm.c b/samples/sample_arm.c index 2e4dca3d..b516f847 100644 --- a/samples/sample_arm.c +++ b/samples/sample_arm.c @@ -152,7 +152,7 @@ static void test_thumb(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); @@ -163,7 +163,7 @@ int main(int argc, char **argv, char **envp) } #endif - test_arm(); + test_arm(); printf("==========================\n"); test_thumb(); diff --git a/samples/sample_arm64.c b/samples/sample_arm64.c index 5714d9ea..1ce39124 100644 --- a/samples/sample_arm64.c +++ b/samples/sample_arm64.c @@ -98,7 +98,7 @@ static void test_arm64(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); @@ -109,7 +109,7 @@ int main(int argc, char **argv, char **envp) } #endif - test_arm64(); + test_arm64(); // dynamically free shared library #ifdef DYNLOAD diff --git a/samples/sample_m68k.c b/samples/sample_m68k.c index 9b726d84..272ef3e2 100644 --- a/samples/sample_m68k.c +++ b/samples/sample_m68k.c @@ -160,7 +160,7 @@ static void test_m68k(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); @@ -171,7 +171,7 @@ int main(int argc, char **argv, char **envp) } #endif - test_m68k(); + test_m68k(); // dynamically free shared library #ifdef DYNLOAD diff --git a/samples/sample_mips.c b/samples/sample_mips.c index f093f625..efe4012b 100644 --- a/samples/sample_mips.c +++ b/samples/sample_mips.c @@ -145,7 +145,7 @@ static void test_mips_el(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); @@ -156,7 +156,7 @@ int main(int argc, char **argv, char **envp) } #endif - test_mips_eb(); + test_mips_eb(); test_mips_el(); // dynamically free shared library diff --git a/samples/sample_sparc.c b/samples/sample_sparc.c index 9b0bfc21..09770916 100644 --- a/samples/sample_sparc.c +++ b/samples/sample_sparc.c @@ -100,7 +100,7 @@ static void test_sparc(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); @@ -111,7 +111,7 @@ int main(int argc, char **argv, char **envp) } #endif - test_sparc(); + test_sparc(); // dynamically free shared library #ifdef DYNLOAD diff --git a/samples/sample_x86.c b/samples/sample_x86.c index 5e9b5c06..27513d21 100644 --- a/samples/sample_x86.c +++ b/samples/sample_x86.c @@ -972,7 +972,7 @@ int main(int argc, char **argv, char **envp) test_x86_16(); } else if (!strcmp(argv[1], "-32")) { - test_i386(); + test_i386(); test_i386_map_ptr(); test_i386_inout(); test_i386_context_save(); diff --git a/samples/shellcode.c b/samples/shellcode.c index 9de4f977..4e95c774 100644 --- a/samples/shellcode.c +++ b/samples/shellcode.c @@ -157,7 +157,7 @@ static void test_i386(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); diff --git a/tests/regress/memleak_arm.c b/tests/regress/memleak_arm.c index 88b73f80..d0e744e5 100644 --- a/tests/regress/memleak_arm.c +++ b/tests/regress/memleak_arm.c @@ -151,7 +151,7 @@ static void test_thumb(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); diff --git a/tests/regress/memleak_arm64.c b/tests/regress/memleak_arm64.c index df56c44f..4ddb9f69 100644 --- a/tests/regress/memleak_arm64.c +++ b/tests/regress/memleak_arm64.c @@ -98,7 +98,7 @@ static void test_arm64(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); diff --git a/tests/regress/memleak_m68k.c b/tests/regress/memleak_m68k.c index ed22e3a6..084045e1 100644 --- a/tests/regress/memleak_m68k.c +++ b/tests/regress/memleak_m68k.c @@ -160,7 +160,7 @@ static void test_m68k(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); diff --git a/tests/regress/memleak_mips.c b/tests/regress/memleak_mips.c index 0b47955d..ccf01eb7 100644 --- a/tests/regress/memleak_mips.c +++ b/tests/regress/memleak_mips.c @@ -145,7 +145,7 @@ static void test_mips_el(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); diff --git a/tests/regress/memleak_sparc.c b/tests/regress/memleak_sparc.c index 8f3628b7..2a4e4f67 100644 --- a/tests/regress/memleak_sparc.c +++ b/tests/regress/memleak_sparc.c @@ -100,7 +100,7 @@ static void test_sparc(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); diff --git a/tests/regress/memleak_x86.c b/tests/regress/memleak_x86.c index 8328fa96..2572ddd4 100644 --- a/tests/regress/memleak_x86.c +++ b/tests/regress/memleak_x86.c @@ -281,7 +281,7 @@ static void test_x86_64(void) int main(int argc, char **argv, char **envp) { - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD if (!uc_dyn_load(NULL, 0)) { printf("Error dynamically loading shared library.\n"); diff --git a/tests/regress/mips_delay_slot_code_hook.c b/tests/regress/mips_delay_slot_code_hook.c index 9c992607..8eafd96f 100644 --- a/tests/regress/mips_delay_slot_code_hook.c +++ b/tests/regress/mips_delay_slot_code_hook.c @@ -40,11 +40,11 @@ but that the code hook is just not occurring. // It should loop 3 times before ending. const uint64_t addr = 0x100000; const unsigned char loop_test_code[] = { - 0x02,0x00,0x04,0x24, // 100000: li $a0, 2 - // loop1 - 0x00,0x00,0x00,0x00, // 100004: nop - 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 - 0xFF,0xFF,0x84,0x24, // 10000C: addiu $a0, -1 + 0x02,0x00,0x04,0x24, // 100000: li $a0, 2 + // loop1 + 0x00,0x00,0x00,0x00, // 100004: nop + 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 + 0xFF,0xFF,0x84,0x24, // 10000C: addiu $a0, -1 }; bool test_passed_ok = false; int loop_count = 0; @@ -52,14 +52,14 @@ int loop_count = 0; static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) { - if( address == 0x10000C ) - test_passed_ok = true; - if( address == 0x100004 ) - { - printf("\nloop %d:\n", loop_count); - loop_count++; - } - printf("Code: %"PRIx64"\n", address); + if( address == 0x10000C ) + test_passed_ok = true; + if( address == 0x100004 ) + { + printf("\nloop %d:\n", loop_count); + loop_count++; + } + printf("Code: %"PRIx64"\n", address); } @@ -67,74 +67,74 @@ int main(int argc, char **argv, char **envp) { uc_engine *uc; uc_err err; - uc_hook hhc; - uint32_t val; + uc_hook hhc; + uint32_t val; - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD - uc_dyn_load(NULL, 0); + uc_dyn_load(NULL, 0); #endif - // Initialize emulator in MIPS 32bit little endian mode + // Initialize emulator in MIPS 32bit little endian mode err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc); if (err) - { + { printf("Failed on uc_open() with error returned: %u\n", err); return err; } - // map in a page of mem - err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); + // map in a page of mem + err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); if (err) - { + { printf("Failed on uc_mem_map() with error returned: %u\n", err); return err; } - // write machine code to be emulated to memory + // write machine code to be emulated to memory err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code)); - if( err ) - { + if( err ) + { printf("Failed on uc_mem_write() with error returned: %u\n", err); return err; } - + // hook all instructions by having @begin > @end uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, 1, 0); - if( err ) - { + if( err ) + { printf("Failed on uc_hook_add(code) with error returned: %u\n", err); return err; } - + // execute code - printf("---- Executing Code ----\n"); - err = uc_emu_start(uc, addr, addr + sizeof(loop_test_code), 0, 0); + printf("---- Executing Code ----\n"); + err = uc_emu_start(uc, addr, addr + sizeof(loop_test_code), 0, 0); if (err) - { + { printf("Failed on uc_emu_start() with error returned %u: %s\n", err, uc_strerror(err)); - return err; + return err; } - // done executing, print some reg values as a test - printf("---- Execution Complete ----\n\n"); - uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); - uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); - - // free resources - uc_close(uc); - - if( test_passed_ok ) - printf("\n\nTEST PASSED!\n\n"); - else - printf("\n\nTEST FAILED!\n\n"); + // done executing, print some reg values as a test + printf("---- Execution Complete ----\n\n"); + uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); + uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); + + // free resources + uc_close(uc); + + if( test_passed_ok ) + printf("\n\nTEST PASSED!\n\n"); + else + printf("\n\nTEST FAILED!\n\n"); - // dynamically free shared library + // dynamically free shared library #ifdef DYNLOAD uc_dyn_free(); #endif - return 0; + return 0; } diff --git a/tests/regress/threaded_emu_start.c b/tests/regress/threaded_emu_start.c index 504763fd..fd3152c0 100644 --- a/tests/regress/threaded_emu_start.c +++ b/tests/regress/threaded_emu_start.c @@ -52,11 +52,11 @@ background. // This should loop forever. const uint64_t addr = 0x100000; const unsigned char loop_test_code[] = { - 0x02,0x00,0x04,0x24, // 100000: li $a0, 2 - // loop1 - 0x00,0x00,0x00,0x00, // 100004: nop - 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 - 0x00,0x00,0x00,0x00, // 10000C: nop + 0x02,0x00,0x04,0x24, // 100000: li $a0, 2 + // loop1 + 0x00,0x00,0x00,0x00, // 100004: nop + 0xFE,0xFF,0x80,0x14, // 100008: bnez $a0, loop1 + 0x00,0x00,0x00,0x00, // 10000C: nop }; bool test_passed_ok = false; int loop_count = 0; @@ -65,14 +65,14 @@ int loop_count = 0; // This hook is used to show that code is executing in the emulator. static void mips_codehook(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) { - printf("Code: %"PRIx64"\n", address); + printf("Code: %"PRIx64"\n", address); } typedef struct { - uc_engine *uc; - uint64_t startAddr; - uint64_t endAddr; + uc_engine *uc; + uint64_t startAddr; + uint64_t endAddr; } EmuStarterParam_t; // This is a thread that just runs uc_emu_start() in it. @@ -80,38 +80,38 @@ typedef struct { static uc_err emu_starter(void* param) { uc_engine *uc; - uint64_t start_addr; - uint64_t end_addr; - uc_err err; - - EmuStarterParam_t* starter_params = (EmuStarterParam_t *)param; - uc = starter_params->uc; - start_addr = starter_params->startAddr; - end_addr = starter_params->endAddr; - - printf("uc_emu_start()\n"); - err = uc_emu_start(uc, start_addr, end_addr, 0, 0); + uint64_t start_addr; + uint64_t end_addr; + uc_err err; + + EmuStarterParam_t* starter_params = (EmuStarterParam_t *)param; + uc = starter_params->uc; + start_addr = starter_params->startAddr; + end_addr = starter_params->endAddr; + + printf("uc_emu_start()\n"); + err = uc_emu_start(uc, start_addr, end_addr, 0, 0); if (err) - { + { printf("Failed on uc_emu_start() with error returned %u: %s\n", err, uc_strerror(err)); } - return err; + return err; } #ifdef _WIN32 static unsigned int __stdcall win32_emu_starter(void* param) { - uc_err err = emu_starter(param); - _endthreadex(err); - return err; + uc_err err = emu_starter(param); + _endthreadex(err); + return err; } #else static void* posix_emu_starter(void* param) { - uc_err err = emu_starter(param); - return (void*)err; + uc_err err = emu_starter(param); + return (void*)err; } #endif @@ -120,124 +120,124 @@ int main(int argc, char **argv, char **envp) { uc_engine *uc; uc_err err; - int ret; - uc_hook hhc; - uint32_t val; - EmuStarterParam_t starter_params; + int ret; + uc_hook hhc; + uint32_t val; + EmuStarterParam_t starter_params; #ifdef _WIN32 - HANDLE th = (HANDLE)-1; + HANDLE th = (HANDLE)-1; #else - pthread_t th; + pthread_t th; #endif - // dynamically load shared library + // dynamically load shared library #ifdef DYNLOAD - uc_dyn_load(NULL, 0); + uc_dyn_load(NULL, 0); #endif - // Initialize emulator in MIPS 32bit little endian mode + // Initialize emulator in MIPS 32bit little endian mode printf("uc_open()\n"); - err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc); + err = uc_open(UC_ARCH_MIPS, UC_MODE_MIPS32, &uc); if (err) - { + { printf("Failed on uc_open() with error returned: %u\n", err); return err; } - // map in a page of mem - printf("uc_mem_map()\n"); - err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); + // map in a page of mem + printf("uc_mem_map()\n"); + err = uc_mem_map(uc, addr, 0x1000, UC_PROT_ALL); if (err) - { + { printf("Failed on uc_mem_map() with error returned: %u\n", err); return err; } - // write machine code to be emulated to memory - printf("uc_mem_write()\n"); + // write machine code to be emulated to memory + printf("uc_mem_write()\n"); err = uc_mem_write(uc, addr, loop_test_code, sizeof(loop_test_code)); - if( err ) - { + if( err ) + { printf("Failed on uc_mem_write() with error returned: %u\n", err); return err; } - + // hook all instructions by having @begin > @end - printf("uc_hook_add()\n"); + printf("uc_hook_add()\n"); uc_hook_add(uc, &hhc, UC_HOOK_CODE, mips_codehook, NULL, 1, 0); - if( err ) - { + if( err ) + { printf("Failed on uc_hook_add(code) with error returned: %u\n", err); return err; } - - - // start background thread - printf("---- Thread Starting ----\n"); - starter_params.uc = uc; - starter_params.startAddr = addr; - starter_params.endAddr = addr + sizeof(loop_test_code); + + + // start background thread + printf("---- Thread Starting ----\n"); + starter_params.uc = uc; + starter_params.startAddr = addr; + starter_params.endAddr = addr + sizeof(loop_test_code); #ifdef _WIN32 - // create thread - th = (HANDLE)_beginthreadex(NULL, 0, win32_emu_starter, &starter_params, CREATE_SUSPENDED, NULL); - if(th == (HANDLE)-1) - { - printf("Failed on _beginthreadex() with error returned: %u\n", _errno()); - return -1; - } - // start thread - ret = ResumeThread(th); - if( ret == -1 ) - { - printf("Failed on ResumeThread() with error returned: %u\n", _errno()); - return -2; - } - // wait 3 seconds - Sleep(3 * 1000); + // create thread + th = (HANDLE)_beginthreadex(NULL, 0, win32_emu_starter, &starter_params, CREATE_SUSPENDED, NULL); + if(th == (HANDLE)-1) + { + printf("Failed on _beginthreadex() with error returned: %u\n", _errno()); + return -1; + } + // start thread + ret = ResumeThread(th); + if( ret == -1 ) + { + printf("Failed on ResumeThread() with error returned: %u\n", _errno()); + return -2; + } + // wait 3 seconds + Sleep(3 * 1000); #else - // add posix code to start the emu_starter() thread - ret = pthread_create(&th, NULL, posix_emu_starter, &starter_params); - if( ret ) - { - printf("Failed on pthread_create() with error returned: %u\n", err); - return -2; - } - // wait 3 seconds - sleep(3); + // add posix code to start the emu_starter() thread + ret = pthread_create(&th, NULL, posix_emu_starter, &starter_params); + if( ret ) + { + printf("Failed on pthread_create() with error returned: %u\n", err); + return -2; + } + // wait 3 seconds + sleep(3); #endif - // Stop the thread after it has been let to run in the background for a while - printf("---- Thread Stopping ----\n"); - printf("uc_emu_stop()\n"); - err = uc_emu_stop(uc); - if( err ) - { + // Stop the thread after it has been let to run in the background for a while + printf("---- Thread Stopping ----\n"); + printf("uc_emu_stop()\n"); + err = uc_emu_stop(uc); + if( err ) + { printf("Failed on uc_emu_stop() with error returned: %u\n", err); return err; } - test_passed_ok = true; - + test_passed_ok = true; + - // done executing, print some reg values as a test - uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); - uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); - - // free resources - printf("uc_close()\n"); - uc_close(uc); - - if( test_passed_ok ) - printf("\n\nTEST PASSED!\n\n"); - else - printf("\n\nTEST FAILED!\n\n"); + // done executing, print some reg values as a test + uc_reg_read(uc, UC_MIPS_REG_PC, &val); printf("pc is %X\n", val); + uc_reg_read(uc, UC_MIPS_REG_A0, &val); printf("a0 is %X\n", val); + + // free resources + printf("uc_close()\n"); + uc_close(uc); + + if( test_passed_ok ) + printf("\n\nTEST PASSED!\n\n"); + else + printf("\n\nTEST FAILED!\n\n"); - // dynamically free shared library + // dynamically free shared library #ifdef DYNLOAD uc_dyn_free(); #endif - return 0; + return 0; } diff --git a/tests/unit/test_hang.c b/tests/unit/test_hang.c index 8589573d..02171b4e 100644 --- a/tests/unit/test_hang.c +++ b/tests/unit/test_hang.c @@ -1,6 +1,6 @@ /* - refer to issue #575. - to run correctly unicorn needs to be compiled for AArch64. + refer to issue #575. + to run correctly unicorn needs to be compiled for AArch64. */ #include "unicorn_test.h" @@ -9,94 +9,94 @@ uint64_t trunc_page(uint64_t addr) { - return (addr & ~(4095)); + return (addr & ~(4095)); } /* Called before every test to set up a new instance */ static int init(void **state) { - printf("[+] Initializing Unicorn...\n"); - uc_engine *uc; + printf("[+] Initializing Unicorn...\n"); + uc_engine *uc; - if (uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc) != UC_ERR_OK) { - printf("Error on open. Be sure that your unicorn library supports AArch64.\n"); - return -1; - } + if (uc_open(UC_ARCH_ARM64, UC_MODE_ARM, &uc) != UC_ERR_OK) { + printf("Error on open. Be sure that your unicorn library supports AArch64.\n"); + return -1; + } - *state = uc; + *state = uc; - return 0; + return 0; } /* Called after every test to clean up */ static int teardown(void **state) { - printf("[+] Exiting...\n"); - uc_engine *uc = *state; + printf("[+] Exiting...\n"); + uc_engine *uc = *state; - uc_close(uc); + uc_close(uc); - *state = NULL; - return 0; + *state = NULL; + return 0; } void test_hang(void **state) { - uint32_t code[] = { - 0xd503201f, /* NOP */ - 0xd503201f, /* NOP */ - 0xd503201f, /* NOP */ - 0xaa0103e0 /* MOV X0, X1 */ - }; + uint32_t code[] = { + 0xd503201f, /* NOP */ + 0xd503201f, /* NOP */ + 0xd503201f, /* NOP */ + 0xaa0103e0 /* MOV X0, X1 */ + }; - uc_engine *uc = *state; + uc_engine *uc = *state; - uint64_t x0 = 0; - uint64_t x1 = 1; + uint64_t x0 = 0; + uint64_t x1 = 1; - /* - * emulation will hang if some instruction hits every quarter of a page, - * i.e. these offsets: - * 0x1400, 0x1800, 0x1c00, 0x2000 - * - * in this test, the code to be emulated is mapped just before the 0x1400 - * offset, so that the final instruction emulated (MOV X0, X1) hits the offset, - * causing the hang. - * If you try to write the code just four bytes behind, the hang doesn't occur. - * - * So far, this strange behaviour has only been observed with AArch64 Unicorn APIs. - */ + /* + * emulation will hang if some instruction hits every quarter of a page, + * i.e. these offsets: + * 0x1400, 0x1800, 0x1c00, 0x2000 + * + * in this test, the code to be emulated is mapped just before the 0x1400 + * offset, so that the final instruction emulated (MOV X0, X1) hits the offset, + * causing the hang. + * If you try to write the code just four bytes behind, the hang doesn't occur. + * + * So far, this strange behaviour has only been observed with AArch64 Unicorn APIs. + */ - uint64_t addr = 0x13f0; // try to map at (0x13f0 - 0x4) and the hang doesn't occur - uint64_t trunc_addr = trunc_page(addr); // round down to nearest page + uint64_t addr = 0x13f0; // try to map at (0x13f0 - 0x4) and the hang doesn't occur + uint64_t trunc_addr = trunc_page(addr); // round down to nearest page - uc_mem_map(uc, trunc_addr, 2 * 1024 * 1024, UC_PROT_ALL); + uc_mem_map(uc, trunc_addr, 2 * 1024 * 1024, UC_PROT_ALL); - if (uc_mem_write(uc, addr, &code, sizeof(code))) { - printf("error on write\n"); - return; - } + if (uc_mem_write(uc, addr, &code, sizeof(code))) { + printf("error on write\n"); + return; + } - uc_reg_write(uc, UC_ARM64_REG_X0, &x0); - uc_reg_write(uc, UC_ARM64_REG_X1, &x1); + uc_reg_write(uc, UC_ARM64_REG_X0, &x0); + uc_reg_write(uc, UC_ARM64_REG_X1, &x1); - if (uc_emu_start(uc, addr, addr + sizeof(code), 0, 0)) { - printf("error on start\n"); - return; - } + if (uc_emu_start(uc, addr, addr + sizeof(code), 0, 0)) { + printf("error on start\n"); + return; + } - uc_reg_read(uc, UC_ARM64_REG_X0, &x0); - uc_reg_read(uc, UC_ARM64_REG_X1, &x1); + uc_reg_read(uc, UC_ARM64_REG_X0, &x0); + uc_reg_read(uc, UC_ARM64_REG_X1, &x1); - printf("x0: %"PRIx64"\n", x0); - printf("x1: %"PRIx64"\n", x1); + printf("x0: %"PRIx64"\n", x0); + printf("x1: %"PRIx64"\n", x1); } int main(int argc, const char * argv[]) { - const struct CMUnitTest tests[] = { - cmocka_unit_test_setup_teardown(test_hang, init, teardown), - }; + const struct CMUnitTest tests[] = { + cmocka_unit_test_setup_teardown(test_hang, init, teardown), + }; - return cmocka_run_group_tests(tests, NULL, NULL);; + return cmocka_run_group_tests(tests, NULL, NULL);; } diff --git a/tests/unit/test_x86_shl_enter_leave.c b/tests/unit/test_x86_shl_enter_leave.c index d53d0482..1ba8fcbc 100644 --- a/tests/unit/test_x86_shl_enter_leave.c +++ b/tests/unit/test_x86_shl_enter_leave.c @@ -16,24 +16,24 @@ typedef struct _reg_value { - uint32_t regId, regValue, mask; + uint32_t regId, regValue, mask; } reg_value; typedef struct _instruction { - const char* asmStr; - uint8_t code[16]; //x86 inst == 15 bytes max - uint32_t codeSize; - reg_value* values; - uint32_t nbValues; - uint32_t addr; + const char* asmStr; + uint8_t code[16]; //x86 inst == 15 bytes max + uint32_t codeSize; + reg_value* values; + uint32_t nbValues; + uint32_t addr; } instruction; typedef struct _block { - instruction* insts[255]; - uint32_t nbInsts; - uint32_t size; + instruction* insts[255]; + uint32_t nbInsts; + uint32_t size; } block; /******************************************************************************/ @@ -42,23 +42,23 @@ typedef struct _block #define CAT(X, Y) CAT2(X, Y) #define BLOCK_START(BLOCK) \ - { \ - block* blockPtr = &BLOCK; \ - blockPtr->nbInsts = 0; \ - instruction* instPtr = NULL; + { \ + block* blockPtr = &BLOCK; \ + blockPtr->nbInsts = 0; \ + instruction* instPtr = NULL; #define BLOCK_END() } #define BLOCK_ADD(CODE_ASM, CODE) \ - const uint8_t CAT(code, __LINE__)[] = CODE; \ - instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, NULL, 0); \ - addInstructionToBlock(blockPtr, instPtr); + const uint8_t CAT(code, __LINE__)[] = CODE; \ + instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, NULL, 0); \ + addInstructionToBlock(blockPtr, instPtr); #define BLOCK_ADD_CHECK(CODE_ASM, CODE, REGVALUES) \ - const uint8_t CAT(code, __LINE__)[] = CODE; \ - const reg_value CAT(regValues, __LINE__)[] = REGVALUES; \ - instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, CAT(regValues, __LINE__), sizeof(CAT(regValues, __LINE__)) / sizeof(reg_value)); \ - addInstructionToBlock(blockPtr, instPtr); + const uint8_t CAT(code, __LINE__)[] = CODE; \ + const reg_value CAT(regValues, __LINE__)[] = REGVALUES; \ + instPtr = newInstruction(CAT(code, __LINE__), sizeof(CAT(code, __LINE__)), CODE_ASM, CAT(regValues, __LINE__), sizeof(CAT(regValues, __LINE__)) / sizeof(reg_value)); \ + addInstructionToBlock(blockPtr, instPtr); #define V(...) { __VA_ARGS__ } @@ -77,43 +77,43 @@ void initRegisters(uc_engine *uc); void hook_code_test_i386_shl(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) { - uint32_t i; - block* b = (block*)user_data; - instruction* currInst = getInstruction(b, (uint32_t)address); - assert_true(currInst != NULL); + uint32_t i; + block* b = (block*)user_data; + instruction* currInst = getInstruction(b, (uint32_t)address); + assert_true(currInst != NULL); - print_message("|\teip=%08x - %s\n", (uint32_t)address, currInst->asmStr); + print_message("|\teip=%08x - %s\n", (uint32_t)address, currInst->asmStr); - for (i = 0; i < currInst->nbValues; i++) - { - uint32_t regValue = getRegisterValue(uc, currInst->values[i].regId); - print_message("|\t\ttesting %s : ", getRegisterName(currInst->values[i].regId)); - assert_int_equal(regValue & currInst->values[i].mask, currInst->values[i].regValue); - print_message("ok\n"); - } + for (i = 0; i < currInst->nbValues; i++) + { + uint32_t regValue = getRegisterValue(uc, currInst->values[i].regId); + print_message("|\t\ttesting %s : ", getRegisterName(currInst->values[i].regId)); + assert_int_equal(regValue & currInst->values[i].mask, currInst->values[i].regValue); + print_message("ok\n"); + } - if (currInst->code[0] == 0xCC) - OK(uc_emu_stop(uc)); + if (currInst->code[0] == 0xCC) + OK(uc_emu_stop(uc)); } bool hook_mem_invalid(uc_engine *uc, uc_mem_type type, uint64_t addr, int size, int64_t value, void *user_data) { - switch (type) - { - default: - print_message("hook_mem_invalid: UC_HOOK_MEM_INVALID type: %d at 0x%" PRIx64 "\n", type, addr); break; - case UC_MEM_READ_UNMAPPED: - print_message("hook_mem_invalid: Read from invalid memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break; - case UC_MEM_WRITE_UNMAPPED: - print_message("hook_mem_invalid: Write to invalid memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break; - case UC_MEM_FETCH_PROT: - print_message("hook_mem_invalid: Fetch from non-executable memory at 0x%" PRIx64 "\n", addr); break; - case UC_MEM_WRITE_PROT: - print_message("hook_mem_invalid: Write to non-writeable memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break; - case UC_MEM_READ_PROT: - print_message("hook_mem_invalid: Read from non-readable memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break; - } - return false; + switch (type) + { + default: + print_message("hook_mem_invalid: UC_HOOK_MEM_INVALID type: %d at 0x%" PRIx64 "\n", type, addr); break; + case UC_MEM_READ_UNMAPPED: + print_message("hook_mem_invalid: Read from invalid memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break; + case UC_MEM_WRITE_UNMAPPED: + print_message("hook_mem_invalid: Write to invalid memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break; + case UC_MEM_FETCH_PROT: + print_message("hook_mem_invalid: Fetch from non-executable memory at 0x%" PRIx64 "\n", addr); break; + case UC_MEM_WRITE_PROT: + print_message("hook_mem_invalid: Write to non-writeable memory at 0x%" PRIx64 ", data size = %u, data value = 0x%" PRIx64 "\n", addr, size, value); break; + case UC_MEM_READ_PROT: + print_message("hook_mem_invalid: Read from non-readable memory at 0x%" PRIx64 ", data size = %u\n", addr, size); break; + } + return false; } #define ADDR_CODE 0x100000 @@ -123,311 +123,311 @@ bool hook_mem_invalid(uc_engine *uc, uc_mem_type type, uint64_t addr, int size, static void test_i386_shl_cl(void **state) { - uc_engine *uc; - uc_hook trace1; - block b; + uc_engine *uc; + uc_hook trace1; + block b; - // Initialize emulator in X86-32bit mode - OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); - OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); - - initRegisters(uc); + // Initialize emulator in X86-32bit mode + OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); + OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); + + initRegisters(uc); - BLOCK_START(b); - BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00)); - BLOCK_ADD_CHECK("mov cl, 2", V(0xB1, 0x02), V(V(UC_X86_REG_EBX, 0x3C, NO_MASK))); - BLOCK_ADD_CHECK("shl ebx, cl", V(0xD3, 0xE3), V(V(UC_X86_REG_CL, 0x2, NO_MASK))); - BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK))); - BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK))); - BLOCK_END(); + BLOCK_START(b); + BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00)); + BLOCK_ADD_CHECK("mov cl, 2", V(0xB1, 0x02), V(V(UC_X86_REG_EBX, 0x3C, NO_MASK))); + BLOCK_ADD_CHECK("shl ebx, cl", V(0xD3, 0xE3), V(V(UC_X86_REG_CL, 0x2, NO_MASK))); + BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK))); + BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK))); + BLOCK_END(); - loadBlock(uc, &b, ADDR_CODE); + loadBlock(uc, &b, ADDR_CODE); - OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); - OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); + OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); + OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); - // emulate machine code in infinite time - OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); + // emulate machine code in infinite time + OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); - freeBlock(&b); + freeBlock(&b); - uc_close(uc); + uc_close(uc); } static void test_i386_shl_imm(void **state) { - uc_engine *uc; - uc_hook trace1; - block b; + uc_engine *uc; + uc_hook trace1; + block b; - // Initialize emulator in X86-32bit mode - OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); - OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); + // Initialize emulator in X86-32bit mode + OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); + OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); - initRegisters(uc); + initRegisters(uc); - BLOCK_START(b); - BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00)); - BLOCK_ADD( "shl ebx, 2", V(0xC1, 0xE3, 0x02)); - BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK))); - BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK))); - BLOCK_END(); + BLOCK_START(b); + BLOCK_ADD( "mov ebx, 3Ch", V(0xBB, 0x3C, 0x00, 0x00, 0x00)); + BLOCK_ADD( "shl ebx, 2", V(0xC1, 0xE3, 0x02)); + BLOCK_ADD_CHECK("lahf", V(0x9F), V(V(UC_X86_REG_EBX, 0xF0, NO_MASK), V(UC_X86_REG_EFLAGS, 0x4, ALL_MASK))); + BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_AH, 0x4, PF_MASK))); + BLOCK_END(); - loadBlock(uc, &b, ADDR_CODE); - - OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); - OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); - - // emulate machine code in infinite time - OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); - - freeBlock(&b); + loadBlock(uc, &b, ADDR_CODE); + + OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); + OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); + + // emulate machine code in infinite time + OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); + + freeBlock(&b); - uc_close(uc); + uc_close(uc); } static void test_i386_enter_leave(void **state) { - uc_engine *uc; - uc_hook trace1; - block b; + uc_engine *uc; + uc_hook trace1; + block b; - // Initialize emulator in X86-32bit mode - OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); - OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); - OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL)); + // Initialize emulator in X86-32bit mode + OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); + OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); + OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL)); - initRegisters(uc); + initRegisters(uc); - BLOCK_START(b); - BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00)); - BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK))); - BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK))); - BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); - BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK))); - BLOCK_ADD_CHECK("enter 0x10,0", V(0xC8, 0x10, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); - BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK))); - BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); - BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); - BLOCK_END(); + BLOCK_START(b); + BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00)); + BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK))); + BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK))); + BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); + BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK))); + BLOCK_ADD_CHECK("enter 0x10,0", V(0xC8, 0x10, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); + BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK))); + BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); + BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); + BLOCK_END(); - loadBlock(uc, &b, ADDR_CODE); + loadBlock(uc, &b, ADDR_CODE); - OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); - OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); + OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); + OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); - // emulate machine code in infinite time - OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); + // emulate machine code in infinite time + OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); - freeBlock(&b); + freeBlock(&b); - uc_close(uc); + uc_close(uc); } static void test_i386_enter_nested_leave(void **state) { - uc_engine *uc; - uc_hook trace1; - block b; + uc_engine *uc; + uc_hook trace1; + block b; - // Initialize emulator in X86-32bit mode - OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); - OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); - OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL)); + // Initialize emulator in X86-32bit mode + OK(uc_open(UC_ARCH_X86, UC_MODE_32, &uc)); + OK(uc_mem_map(uc, ADDR_CODE, 0x1000, UC_PROT_ALL)); + OK(uc_mem_map(uc, ADDR_STACK - 0x1000, 0x1000, UC_PROT_ALL)); - initRegisters(uc); + initRegisters(uc); - BLOCK_START(b); - BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00)); - BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK))); - BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK))); - BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); - BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK))); - BLOCK_ADD_CHECK("mov ebp, esp", V(0x89, 0xE5), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); - BLOCK_ADD_CHECK("enter 0x10,1", V(0xC8, 0x10, 0x00, 0x01), V(V(UC_X86_REG_EBP, 0x200000 - 4, NO_MASK))); - BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 2*4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK))); - BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); - BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); - BLOCK_END(); + BLOCK_START(b); + BLOCK_ADD( "mov esp, 0x200000", V(0xBC, 0x00, 0x00, 0x20, 0x00)); + BLOCK_ADD_CHECK("mov eax, 1", V(0xB8, 0x01, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000, NO_MASK))); + BLOCK_ADD_CHECK("call 0x100015", V(0xE8, 0x06, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x1, NO_MASK))); + BLOCK_ADD_CHECK("mov eax, 3", V(0xB8, 0x03, 0x00, 0x00, 0x00), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); + BLOCK_ADD_CHECK("int3", V(0xCC), V(V(UC_X86_REG_EAX, 0x3, NO_MASK))); + BLOCK_ADD_CHECK("mov ebp, esp", V(0x89, 0xE5), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); + BLOCK_ADD_CHECK("enter 0x10,1", V(0xC8, 0x10, 0x00, 0x01), V(V(UC_X86_REG_EBP, 0x200000 - 4, NO_MASK))); + BLOCK_ADD_CHECK("mov eax, 2", V(0xB8, 0x02, 0x00, 0x00, 0x00), V(V(UC_X86_REG_ESP, 0x200000 - 4 - 2*4 - 0x10, NO_MASK), V(UC_X86_REG_EBP, 0x200000 - 4 - 4, NO_MASK))); + BLOCK_ADD_CHECK("leave", V(0xC9), V(V(UC_X86_REG_EAX, 0x2, NO_MASK))); + BLOCK_ADD_CHECK("ret", V(0xC3), V(V(UC_X86_REG_ESP, 0x200000 - 4, NO_MASK))); + BLOCK_END(); - loadBlock(uc, &b, ADDR_CODE); + loadBlock(uc, &b, ADDR_CODE); - OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); - OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); + OK(uc_hook_add(uc, &trace1, UC_HOOK_CODE, hook_code_test_i386_shl, &b, 1, 0)); + OK(uc_hook_add(uc, &trace1, UC_HOOK_MEM_INVALID, hook_mem_invalid, NULL, 1, 0)); - // emulate machine code in infinite time - OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); + // emulate machine code in infinite time + OK(uc_emu_start(uc, ADDR_CODE, ADDR_CODE + b.size, 0, 0)); - freeBlock(&b); - - uc_close(uc); + freeBlock(&b); + + uc_close(uc); } /******************************************************************************/ int main(void) { - const struct CMUnitTest tests[] = { + const struct CMUnitTest tests[] = { - cmocka_unit_test(test_i386_shl_cl), - cmocka_unit_test(test_i386_shl_imm), - cmocka_unit_test(test_i386_enter_leave), - cmocka_unit_test(test_i386_enter_nested_leave), - }; - return cmocka_run_group_tests(tests, NULL, NULL); + cmocka_unit_test(test_i386_shl_cl), + cmocka_unit_test(test_i386_shl_imm), + cmocka_unit_test(test_i386_enter_leave), + cmocka_unit_test(test_i386_enter_nested_leave), + }; + return cmocka_run_group_tests(tests, NULL, NULL); } /******************************************************************************/ instruction* newInstruction(const uint8_t * _code, uint32_t _codeSize, const char* _asmStr, const reg_value* _values, uint32_t _nbValues) { - instruction* inst = (instruction*)malloc(sizeof(instruction)); + instruction* inst = (instruction*)malloc(sizeof(instruction)); - inst->asmStr = _asmStr; - memcpy(inst->code, _code, _codeSize); - inst->codeSize = _codeSize; - inst->nbValues = 0; - if (_values) - { - inst->values = (reg_value*)malloc(_nbValues*sizeof(reg_value)); - memcpy(inst->values, _values, _nbValues*sizeof(reg_value)); - inst->nbValues = _nbValues; - } + inst->asmStr = _asmStr; + memcpy(inst->code, _code, _codeSize); + inst->codeSize = _codeSize; + inst->nbValues = 0; + if (_values) + { + inst->values = (reg_value*)malloc(_nbValues*sizeof(reg_value)); + memcpy(inst->values, _values, _nbValues*sizeof(reg_value)); + inst->nbValues = _nbValues; + } - return inst; + return inst; } void addInstructionToBlock(block* _b, instruction* _i) { - _b->insts[_b->nbInsts++] = _i; + _b->insts[_b->nbInsts++] = _i; } uint32_t loadBlock(uc_engine *_uc, block* _block, uint32_t _at) { - uint32_t i, j, offset; + uint32_t i, j, offset; - for (i = 0, offset = 0; i < _block->nbInsts; i++) - { - const uint32_t codeSize = _block->insts[i]->codeSize; - const uint8_t* code = _block->insts[i]->code; - _block->insts[i]->addr = _at + offset; - print_message("load: %08X: ", _block->insts[i]->addr); - for (j = 0; j < codeSize; j++) print_message("%02X ", code[j]); - for (j = 0; j < 15 - codeSize; j++) print_message(" "); - print_message("%s\n", _block->insts[i]->asmStr); - OK(uc_mem_write(_uc, _at + offset, code, codeSize)); - offset += codeSize; - } - _block->size = offset; - return offset; + for (i = 0, offset = 0; i < _block->nbInsts; i++) + { + const uint32_t codeSize = _block->insts[i]->codeSize; + const uint8_t* code = _block->insts[i]->code; + _block->insts[i]->addr = _at + offset; + print_message("load: %08X: ", _block->insts[i]->addr); + for (j = 0; j < codeSize; j++) print_message("%02X ", code[j]); + for (j = 0; j < 15 - codeSize; j++) print_message(" "); + print_message("%s\n", _block->insts[i]->asmStr); + OK(uc_mem_write(_uc, _at + offset, code, codeSize)); + offset += codeSize; + } + _block->size = offset; + return offset; } void freeBlock(block* _block) { - uint32_t i; - for (i = 0; i < _block->nbInsts; i++) - { - if (_block->insts[i]->nbValues > 0) - free(_block->insts[i]->values); - free(_block->insts[i]); - } + uint32_t i; + for (i = 0; i < _block->nbInsts; i++) + { + if (_block->insts[i]->nbValues > 0) + free(_block->insts[i]->values); + free(_block->insts[i]); + } } void initRegisters(uc_engine *uc) { - // initialize machine registers - uint32_t zero = 0; - OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero)); - OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero)); - OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero)); - OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero)); - OK(uc_reg_write(uc, UC_X86_REG_EBP, &zero)); - OK(uc_reg_write(uc, UC_X86_REG_ESP, &zero)); - OK(uc_reg_write(uc, UC_X86_REG_EDI, &zero)); - OK(uc_reg_write(uc, UC_X86_REG_ESI, &zero)); - OK(uc_reg_write(uc, UC_X86_REG_EFLAGS, &zero)); + // initialize machine registers + uint32_t zero = 0; + OK(uc_reg_write(uc, UC_X86_REG_EAX, &zero)); + OK(uc_reg_write(uc, UC_X86_REG_EBX, &zero)); + OK(uc_reg_write(uc, UC_X86_REG_ECX, &zero)); + OK(uc_reg_write(uc, UC_X86_REG_EDX, &zero)); + OK(uc_reg_write(uc, UC_X86_REG_EBP, &zero)); + OK(uc_reg_write(uc, UC_X86_REG_ESP, &zero)); + OK(uc_reg_write(uc, UC_X86_REG_EDI, &zero)); + OK(uc_reg_write(uc, UC_X86_REG_ESI, &zero)); + OK(uc_reg_write(uc, UC_X86_REG_EFLAGS, &zero)); } instruction* getInstruction(block* _block, uint32_t _addr) { - uint32_t i; - for (i = 0; i < _block->nbInsts; i++) - { - if (_block->insts[i]->addr == _addr) - return _block->insts[i]; - } - return NULL; + uint32_t i; + for (i = 0; i < _block->nbInsts; i++) + { + if (_block->insts[i]->addr == _addr) + return _block->insts[i]; + } + return NULL; } const char* getRegisterName(uint32_t _regid) { - switch (_regid) - { - //8 - case UC_X86_REG_AH: return "AH"; - case UC_X86_REG_AL: return "AL"; - case UC_X86_REG_BH: return "BH"; - case UC_X86_REG_BL: return "BL"; - case UC_X86_REG_CL: return "CL"; - case UC_X86_REG_CH: return "CH"; - case UC_X86_REG_DH: return "DH"; - case UC_X86_REG_DL: return "DL"; - //16 - case UC_X86_REG_AX: return "AX"; - case UC_X86_REG_BX: return "BX"; - case UC_X86_REG_CX: return "CX"; - case UC_X86_REG_DX: return "DX"; - //32 - case UC_X86_REG_EAX: return "EAX"; - case UC_X86_REG_EBX: return "EBX"; - case UC_X86_REG_ECX: return "ECX"; - case UC_X86_REG_EDX: return "EDX"; - case UC_X86_REG_EDI: return "EDI"; - case UC_X86_REG_ESI: return "ESI"; - case UC_X86_REG_EBP: return "EBP"; - case UC_X86_REG_ESP: return "ESP"; - case UC_X86_REG_EIP: return "EIP"; - case UC_X86_REG_EFLAGS: return "EFLAGS"; + switch (_regid) + { + //8 + case UC_X86_REG_AH: return "AH"; + case UC_X86_REG_AL: return "AL"; + case UC_X86_REG_BH: return "BH"; + case UC_X86_REG_BL: return "BL"; + case UC_X86_REG_CL: return "CL"; + case UC_X86_REG_CH: return "CH"; + case UC_X86_REG_DH: return "DH"; + case UC_X86_REG_DL: return "DL"; + //16 + case UC_X86_REG_AX: return "AX"; + case UC_X86_REG_BX: return "BX"; + case UC_X86_REG_CX: return "CX"; + case UC_X86_REG_DX: return "DX"; + //32 + case UC_X86_REG_EAX: return "EAX"; + case UC_X86_REG_EBX: return "EBX"; + case UC_X86_REG_ECX: return "ECX"; + case UC_X86_REG_EDX: return "EDX"; + case UC_X86_REG_EDI: return "EDI"; + case UC_X86_REG_ESI: return "ESI"; + case UC_X86_REG_EBP: return "EBP"; + case UC_X86_REG_ESP: return "ESP"; + case UC_X86_REG_EIP: return "EIP"; + case UC_X86_REG_EFLAGS: return "EFLAGS"; - default: fail(); - } - return "UNKNOWN"; + default: fail(); + } + return "UNKNOWN"; } uint32_t getRegisterValue(uc_engine *uc, uint32_t _regid) { - switch (_regid) - { - //8 - case UC_X86_REG_AH: case UC_X86_REG_AL: - case UC_X86_REG_BH: case UC_X86_REG_BL: - case UC_X86_REG_CL: case UC_X86_REG_CH: - case UC_X86_REG_DH: case UC_X86_REG_DL: - { - uint8_t val = 0; - OK(uc_reg_read(uc, _regid, &val)); - return val; - } - //16 - case UC_X86_REG_AX: case UC_X86_REG_BX: - case UC_X86_REG_CX: case UC_X86_REG_DX: - { - uint16_t val = 0; - OK(uc_reg_read(uc, _regid, &val)); - return val; - } - //32 - case UC_X86_REG_EAX: case UC_X86_REG_EBX: - case UC_X86_REG_ECX: case UC_X86_REG_EDX: - case UC_X86_REG_EDI: case UC_X86_REG_ESI: - case UC_X86_REG_EBP: case UC_X86_REG_ESP: - case UC_X86_REG_EIP: case UC_X86_REG_EFLAGS: - { - uint32_t val = 0; - OK(uc_reg_read(uc, _regid, &val)); - return val; - } + switch (_regid) + { + //8 + case UC_X86_REG_AH: case UC_X86_REG_AL: + case UC_X86_REG_BH: case UC_X86_REG_BL: + case UC_X86_REG_CL: case UC_X86_REG_CH: + case UC_X86_REG_DH: case UC_X86_REG_DL: + { + uint8_t val = 0; + OK(uc_reg_read(uc, _regid, &val)); + return val; + } + //16 + case UC_X86_REG_AX: case UC_X86_REG_BX: + case UC_X86_REG_CX: case UC_X86_REG_DX: + { + uint16_t val = 0; + OK(uc_reg_read(uc, _regid, &val)); + return val; + } + //32 + case UC_X86_REG_EAX: case UC_X86_REG_EBX: + case UC_X86_REG_ECX: case UC_X86_REG_EDX: + case UC_X86_REG_EDI: case UC_X86_REG_ESI: + case UC_X86_REG_EBP: case UC_X86_REG_ESP: + case UC_X86_REG_EIP: case UC_X86_REG_EFLAGS: + { + uint32_t val = 0; + OK(uc_reg_read(uc, _regid, &val)); + return val; + } - default: fail(); - } - return 0; + default: fail(); + } + return 0; } diff --git a/uc.c b/uc.c index 13855969..8cbfafc2 100644 --- a/uc.c +++ b/uc.c @@ -268,15 +268,15 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result) if (uc->reg_reset) uc->reg_reset(uc); - // init winsock sockets so we can use select() for usleep() implementation + // init winsock sockets so we can use select() for usleep() implementation #ifdef _MSC_VER - { - WSADATA wsa_data; - WSAStartup(0x202, &wsa_data); - } + { + WSADATA wsa_data; + WSAStartup(0x202, &wsa_data); + } #endif - return UC_ERR_OK; + return UC_ERR_OK; } else { return UC_ERR_ARCH; } @@ -355,14 +355,14 @@ uc_err uc_close(uc_engine *uc) memset(uc, 0, sizeof(*uc)); free(uc); - // free winsock sockets - used so we can use select() for usleep() implementation + // free winsock sockets - used so we can use select() for usleep() implementation #ifdef _MSC_VER - { - WSACleanup(); - } + { + WSACleanup(); + } #endif - return UC_ERR_OK; + return UC_ERR_OK; }