From 78254267ffb32114813db2b976193d08621e1422 Mon Sep 17 00:00:00 2001
From: "Dr. David Alan Gilbert" <dgilbert@redhat.com>
Date: Sun, 25 Feb 2018 20:25:32 -0500
Subject: [PATCH] target-i386: Allow physical address bits to be set

Currently QEMU sets the x86 number of physical address bits to the
magic number 40. This is only correct on some small AMD systems;
Intel systems tend to have 36, 39, 46 bits, and large AMD systems
tend to have 48.

Having the value different from your actual hardware is detectable
by the guest and in principal can cause problems;
The current limit of 40 stops TB VMs being created by those lucky
enough to have that much.

This patch lets you set the physical bits by a cpu property but
defaults to the same 40bits which matches TCGs setup.

I've removed the ancient warning about the 42 bit limit in exec.c;
I can't find that limit in there and no one else seems to know where
it is.

We use a magic value of 0 as the property default so that we can
later distinguish between the default and a user set value.

Backports commit af45907a132857cfd47acc998bf5f7c26cd13071 from qemu
---
 qemu/target-i386/cpu.c | 45 +++++++++++++++++++++++++++++++++---------
 qemu/target-i386/cpu.h |  3 +++
 2 files changed, 39 insertions(+), 9 deletions(-)

diff --git a/qemu/target-i386/cpu.c b/qemu/target-i386/cpu.c
index b53512da..6920decf 100644
--- a/qemu/target-i386/cpu.c
+++ b/qemu/target-i386/cpu.c
@@ -25,6 +25,7 @@
 #include "cpu.h"
 #include "exec/exec-all.h"
 #include "sysemu/cpus.h"
+#include "sysemu/kvm.h"
 
 #include "qapi/qmp/qerror.h"
 
@@ -2736,17 +2737,13 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
         break;
     case 0x80000008:
         /* virtual & phys address size in low 2 bytes. */
-/* XXX: This value must match the one used in the MMU code. */
         if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
-            /* 64 bit processor */
-/* XXX: The physical address space is limited to 42 bits in exec.c. */
-            *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
+            /* 64 bit processor, 48 bits virtual, configurable
+             * physical bits.
+             */
+            *eax = 0x00003000 + cpu->phys_bits;
         } else {
-            if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
-                *eax = 0x00000024; /* 36 bits physical */
-            } else {
-                *eax = 0x00000020; /* 32 bits physical */
-            }
+            *eax = cpu->phys_bits;
         }
         *ebx = 0;
         *ecx = 0;
@@ -3036,6 +3033,36 @@ static int x86_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
            & CPUID_EXT2_AMD_ALIASES);
     }
 
+    if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
+        /* 0 means it was not explicitly set by the user (or by machine
+         * compat_props). In this case, the default is the value used by
+         * TCG (40).
+         */
+        if (cpu->phys_bits == 0) {
+            cpu->phys_bits = TCG_PHYS_ADDR_BITS;
+        }
+        // Unicorn: removed KVM checks
+        if (cpu->phys_bits != TCG_PHYS_ADDR_BITS) {
+            error_setg(errp, "TCG only supports phys-bits=%u",
+                              TCG_PHYS_ADDR_BITS);
+            return -1;
+        }
+    } else {
+        /* For 32 bit systems don't use the user set value, but keep
+         * phys_bits consistent with what we tell the guest.
+         */
+        if (cpu->phys_bits != 0) {
+            error_setg(errp, "phys-bits is not user-configurable in 32 bit");
+            return -1;
+        }
+
+        if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
+            cpu->phys_bits = 36;
+        } else {
+            cpu->phys_bits = 32;
+        }
+    }
+
     if (x86_cpu_filter_features(cpu) && cpu->enforce_cpuid) {
         error_setg(&local_err,
                        "TCG doesn't support requested features");
diff --git a/qemu/target-i386/cpu.h b/qemu/target-i386/cpu.h
index 1a911db7..831af2ea 100644
--- a/qemu/target-i386/cpu.h
+++ b/qemu/target-i386/cpu.h
@@ -1185,6 +1185,9 @@ typedef struct X86CPU {
     /* Compatibility bits for old machine types: */
     bool enable_cpuid_0xb;
 
+    /* Number of physical address bits supported */
+    uint32_t phys_bits;
+
     /* in order to simplify APIC support, we leave this pointer to the
        user */
     struct DeviceState *apic_state;