From 782835889ce0b42e25db16f19fecaa8552c92158 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Sun, 7 Mar 2021 12:18:59 -0500 Subject: [PATCH] target/riscv: vector mask population count vmpopc Backports 2e88f551df8fe6af81c0f920b7341ae2c75d00f2 --- qemu/header_gen.py | 1 + qemu/riscv32.h | 1 + qemu/riscv64.h | 1 + qemu/target/riscv/helper.h | 2 ++ qemu/target/riscv/insn32.decode | 1 + qemu/target/riscv/insn_trans/trans_rvv.inc.c | 34 ++++++++++++++++++++ qemu/target/riscv/vector_helper.c | 20 ++++++++++++ 7 files changed, 60 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 17072a55..c8c9b382 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7258,6 +7258,7 @@ riscv_symbols = ( 'helper_vmnor_mm', 'helper_vmornot_mm', 'helper_vmxnor_mm', + 'helper_vmpopc_m', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 807ed079..1a6fc84d 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4694,6 +4694,7 @@ #define helper_vmnor_mm helper_vmnor_mm_riscv32 #define helper_vmornot_mm helper_vmornot_mm_riscv32 #define helper_vmxnor_mm helper_vmxnor_mm_riscv32 +#define helper_vmpopc_m helper_vmpopc_m_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index e5a4bbad..b6c014c3 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4694,6 +4694,7 @@ #define helper_vmnor_mm helper_vmnor_mm_riscv64 #define helper_vmornot_mm helper_vmornot_mm_riscv64 #define helper_vmxnor_mm helper_vmxnor_mm_riscv64 +#define helper_vmpopc_m helper_vmpopc_m_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index dc2f1e9f..20aabb75 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -1104,3 +1104,5 @@ DEF_HELPER_6(vmor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmnor_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmornot_mm, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vmxnor_mm, void, ptr, ptr, ptr, ptr, env, i32) + +DEF_HELPER_4(vmpopc_m, tl, ptr, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index c71cbef1..971c06c0 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -555,6 +555,7 @@ vmor_mm 011010 - ..... ..... 010 ..... 1010111 @r vmnor_mm 011110 - ..... ..... 010 ..... 1010111 @r vmornot_mm 011100 - ..... ..... 010 ..... 1010111 @r vmxnor_mm 011111 - ..... ..... 010 ..... 1010111 @r +vmpopc_m 010100 . ..... ----- 010 ..... 1010111 @r2_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 1e81a722..cabdf9a7 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2427,3 +2427,37 @@ GEN_MM_TRANS(vmor_mm) GEN_MM_TRANS(vmnor_mm) GEN_MM_TRANS(vmornot_mm) GEN_MM_TRANS(vmxnor_mm) + +/* Vector mask population count vmpopc */ +static bool trans_vmpopc_m(DisasContext *s, arg_rmr *a) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + + if (vext_check_isa_ill(s)) { + TCGv_ptr src2, mask; + TCGv dst; + TCGv_i32 desc; + uint32_t data = 0; + data = FIELD_DP32(data, VDATA, MLEN, s->mlen); + data = FIELD_DP32(data, VDATA, VM, a->vm); + data = FIELD_DP32(data, VDATA, LMUL, s->lmul); + + mask = tcg_temp_new_ptr(tcg_ctx); + src2 = tcg_temp_new_ptr(tcg_ctx); + dst = tcg_temp_new(tcg_ctx); + desc = tcg_const_i32(tcg_ctx, simd_desc(0, s->vlen / 8, data)); + + tcg_gen_addi_ptr(tcg_ctx, src2, tcg_ctx->cpu_env, vreg_ofs(s, a->rs2)); + tcg_gen_addi_ptr(tcg_ctx, mask, tcg_ctx->cpu_env, vreg_ofs(s, 0)); + + gen_helper_vmpopc_m(tcg_ctx, dst, mask, src2, tcg_ctx->cpu_env, desc); + gen_set_gpr(s, a->rd, dst); + + tcg_temp_free_ptr(tcg_ctx, mask); + tcg_temp_free_ptr(tcg_ctx, src2); + tcg_temp_free(tcg_ctx, dst); + tcg_temp_free_i32(tcg_ctx, desc); + return true; + } + return false; +} diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index f63b7276..a5092f39 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -4518,3 +4518,23 @@ GEN_VEXT_MASK_VV(vmor_mm, DO_OR) GEN_VEXT_MASK_VV(vmnor_mm, DO_NOR) GEN_VEXT_MASK_VV(vmornot_mm, DO_ORNOT) GEN_VEXT_MASK_VV(vmxnor_mm, DO_XNOR) + +/* Vector mask population count vmpopc */ +target_ulong HELPER(vmpopc_m)(void *v0, void *vs2, CPURISCVState *env, + uint32_t desc) +{ + target_ulong cnt = 0; + uint32_t mlen = vext_mlen(desc); + uint32_t vm = vext_vm(desc); + uint32_t vl = env->vl; + int i; + + for (i = 0; i < vl; i++) { + if (vm || vext_elem_mask(v0, mlen, i)) { + if (vext_elem_mask(vs2, mlen, i)) { + cnt++; + } + } + } + return cnt; +}