From 795bcc7de309dc274f7dbb40d10ccb344665dfaf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20P=2E=20Berrang=C3=A9?= Date: Tue, 22 May 2018 16:56:28 -0400 Subject: [PATCH] i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639) New microcode introduces the "Speculative Store Bypass Disable" CPUID feature bit. This needs to be exposed to guest OS to allow them to protect against CVE-2018-3639. Backports commit d19d1f965904a533998739698020ff4ee8a103da from qemu --- qemu/target/i386/cpu.c | 2 +- qemu/target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c index 034ceac4..1abd9c02 100644 --- a/qemu/target/i386/cpu.c +++ b/qemu/target/i386/cpu.c @@ -661,7 +661,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, "spec-ctrl", NULL, - NULL, NULL, NULL, NULL, + NULL, NULL, NULL, "ssbd", }, 7, true, 0, diff --git a/qemu/target/i386/cpu.h b/qemu/target/i386/cpu.h index 51f6e9a8..5d277548 100644 --- a/qemu/target/i386/cpu.h +++ b/qemu/target/i386/cpu.h @@ -663,6 +663,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control */ +#define CPUID_7_0_EDX_SPEC_CTRL_SSBD (1U << 31) /* Speculative Store Bypass Disable */ #define KVM_HINTS_DEDICATED (1U << 0)