diff --git a/qemu/header_gen.py b/qemu/header_gen.py
index 9c38e29f..810d6135 100644
--- a/qemu/header_gen.py
+++ b/qemu/header_gen.py
@@ -7233,6 +7233,12 @@ riscv_symbols = (
     'helper_vredxor_vs_h',
     'helper_vredxor_vs_w',
     'helper_vredxor_vs_d',
+    'helper_vwredsumu_vs_b',
+    'helper_vwredsumu_vs_h',
+    'helper_vwredsumu_vs_w',
+    'helper_vwredsum_vs_b',
+    'helper_vwredsum_vs_h',
+    'helper_vwredsum_vs_w',
     'pmp_hart_has_privs',
     'pmpaddr_csr_read',
     'pmpaddr_csr_write',
diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h
index 4d327b98..fc90b7b5 100644
--- a/qemu/target/riscv/helper.h
+++ b/qemu/target/riscv/helper.h
@@ -1075,3 +1075,10 @@ DEF_HELPER_6(vredxor_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vredxor_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vredxor_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
 DEF_HELPER_6(vredxor_vs_d, void, ptr, ptr, ptr, ptr, env, i32)
+
+DEF_HELPER_6(vwredsumu_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsumu_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsumu_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_b, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_h, void, ptr, ptr, ptr, ptr, env, i32)
+DEF_HELPER_6(vwredsum_vs_w, void, ptr, ptr, ptr, ptr, env, i32)
diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode
index 878eeecb..b78fd8bc 100644
--- a/qemu/target/riscv/insn32.decode
+++ b/qemu/target/riscv/insn32.decode
@@ -539,6 +539,8 @@ vredminu_vs     000100 . ..... ..... 010 ..... 1010111 @r_vm
 vredmin_vs      000101 . ..... ..... 010 ..... 1010111 @r_vm
 vredmaxu_vs     000110 . ..... ..... 010 ..... 1010111 @r_vm
 vredmax_vs      000111 . ..... ..... 010 ..... 1010111 @r_vm
+vwredsumu_vs    110000 . ..... ..... 000 ..... 1010111 @r_vm
+vwredsum_vs     110001 . ..... ..... 000 ..... 1010111 @r_vm
 
 vsetvli         0 ........... ..... 111 ..... 1010111  @r2_zimm
 vsetvl          1000000 ..... ..... 111 ..... 1010111  @r
diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c
index c2d611d0..93ee02cf 100644
--- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c
@@ -2379,3 +2379,7 @@ GEN_OPIVV_TRANS(vredmin_vs, reduction_check)
 GEN_OPIVV_TRANS(vredand_vs, reduction_check)
 GEN_OPIVV_TRANS(vredor_vs, reduction_check)
 GEN_OPIVV_TRANS(vredxor_vs, reduction_check)
+
+/* Vector Widening Integer Reduction Instructions */
+GEN_OPIVV_WIDEN_TRANS(vwredsum_vs, reduction_check)
+GEN_OPIVV_WIDEN_TRANS(vwredsumu_vs, reduction_check)
diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c
index bcbd7522..c47f1aba 100644
--- a/qemu/target/riscv/vector_helper.c
+++ b/qemu/target/riscv/vector_helper.c
@@ -4382,3 +4382,14 @@ GEN_VEXT_RED(vredxor_vs_b, int8_t, int8_t, H1, H1, DO_XOR, clearb)
 GEN_VEXT_RED(vredxor_vs_h, int16_t, int16_t, H2, H2, DO_XOR, clearh)
 GEN_VEXT_RED(vredxor_vs_w, int32_t, int32_t, H4, H4, DO_XOR, clearl)
 GEN_VEXT_RED(vredxor_vs_d, int64_t, int64_t, H8, H8, DO_XOR, clearq)
+
+/* Vector Widening Integer Reduction Instructions */
+/* signed sum reduction into double-width accumulator */
+GEN_VEXT_RED(vwredsum_vs_b, int16_t, int8_t, H2, H1, DO_ADD, clearh)
+GEN_VEXT_RED(vwredsum_vs_h, int32_t, int16_t, H4, H2, DO_ADD, clearl)
+GEN_VEXT_RED(vwredsum_vs_w, int64_t, int32_t, H8, H4, DO_ADD, clearq)
+
+/* Unsigned sum reduction into double-width accumulator */
+GEN_VEXT_RED(vwredsumu_vs_b, uint16_t, uint8_t, H2, H1, DO_ADD, clearh)
+GEN_VEXT_RED(vwredsumu_vs_h, uint32_t, uint16_t, H4, H2, DO_ADD, clearl)
+GEN_VEXT_RED(vwredsumu_vs_w, uint64_t, uint32_t, H8, H4, DO_ADD, clearq)