From 798ce750d55b1d5302582f96f666a035ec6f1a68 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Date: Mon, 8 Mar 2021 11:35:17 -0500 Subject: [PATCH] target/arm/cpu: Update coding style to make checkpatch.pl happy Backports dddc200dcddd1a4e44c32e2b0f5a3cb248c506a6 --- qemu/target/arm/cpu.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 9fc65c76..da76d50c 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -1624,7 +1624,8 @@ static void cortex_a8_initfn(struct uc_struct *uc, Object *obj, void *opaque) } static const ARMCPRegInfo cortexa9_cp_reginfo[] = { - /* power_control should be set to maximum latency. Again, + /* + * power_control should be set to maximum latency. Again, * default to 0 and set by private hook */ { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0, @@ -1661,7 +1662,8 @@ static void cortex_a9_initfn(struct uc_struct *uc, Object *obj, void *opaque) set_feature(&cpu->env, ARM_FEATURE_NEON); set_feature(&cpu->env, ARM_FEATURE_THUMB2EE); set_feature(&cpu->env, ARM_FEATURE_EL3); - /* Note that A9 supports the MP extensions even for + /* + * Note that A9 supports the MP extensions even for * A9UP and single-core A9MP (which are both different * and valid configurations; we don't model A9UP). */ @@ -1696,7 +1698,8 @@ static void cortex_a9_initfn(struct uc_struct *uc, Object *obj, void *opaque) #ifndef CONFIG_USER_ONLY static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { - /* Linux wants the number of processors from here. + /* + * Linux wants the number of processors from here. * Might as well set the interrupt-controller bit too. */ return ((smp_cpus - 1) << 24) | (1 << 23); @@ -1743,7 +1746,8 @@ static void cortex_a7_initfn(struct uc_struct *uc, Object *obj, void *opaque) cpu->isar.id_mmfr1 = 0x40000000; cpu->isar.id_mmfr2 = 0x01240000; cpu->isar.id_mmfr3 = 0x02102211; - /* a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but + /* + * a7_mpcore_r0p5_trm, page 4-4 gives 0x01101110; but * table 4-41 gives 0x02101110, which includes the arm div insns. */ cpu->isar.id_isar0 = 0x02101110;