diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 76373533..41eb06f6 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64 #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_aarch64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64 +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_aarch64 #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_aarch64 #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_aarch64 #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_aarch64 #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_aarch64 #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_aarch64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64 +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_aarch64 #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_aarch64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64 +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_aarch64 #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_aarch64 #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_aarch64 #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_aarch64 @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64 #define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64 +#define tcg_gen_sars_vec tcg_gen_sars_vec_aarch64 #define tcg_gen_sarv_vec tcg_gen_sarv_vec_aarch64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64 @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_aarch64 #define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64 +#define tcg_gen_shls_vec tcg_gen_shls_vec_aarch64 #define tcg_gen_shlv_vec tcg_gen_shlv_vec_aarch64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_aarch64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64 #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64 +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_aarch64 #define tcg_gen_shrv_vec tcg_gen_shrv_vec_aarch64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 60ca2a7a..2b06d3d4 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64eb #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_aarch64eb #define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64eb +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_aarch64eb #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_aarch64eb #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_aarch64eb #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_aarch64eb #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_aarch64eb #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_aarch64eb #define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64eb +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_aarch64eb #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_aarch64eb #define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64eb +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_aarch64eb #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_aarch64eb #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_aarch64eb #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_aarch64eb @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64eb #define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64eb #define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64eb +#define tcg_gen_sars_vec tcg_gen_sars_vec_aarch64eb #define tcg_gen_sarv_vec tcg_gen_sarv_vec_aarch64eb #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64eb #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64eb @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64eb #define tcg_gen_shli_i64 tcg_gen_shli_i64_aarch64eb #define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64eb +#define tcg_gen_shls_vec tcg_gen_shls_vec_aarch64eb #define tcg_gen_shlv_vec tcg_gen_shlv_vec_aarch64eb #define tcg_gen_shr_i32 tcg_gen_shr_i32_aarch64eb #define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64eb #define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64eb #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64eb +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_aarch64eb #define tcg_gen_shrv_vec tcg_gen_shrv_vec_aarch64eb #define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64eb #define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64eb diff --git a/qemu/arm.h b/qemu/arm.h index 1c47a570..1629f8d5 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_arm #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_arm #define tcg_gen_gvec_sari tcg_gen_gvec_sari_arm +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_arm #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_arm #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_arm #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_arm #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_arm #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_arm #define tcg_gen_gvec_shli tcg_gen_gvec_shli_arm +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_arm #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_arm #define tcg_gen_gvec_shri tcg_gen_gvec_shri_arm +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_arm #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_arm #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_arm #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_arm @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_arm #define tcg_gen_sari_i64 tcg_gen_sari_i64_arm #define tcg_gen_sari_vec tcg_gen_sari_vec_arm +#define tcg_gen_sars_vec tcg_gen_sars_vec_arm #define tcg_gen_sarv_vec tcg_gen_sarv_vec_arm #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_arm #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_arm @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_arm #define tcg_gen_shli_i64 tcg_gen_shli_i64_arm #define tcg_gen_shli_vec tcg_gen_shli_vec_arm +#define tcg_gen_shls_vec tcg_gen_shls_vec_arm #define tcg_gen_shlv_vec tcg_gen_shlv_vec_arm #define tcg_gen_shr_i32 tcg_gen_shr_i32_arm #define tcg_gen_shr_i64 tcg_gen_shr_i64_arm #define tcg_gen_shri_i32 tcg_gen_shri_i32_arm #define tcg_gen_shri_i64 tcg_gen_shri_i64_arm #define tcg_gen_shri_vec tcg_gen_shri_vec_arm +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_arm #define tcg_gen_shrv_vec tcg_gen_shrv_vec_arm #define tcg_gen_smax_i32 tcg_gen_smax_i32_arm #define tcg_gen_smax_i64 tcg_gen_smax_i64_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 6f40df4e..4757cce8 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_armeb #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_armeb #define tcg_gen_gvec_sari tcg_gen_gvec_sari_armeb +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_armeb #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_armeb #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_armeb #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_armeb #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_armeb #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_armeb #define tcg_gen_gvec_shli tcg_gen_gvec_shli_armeb +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_armeb #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_armeb #define tcg_gen_gvec_shri tcg_gen_gvec_shri_armeb +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_armeb #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_armeb #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_armeb #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_armeb @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_armeb #define tcg_gen_sari_i64 tcg_gen_sari_i64_armeb #define tcg_gen_sari_vec tcg_gen_sari_vec_armeb +#define tcg_gen_sars_vec tcg_gen_sars_vec_armeb #define tcg_gen_sarv_vec tcg_gen_sarv_vec_armeb #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_armeb #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_armeb @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_armeb #define tcg_gen_shli_i64 tcg_gen_shli_i64_armeb #define tcg_gen_shli_vec tcg_gen_shli_vec_armeb +#define tcg_gen_shls_vec tcg_gen_shls_vec_armeb #define tcg_gen_shlv_vec tcg_gen_shlv_vec_armeb #define tcg_gen_shr_i32 tcg_gen_shr_i32_armeb #define tcg_gen_shr_i64 tcg_gen_shr_i64_armeb #define tcg_gen_shri_i32 tcg_gen_shri_i32_armeb #define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb #define tcg_gen_shri_vec tcg_gen_shri_vec_armeb +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_armeb #define tcg_gen_shrv_vec tcg_gen_shrv_vec_armeb #define tcg_gen_smax_i32 tcg_gen_smax_i32_armeb #define tcg_gen_smax_i64 tcg_gen_smax_i64_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 20cd473b..d1dbbe47 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -2912,14 +2912,17 @@ symbols = ( 'tcg_gen_gvec_sar32v', 'tcg_gen_gvec_sar64v', 'tcg_gen_gvec_sari', + 'tcg_gen_gvec_sars', 'tcg_gen_gvec_sarv', 'tcg_gen_gvec_shl8v', 'tcg_gen_gvec_shl16v', 'tcg_gen_gvec_shl32v', 'tcg_gen_gvec_shl64v', 'tcg_gen_gvec_shli', + 'tcg_gen_gvec_shls', 'tcg_gen_gvec_shlv', 'tcg_gen_gvec_shri', + 'tcg_gen_gvec_shrs', 'tcg_gen_gvec_shrv', 'tcg_gen_gvec_shr8v', 'tcg_gen_gvec_shr16v', @@ -3036,6 +3039,7 @@ symbols = ( 'tcg_gen_sari_i32', 'tcg_gen_sari_i64', 'tcg_gen_sari_vec', + 'tcg_gen_sars_vec', 'tcg_gen_sarv_vec', 'tcg_gen_setcond_i32', 'tcg_gen_setcond_i64', @@ -3049,12 +3053,14 @@ symbols = ( 'tcg_gen_shli_i32', 'tcg_gen_shli_i64', 'tcg_gen_shli_vec', + 'tcg_gen_shls_vec', 'tcg_gen_shlv_vec', 'tcg_gen_shr_i32', 'tcg_gen_shr_i64', 'tcg_gen_shri_i32', 'tcg_gen_shri_i64', 'tcg_gen_shri_vec', + 'tcg_gen_shrs_vec', 'tcg_gen_shrv_vec', 'tcg_gen_smax_i32', 'tcg_gen_smax_i64', diff --git a/qemu/m68k.h b/qemu/m68k.h index 2231aa04..8cec72b2 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_m68k #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_m68k #define tcg_gen_gvec_sari tcg_gen_gvec_sari_m68k +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_m68k #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_m68k #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_m68k #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_m68k #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_m68k #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_m68k #define tcg_gen_gvec_shli tcg_gen_gvec_shli_m68k +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_m68k #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_m68k #define tcg_gen_gvec_shri tcg_gen_gvec_shri_m68k +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_m68k #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_m68k #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_m68k #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_m68k @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_m68k #define tcg_gen_sari_i64 tcg_gen_sari_i64_m68k #define tcg_gen_sari_vec tcg_gen_sari_vec_m68k +#define tcg_gen_sars_vec tcg_gen_sars_vec_m68k #define tcg_gen_sarv_vec tcg_gen_sarv_vec_m68k #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_m68k #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_m68k @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_m68k #define tcg_gen_shli_i64 tcg_gen_shli_i64_m68k #define tcg_gen_shli_vec tcg_gen_shli_vec_m68k +#define tcg_gen_shls_vec tcg_gen_shls_vec_m68k #define tcg_gen_shlv_vec tcg_gen_shlv_vec_m68k #define tcg_gen_shr_i32 tcg_gen_shr_i32_m68k #define tcg_gen_shr_i64 tcg_gen_shr_i64_m68k #define tcg_gen_shri_i32 tcg_gen_shri_i32_m68k #define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k #define tcg_gen_shri_vec tcg_gen_shri_vec_m68k +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_m68k #define tcg_gen_shrv_vec tcg_gen_shrv_vec_m68k #define tcg_gen_smax_i32 tcg_gen_smax_i32_m68k #define tcg_gen_smax_i64 tcg_gen_smax_i64_m68k diff --git a/qemu/mips.h b/qemu/mips.h index c3cce17f..a042c708 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips #define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_mips #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips #define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_mips #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips #define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_mips #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips #define tcg_gen_sari_i64 tcg_gen_sari_i64_mips #define tcg_gen_sari_vec tcg_gen_sari_vec_mips +#define tcg_gen_sars_vec tcg_gen_sars_vec_mips #define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips #define tcg_gen_shli_i64 tcg_gen_shli_i64_mips #define tcg_gen_shli_vec tcg_gen_shli_vec_mips +#define tcg_gen_shls_vec tcg_gen_shls_vec_mips #define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips #define tcg_gen_shr_i32 tcg_gen_shr_i32_mips #define tcg_gen_shr_i64 tcg_gen_shr_i64_mips #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips #define tcg_gen_shri_vec tcg_gen_shri_vec_mips +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_mips #define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips #define tcg_gen_smax_i32 tcg_gen_smax_i32_mips #define tcg_gen_smax_i64 tcg_gen_smax_i64_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index a3248a59..7aed95e1 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64 #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64 +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_mips64 #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips64 #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips64 #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips64 #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips64 #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64 +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_mips64 #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64 +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_mips64 #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips64 #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips64 #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips64 @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64 #define tcg_gen_sari_vec tcg_gen_sari_vec_mips64 +#define tcg_gen_sars_vec tcg_gen_sars_vec_mips64 #define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64 @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_mips64 #define tcg_gen_shli_vec tcg_gen_shli_vec_mips64 +#define tcg_gen_shls_vec tcg_gen_shls_vec_mips64 #define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_mips64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_mips64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64 #define tcg_gen_shri_vec tcg_gen_shri_vec_mips64 +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_mips64 #define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 813c9f4b..b43851f3 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64el #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips64el #define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64el +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_mips64el #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips64el #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips64el #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips64el #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips64el #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips64el #define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64el +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_mips64el #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips64el #define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64el +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_mips64el #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips64el #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips64el #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips64el @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64el #define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64el #define tcg_gen_sari_vec tcg_gen_sari_vec_mips64el +#define tcg_gen_sars_vec tcg_gen_sars_vec_mips64el #define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips64el #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64el #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64el @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64el #define tcg_gen_shli_i64 tcg_gen_shli_i64_mips64el #define tcg_gen_shli_vec tcg_gen_shli_vec_mips64el +#define tcg_gen_shls_vec tcg_gen_shls_vec_mips64el #define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips64el #define tcg_gen_shr_i32 tcg_gen_shr_i32_mips64el #define tcg_gen_shr_i64 tcg_gen_shr_i64_mips64el #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64el #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el #define tcg_gen_shri_vec tcg_gen_shri_vec_mips64el +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_mips64el #define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips64el #define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64el #define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 46a17a70..d2fc46bf 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mipsel #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mipsel #define tcg_gen_gvec_sari tcg_gen_gvec_sari_mipsel +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_mipsel #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mipsel #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mipsel #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mipsel #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mipsel #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mipsel #define tcg_gen_gvec_shli tcg_gen_gvec_shli_mipsel +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_mipsel #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mipsel #define tcg_gen_gvec_shri tcg_gen_gvec_shri_mipsel +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_mipsel #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mipsel #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mipsel #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mipsel @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_mipsel #define tcg_gen_sari_i64 tcg_gen_sari_i64_mipsel #define tcg_gen_sari_vec tcg_gen_sari_vec_mipsel +#define tcg_gen_sars_vec tcg_gen_sars_vec_mipsel #define tcg_gen_sarv_vec tcg_gen_sarv_vec_mipsel #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mipsel #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mipsel @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_mipsel #define tcg_gen_shli_i64 tcg_gen_shli_i64_mipsel #define tcg_gen_shli_vec tcg_gen_shli_vec_mipsel +#define tcg_gen_shls_vec tcg_gen_shls_vec_mipsel #define tcg_gen_shlv_vec tcg_gen_shlv_vec_mipsel #define tcg_gen_shr_i32 tcg_gen_shr_i32_mipsel #define tcg_gen_shr_i64 tcg_gen_shr_i64_mipsel #define tcg_gen_shri_i32 tcg_gen_shri_i32_mipsel #define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel #define tcg_gen_shri_vec tcg_gen_shri_vec_mipsel +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_mipsel #define tcg_gen_shrv_vec tcg_gen_shrv_vec_mipsel #define tcg_gen_smax_i32 tcg_gen_smax_i32_mipsel #define tcg_gen_smax_i64 tcg_gen_smax_i64_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index e9822ba1..0baedefb 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_powerpc #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_powerpc #define tcg_gen_gvec_sari tcg_gen_gvec_sari_powerpc +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_powerpc #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_powerpc #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_powerpc #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_powerpc #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_powerpc #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_powerpc #define tcg_gen_gvec_shli tcg_gen_gvec_shli_powerpc +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_powerpc #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_powerpc #define tcg_gen_gvec_shri tcg_gen_gvec_shri_powerpc +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_powerpc #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_powerpc #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_powerpc #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_powerpc @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_powerpc #define tcg_gen_sari_i64 tcg_gen_sari_i64_powerpc #define tcg_gen_sari_vec tcg_gen_sari_vec_powerpc +#define tcg_gen_sars_vec tcg_gen_sars_vec_powerpc #define tcg_gen_sarv_vec tcg_gen_sarv_vec_powerpc #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_powerpc #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_powerpc @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_powerpc #define tcg_gen_shli_i64 tcg_gen_shli_i64_powerpc #define tcg_gen_shli_vec tcg_gen_shli_vec_powerpc +#define tcg_gen_shls_vec tcg_gen_shls_vec_powerpc #define tcg_gen_shlv_vec tcg_gen_shlv_vec_powerpc #define tcg_gen_shr_i32 tcg_gen_shr_i32_powerpc #define tcg_gen_shr_i64 tcg_gen_shr_i64_powerpc #define tcg_gen_shri_i32 tcg_gen_shri_i32_powerpc #define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc #define tcg_gen_shri_vec tcg_gen_shri_vec_powerpc +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_powerpc #define tcg_gen_shrv_vec tcg_gen_shrv_vec_powerpc #define tcg_gen_smax_i32 tcg_gen_smax_i32_powerpc #define tcg_gen_smax_i64 tcg_gen_smax_i64_powerpc diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 08f45b0c..5a5d78bd 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv32 #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_riscv32 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv32 +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_riscv32 #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_riscv32 #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_riscv32 #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_riscv32 #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_riscv32 #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_riscv32 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv32 +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_riscv32 #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_riscv32 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv32 +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_riscv32 #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_riscv32 #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_riscv32 #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_riscv32 @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv32 #define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv32 #define tcg_gen_sari_vec tcg_gen_sari_vec_riscv32 +#define tcg_gen_sars_vec tcg_gen_sars_vec_riscv32 #define tcg_gen_sarv_vec tcg_gen_sarv_vec_riscv32 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv32 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv32 @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv32 #define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv32 #define tcg_gen_shli_vec tcg_gen_shli_vec_riscv32 +#define tcg_gen_shls_vec tcg_gen_shls_vec_riscv32 #define tcg_gen_shlv_vec tcg_gen_shlv_vec_riscv32 #define tcg_gen_shr_i32 tcg_gen_shr_i32_riscv32 #define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv32 #define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv32 #define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv32 #define tcg_gen_shri_vec tcg_gen_shri_vec_riscv32 +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_riscv32 #define tcg_gen_shrv_vec tcg_gen_shrv_vec_riscv32 #define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv32 #define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 9c831e59..a0855934 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv64 #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_riscv64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv64 +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_riscv64 #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_riscv64 #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_riscv64 #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_riscv64 #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_riscv64 #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_riscv64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv64 +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_riscv64 #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_riscv64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv64 +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_riscv64 #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_riscv64 #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_riscv64 #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_riscv64 @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv64 #define tcg_gen_sari_vec tcg_gen_sari_vec_riscv64 +#define tcg_gen_sars_vec tcg_gen_sars_vec_riscv64 #define tcg_gen_sarv_vec tcg_gen_sarv_vec_riscv64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv64 @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv64 #define tcg_gen_shli_vec tcg_gen_shli_vec_riscv64 +#define tcg_gen_shls_vec tcg_gen_shls_vec_riscv64 #define tcg_gen_shlv_vec tcg_gen_shlv_vec_riscv64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_riscv64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv64 #define tcg_gen_shri_vec tcg_gen_shri_vec_riscv64 +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_riscv64 #define tcg_gen_shrv_vec tcg_gen_shrv_vec_riscv64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv64 diff --git a/qemu/sparc.h b/qemu/sparc.h index 35791c57..b98d7958 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_sparc #define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_sparc #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_sparc #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_sparc #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_sparc #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_sparc #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_sparc #define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_sparc #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_sparc #define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_sparc #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_sparc #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_sparc #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_sparc @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc #define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc #define tcg_gen_sari_vec tcg_gen_sari_vec_sparc +#define tcg_gen_sars_vec tcg_gen_sars_vec_sparc #define tcg_gen_sarv_vec tcg_gen_sarv_vec_sparc #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc #define tcg_gen_shli_i64 tcg_gen_shli_i64_sparc #define tcg_gen_shli_vec tcg_gen_shli_vec_sparc +#define tcg_gen_shls_vec tcg_gen_shls_vec_sparc #define tcg_gen_shlv_vec tcg_gen_shlv_vec_sparc #define tcg_gen_shr_i32 tcg_gen_shr_i32_sparc #define tcg_gen_shr_i64 tcg_gen_shr_i64_sparc #define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc #define tcg_gen_shri_vec tcg_gen_shri_vec_sparc +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_sparc #define tcg_gen_shrv_vec tcg_gen_shrv_vec_sparc #define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc #define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 06417a02..c73154c9 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc64 #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_sparc64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc64 +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_sparc64 #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_sparc64 #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_sparc64 #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_sparc64 #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_sparc64 #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_sparc64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc64 +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_sparc64 #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_sparc64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc64 +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_sparc64 #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_sparc64 #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_sparc64 #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_sparc64 @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc64 #define tcg_gen_sari_vec tcg_gen_sari_vec_sparc64 +#define tcg_gen_sars_vec tcg_gen_sars_vec_sparc64 #define tcg_gen_sarv_vec tcg_gen_sarv_vec_sparc64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc64 @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_sparc64 #define tcg_gen_shli_vec tcg_gen_shli_vec_sparc64 +#define tcg_gen_shls_vec tcg_gen_shls_vec_sparc64 #define tcg_gen_shlv_vec tcg_gen_shlv_vec_sparc64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_sparc64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_sparc64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64 #define tcg_gen_shri_vec tcg_gen_shri_vec_sparc64 +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_sparc64 #define tcg_gen_shrv_vec tcg_gen_shrv_vec_sparc64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc64 diff --git a/qemu/tcg/tcg-op-gvec.c b/qemu/tcg/tcg-op-gvec.c index d0bf4cfe..c3c19880 100644 --- a/qemu/tcg/tcg-op-gvec.c +++ b/qemu/tcg/tcg-op-gvec.c @@ -2557,6 +2557,220 @@ void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof } } +/* + * Specialized generation vector shifts by a non-constant scalar. + */ + +typedef struct { + void (*fni4)(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32); + void (*fni8)(TCGContext *, TCGv_i64, TCGv_i64, TCGv_i64); + void (*fniv_s)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_i32); + void (*fniv_v)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_vec); + gen_helper_gvec_2 *fno[4]; + TCGOpcode s_list[2]; + TCGOpcode v_list[2]; +} GVecGen2sh; + +static void expand_2sh_vec(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t oprsz, uint32_t tysz, TCGType type, + TCGv_i32 shift, + void (*fni)(TCGContext *, unsigned, TCGv_vec, TCGv_vec, TCGv_i32)) +{ + TCGv_vec t0 = tcg_temp_new_vec(s, type); + uint32_t i; + + for (i = 0; i < oprsz; i += tysz) { + tcg_gen_ld_vec(s, t0, s->cpu_env, aofs + i); + fni(s, vece, t0, t0, shift); + tcg_gen_st_vec(s, t0, s->cpu_env, dofs + i); + } + tcg_temp_free_vec(s, t0); +} + +static void +do_gvec_shifts(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, TCGv_i32 shift, + uint32_t oprsz, uint32_t maxsz, const GVecGen2sh *g) +{ + TCGType type; + uint32_t some; + + check_size_align(oprsz, maxsz, dofs | aofs); + check_overlap_2(dofs, aofs, maxsz); + + /* If the backend has a scalar expansion, great. */ + type = choose_vector_type(g->s_list, vece, oprsz, vece == MO_64); + if (type) { + const TCGOpcode *hold_list = tcg_swap_vecop_list(s, NULL); + switch (type) { + case TCG_TYPE_V256: + some = QEMU_ALIGN_DOWN(oprsz, 32); + expand_2sh_vec(s, vece, dofs, aofs, some, 32, + TCG_TYPE_V256, shift, g->fniv_s); + if (some == oprsz) { + break; + } + dofs += some; + aofs += some; + oprsz -= some; + maxsz -= some; + /* fallthru */ + case TCG_TYPE_V128: + expand_2sh_vec(s, vece, dofs, aofs, oprsz, 16, + TCG_TYPE_V128, shift, g->fniv_s); + break; + case TCG_TYPE_V64: + expand_2sh_vec(s, vece, dofs, aofs, oprsz, 8, + TCG_TYPE_V64, shift, g->fniv_s); + break; + default: + g_assert_not_reached(); + } + tcg_swap_vecop_list(s, hold_list); + goto clear_tail; + } + + /* If the backend supports variable vector shifts, also cool. */ + type = choose_vector_type(g->v_list, vece, oprsz, vece == MO_64); + if (type) { + const TCGOpcode *hold_list = tcg_swap_vecop_list(s, NULL); + TCGv_vec v_shift = tcg_temp_new_vec(s, type); + + if (vece == MO_64) { + TCGv_i64 sh64 = tcg_temp_new_i64(s); + tcg_gen_extu_i32_i64(s, sh64, shift); + tcg_gen_dup_i64_vec(s, MO_64, v_shift, sh64); + tcg_temp_free_i64(s, sh64); + } else { + tcg_gen_dup_i32_vec(s, vece, v_shift, shift); + } + + switch (type) { + case TCG_TYPE_V256: + some = QEMU_ALIGN_DOWN(oprsz, 32); + expand_2s_vec(s, vece, dofs, aofs, some, 32, TCG_TYPE_V256, + v_shift, false, g->fniv_v); + if (some == oprsz) { + break; + } + dofs += some; + aofs += some; + oprsz -= some; + maxsz -= some; + /* fallthru */ + case TCG_TYPE_V128: + expand_2s_vec(s, vece, dofs, aofs, oprsz, 16, TCG_TYPE_V128, + v_shift, false, g->fniv_v); + break; + case TCG_TYPE_V64: + expand_2s_vec(s, vece, dofs, aofs, oprsz, 8, TCG_TYPE_V64, + v_shift, false, g->fniv_v); + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_vec(s, v_shift); + tcg_swap_vecop_list(s, hold_list); + goto clear_tail; + } + + /* Otherwise fall back to integral... */ + if (vece == MO_32 && check_size_impl(oprsz, 4)) { + expand_2s_i32(s, dofs, aofs, oprsz, shift, false, g->fni4); + } else if (vece == MO_64 && check_size_impl(oprsz, 8)) { + TCGv_i64 sh64 = tcg_temp_new_i64(s); + tcg_gen_extu_i32_i64(s, sh64, shift); + expand_2s_i64(s, dofs, aofs, oprsz, sh64, false, g->fni8); + tcg_temp_free_i64(s, sh64); + } else { + TCGv_ptr a0 = tcg_temp_new_ptr(s); + TCGv_ptr a1 = tcg_temp_new_ptr(s); + TCGv_i32 desc = tcg_temp_new_i32(s); + + tcg_gen_shli_i32(s, desc, shift, SIMD_DATA_SHIFT); + tcg_gen_ori_i32(s, desc, desc, simd_desc(oprsz, maxsz, 0)); + tcg_gen_addi_ptr(s, a0, s->cpu_env, dofs); + tcg_gen_addi_ptr(s, a1, s->cpu_env, aofs); + + g->fno[vece](s, a0, a1, desc); + + tcg_temp_free_ptr(s, a0); + tcg_temp_free_ptr(s, a1); + tcg_temp_free_i32(s, desc); + return; + } + + clear_tail: + if (oprsz < maxsz) { + expand_clr(s, dofs + oprsz, maxsz - oprsz); + } +} + +void tcg_gen_gvec_shls(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g = { + .fni4 = tcg_gen_shl_i32, + .fni8 = tcg_gen_shl_i64, + .fniv_s = tcg_gen_shls_vec, + .fniv_v = tcg_gen_shlv_vec, + .fno = { + gen_helper_gvec_shl8i, + gen_helper_gvec_shl16i, + gen_helper_gvec_shl32i, + gen_helper_gvec_shl64i, + }, + .s_list = { INDEX_op_shls_vec, 0 }, + .v_list = { INDEX_op_shlv_vec, 0 }, + }; + + tcg_debug_assert(vece <= MO_64); + do_gvec_shifts(s, vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + +void tcg_gen_gvec_shrs(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g = { + .fni4 = tcg_gen_shr_i32, + .fni8 = tcg_gen_shr_i64, + .fniv_s = tcg_gen_shrs_vec, + .fniv_v = tcg_gen_shrv_vec, + .fno = { + gen_helper_gvec_shr8i, + gen_helper_gvec_shr16i, + gen_helper_gvec_shr32i, + gen_helper_gvec_shr64i, + }, + .s_list = { INDEX_op_shrs_vec, 0 }, + .v_list = { INDEX_op_shrv_vec, 0 }, + }; + + tcg_debug_assert(vece <= MO_64); + do_gvec_shifts(s, vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + +void tcg_gen_gvec_sars(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz) +{ + static const GVecGen2sh g = { + .fni4 = tcg_gen_sar_i32, + .fni8 = tcg_gen_sar_i64, + .fniv_s = tcg_gen_sars_vec, + .fniv_v = tcg_gen_sarv_vec, + .fno = { + gen_helper_gvec_sar8i, + gen_helper_gvec_sar16i, + gen_helper_gvec_sar32i, + gen_helper_gvec_sar64i, + }, + .s_list = { INDEX_op_sars_vec, 0 }, + .v_list = { INDEX_op_sarv_vec, 0 }, + }; + + tcg_debug_assert(vece <= MO_64); + do_gvec_shifts(s, vece, dofs, aofs, shift, oprsz, maxsz, &g); +} + /* * Expand D = A << (B % element bits) * diff --git a/qemu/tcg/tcg-op-gvec.h b/qemu/tcg/tcg-op-gvec.h index d4ea46aa..ab0daaed 100644 --- a/qemu/tcg/tcg-op-gvec.h +++ b/qemu/tcg/tcg-op-gvec.h @@ -313,6 +313,13 @@ void tcg_gen_gvec_shri(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shls(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrs(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sars(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + TCGv_i32 shift, uint32_t oprsz, uint32_t maxsz); + /* * Perform vector shift by vector element, modulo the element size. * E.g. D[i] = A[i] << (B[i] % (8 << vece)). diff --git a/qemu/tcg/tcg-op-vec.c b/qemu/tcg/tcg-op-vec.c index cf0b0050..e9be941c 100644 --- a/qemu/tcg/tcg-op-vec.c +++ b/qemu/tcg/tcg-op-vec.c @@ -603,3 +603,57 @@ void tcg_gen_sarv_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv { do_op3(s, vece, r, a, b, INDEX_op_sarv_vec); } + +static void do_shifts(TCGContext *tcg_ctx, unsigned vece, TCGv_vec r, TCGv_vec a, + TCGv_i32 s, TCGOpcode opc_s, TCGOpcode opc_v) +{ + TCGTemp *rt = tcgv_vec_temp(tcg_ctx, r); + TCGTemp *at = tcgv_vec_temp(tcg_ctx, a); + TCGTemp *st = tcgv_i32_temp(tcg_ctx, s); + TCGArg ri = temp_arg(rt); + TCGArg ai = temp_arg(at); + TCGArg si = temp_arg(st); + TCGType type = rt->base_type; + const TCGOpcode *hold_list; + int can; + + tcg_debug_assert(at->base_type >= type); + tcg_assert_listed_vecop(tcg_ctx, opc_s); + hold_list = tcg_swap_vecop_list(tcg_ctx, NULL); + + can = tcg_can_emit_vec_op(opc_s, type, vece); + if (can > 0) { + vec_gen_3(tcg_ctx, opc_s, type, vece, ri, ai, si); + } else if (can < 0) { + tcg_expand_vec_op(tcg_ctx, opc_s, type, vece, ri, ai, si); + } else { + TCGv_vec vec_s = tcg_temp_new_vec(tcg_ctx, type); + + if (vece == MO_64) { + TCGv_i64 s64 = tcg_temp_new_i64(tcg_ctx); + tcg_gen_extu_i32_i64(tcg_ctx, s64, s); + tcg_gen_dup_i64_vec(tcg_ctx, MO_64, vec_s, s64); + tcg_temp_free_i64(tcg_ctx, s64); + } else { + tcg_gen_dup_i32_vec(tcg_ctx, vece, vec_s, s); + } + do_op3(tcg_ctx, vece, r, a, vec_s, opc_v); + tcg_temp_free_vec(tcg_ctx, vec_s); + } + tcg_swap_vecop_list(tcg_ctx, hold_list); +} + +void tcg_gen_shls_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(s, vece, r, a, b, INDEX_op_shls_vec, INDEX_op_shlv_vec); +} + +void tcg_gen_shrs_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(s, vece, r, a, b, INDEX_op_shrs_vec, INDEX_op_shrv_vec); +} + +void tcg_gen_sars_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 b) +{ + do_shifts(s, vece, r, a, b, INDEX_op_sars_vec, INDEX_op_sarv_vec); +} diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index cc6f5b5a..d2e09e21 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -1000,6 +1000,10 @@ void tcg_gen_shli_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64 void tcg_gen_shri_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_shls_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_shrs_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); +void tcg_gen_sars_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_i32 s); + void tcg_gen_shlv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_shrv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); void tcg_gen_sarv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 86058773..2429888c 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -2906,14 +2906,17 @@ #define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_x86_64 #define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_x86_64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_x86_64 +#define tcg_gen_gvec_sars tcg_gen_gvec_sars_x86_64 #define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_x86_64 #define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_x86_64 #define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_x86_64 #define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_x86_64 #define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_x86_64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_x86_64 +#define tcg_gen_gvec_shls tcg_gen_gvec_shls_x86_64 #define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_x86_64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_x86_64 +#define tcg_gen_gvec_shrs tcg_gen_gvec_shrs_x86_64 #define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_x86_64 #define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_x86_64 #define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_x86_64 @@ -3030,6 +3033,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_x86_64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_x86_64 #define tcg_gen_sari_vec tcg_gen_sari_vec_x86_64 +#define tcg_gen_sars_vec tcg_gen_sars_vec_x86_64 #define tcg_gen_sarv_vec tcg_gen_sarv_vec_x86_64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_x86_64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_x86_64 @@ -3043,12 +3047,14 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_x86_64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_x86_64 #define tcg_gen_shli_vec tcg_gen_shli_vec_x86_64 +#define tcg_gen_shls_vec tcg_gen_shls_vec_x86_64 #define tcg_gen_shlv_vec tcg_gen_shlv_vec_x86_64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_x86_64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_x86_64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_x86_64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64 #define tcg_gen_shri_vec tcg_gen_shri_vec_x86_64 +#define tcg_gen_shrs_vec tcg_gen_shrs_vec_x86_64 #define tcg_gen_shrv_vec tcg_gen_shrv_vec_x86_64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_x86_64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_x86_64