From 7a16bc6876a74dc17a286727c845295d23fb90d7 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 13 Jun 2019 18:37:51 -0400 Subject: [PATCH] target/arm: Convert VMOV (imm) to decodetree Convert the VFP VMOV (immediate) instruction to decodetree. Backports commit b518c753f0b94e14e01e97b4ec42c100dafc0cc2 from qemu --- qemu/target/arm/translate-vfp.inc.c | 131 ++++++++++++++++++++++++++++ qemu/target/arm/translate.c | 27 +----- qemu/target/arm/vfp.decode | 5 ++ 3 files changed, 138 insertions(+), 25 deletions(-) diff --git a/qemu/target/arm/translate-vfp.inc.c b/qemu/target/arm/translate-vfp.inc.c index 21d16e8f..7dcdd182 100644 --- a/qemu/target/arm/translate-vfp.inc.c +++ b/qemu/target/arm/translate-vfp.inc.c @@ -1623,3 +1623,134 @@ static bool trans_VFM_dp(DisasContext *s, arg_VFM_sp *a) return true; } + +static bool trans_VMOV_imm_sp(DisasContext *s, arg_VMOV_imm_sp *a) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + uint32_t delta_d = 0; + uint32_t bank_mask = 0; + int veclen = s->vec_len; + TCGv_i32 fd; + uint32_t n, i, vd; + + vd = a->vd; + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen != 0 || s->vec_stride != 0)) { + return false; + } + + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask = 0x18; + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) == 0) { + /* scalar */ + veclen = 0; + } else { + delta_d = s->vec_stride + 1; + } + } + + n = (a->imm4h << 28) & 0x80000000; + i = ((a->imm4h << 4) & 0x70) | a->imm4l; + if (i & 0x40) { + i |= 0x780; + } else { + i |= 0x800; + } + n |= i << 19; + + fd = tcg_temp_new_i32(tcg_ctx); + tcg_gen_movi_i32(tcg_ctx, fd, n); + + for (;;) { + neon_store_reg32(s, fd, vd); + + if (veclen == 0) { + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + } + + tcg_temp_free_i32(tcg_ctx, fd); + return true; +} + +static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a) +{ + TCGContext *tcg_ctx = s->uc->tcg_ctx; + uint32_t delta_d = 0; + uint32_t bank_mask = 0; + int veclen = s->vec_len; + TCGv_i64 fd; + uint32_t n, i, vd; + + vd = a->vd; + + /* UNDEF accesses to D16-D31 if they don't exist. */ + if (!dc_isar_feature(aa32_fp_d32, s) && (vd & 0x10)) { + return false; + } + + if (!dc_isar_feature(aa32_fpshvec, s) && + (veclen != 0 || s->vec_stride != 0)) { + return false; + } + + if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { + return false; + } + + if (!vfp_access_check(s)) { + return true; + } + + if (veclen > 0) { + bank_mask = 0xc; + /* Figure out what type of vector operation this is. */ + if ((vd & bank_mask) == 0) { + /* scalar */ + veclen = 0; + } else { + delta_d = (s->vec_stride >> 1) + 1; + } + } + + n = (a->imm4h << 28) & 0x80000000; + i = ((a->imm4h << 4) & 0x70) | a->imm4l; + if (i & 0x40) { + i |= 0x3f80; + } else { + i |= 0x4000; + } + n |= i << 16; + + fd = tcg_temp_new_i64(tcg_ctx); + tcg_gen_movi_i64(tcg_ctx, fd, ((uint64_t)n) << 32); + + for (;;) { + neon_store_reg64(s, fd, vd); + + if (veclen == 0) { + break; + } + + /* Set up the operands for the next iteration */ + veclen--; + vd = ((vd + delta_d) & (bank_mask - 1)) | (vd & bank_mask); + } + + tcg_temp_free_i64(tcg_ctx, fd); + return true; +} diff --git a/qemu/target/arm/translate.c b/qemu/target/arm/translate.c index 2be9ed58..a7adce3d 100644 --- a/qemu/target/arm/translate.c +++ b/qemu/target/arm/translate.c @@ -3134,7 +3134,7 @@ static void gen_neon_dup_high16(DisasContext *s, TCGv_i32 var) static int disas_vfp_insn(DisasContext *s, uint32_t insn) { TCGContext *tcg_ctx = s->uc->tcg_ctx; - uint32_t rd, rn, rm, op, i, n, delta_d, delta_m, bank_mask; + uint32_t rd, rn, rm, op, delta_d, delta_m, bank_mask; int dp, veclen; TCGv_i32 tmp; TCGv_i32 tmp2; @@ -3194,7 +3194,7 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) rn = VFP_SREG_N(insn); switch (op) { - case 0 ... 13: + case 0 ... 14: /* Already handled by decodetree */ return 1; default: @@ -3380,29 +3380,6 @@ static int disas_vfp_insn(DisasContext *s, uint32_t insn) for (;;) { /* Perform the calculation. */ switch (op) { - case 14: /* fconst */ - if (!arm_dc_feature(s, ARM_FEATURE_VFP3)) { - return 1; - } - - n = (insn << 12) & 0x80000000; - i = ((insn >> 12) & 0x70) | (insn & 0xf); - if (dp) { - if (i & 0x40) - i |= 0x3f80; - else - i |= 0x4000; - n |= i << 16; - tcg_gen_movi_i64(tcg_ctx, s->F0d, ((uint64_t)n) << 32); - } else { - if (i & 0x40) - i |= 0x780; - else - i |= 0x800; - n |= i << 19; - tcg_gen_movi_i32(tcg_ctx, s->F0s, n); - } - break; case 15: /* extension space */ switch (rn) { case 0: /* cpy */ diff --git a/qemu/target/arm/vfp.decode b/qemu/target/arm/vfp.decode index 37eec0e1..1818d4f7 100644 --- a/qemu/target/arm/vfp.decode +++ b/qemu/target/arm/vfp.decode @@ -151,3 +151,8 @@ VFM_sp ---- 1110 1.10 .... .... 1010 . o2:1 . 0 .... \ vm=%vm_sp vn=%vn_sp vd=%vd_sp o1=2 VFM_dp ---- 1110 1.10 .... .... 1011 . o2:1 . 0 .... \ vm=%vm_dp vn=%vn_dp vd=%vd_dp o1=2 + +VMOV_imm_sp ---- 1110 1.11 imm4h:4 .... 1010 0000 imm4l:4 \ + vd=%vd_sp +VMOV_imm_dp ---- 1110 1.11 imm4h:4 .... 1011 0000 imm4l:4 \ + vd=%vd_dp