From 7be3cda1ea59f0538ade1e9430339801efcb8aff Mon Sep 17 00:00:00 2001 From: "Edgar E. Iglesias" Date: Sat, 17 Feb 2018 13:14:30 -0500 Subject: [PATCH] target-arm: lpae: Move declaration of t0sz and t1sz Move declaration of t0sz and t1sz to the top of the function avoiding a mix of code and variable declarations. No functional change. Backports commit 1f4c8c18a5b6f4fad13e13b7e3828124c6c8f34d from qemu --- qemu/target-arm/helper.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 52239bbb..5d2a04dc 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -5831,6 +5831,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, MMUFaultType fault_type = translation_fault; uint32_t level = 1; uint32_t epd = 0; + int32_t t0sz, t1sz; int32_t tsz; uint32_t tg; uint64_t ttbr; @@ -5886,12 +5887,12 @@ static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address, * This is a Non-secure PL0/1 stage 1 translation, so controlled by * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32: */ - int32_t t0sz = extract32(tcr->raw_tcr, 0, 6); + t0sz = extract32(tcr->raw_tcr, 0, 6); if (va_size == 64) { t0sz = MIN(t0sz, 39); t0sz = MAX(t0sz, 16); } - int32_t t1sz = extract32(tcr->raw_tcr, 16, 6); + t1sz = extract32(tcr->raw_tcr, 16, 6); if (va_size == 64) { t1sz = MIN(t1sz, 39); t1sz = MAX(t1sz, 16);