From 7bef6489a866f0b1cab0bf4062d310bb9a86bf54 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 26 Feb 2021 13:58:58 -0500 Subject: [PATCH] target/arm: Merge do_vector2_p into do_mov_p This is the only user of the function Backports d0b2df5a01eeccbac71d4d883158b91e7f9a6a29 --- qemu/target/arm/translate-sve.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index c364dde2..8600755c 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -177,19 +177,6 @@ static void do_dupi_z(DisasContext *s, int rd, uint64_t word) tcg_gen_gvec_dup_imm(tcg_ctx, MO_64, vec_full_reg_offset(s, rd), vsz, vsz, word); } -/* Invoke a vector expander on two Pregs. */ -static bool do_vector2_p(DisasContext *s, GVecGen2Fn *gvec_fn, - int esz, int rd, int rn) -{ - if (sve_access_check(s)) { - TCGContext *tcg_ctx = s->uc->tcg_ctx; - unsigned psz = pred_gvec_reg_size(s); - gvec_fn(tcg_ctx, esz, pred_full_reg_offset(s, rd), - pred_full_reg_offset(s, rn), psz, psz); - } - return true; -} - /* Invoke a vector expander on three Pregs. */ static bool do_vector3_p(DisasContext *s, GVecGen3Fn *gvec_fn, int esz, int rd, int rn, int rm) @@ -223,7 +210,13 @@ static bool do_vecop4_p(DisasContext *s, const GVecGen4 *gvec_op, /* Invoke a vector move on two Pregs. */ static bool do_mov_p(DisasContext *s, int rd, int rn) { - return do_vector2_p(s, tcg_gen_gvec_mov, 0, rd, rn); + if (sve_access_check(s)) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + unsigned psz = pred_gvec_reg_size(s); + tcg_gen_gvec_mov(tcg_ctx, MO_8, pred_full_reg_offset(s, rd), + pred_full_reg_offset(s, rn), psz, psz); + } + return true; } /* Set the cpu flags as per a return from an SVE helper. */