diff --git a/qemu/configure b/qemu/configure index 103ae848..7f860ddf 100755 --- a/qemu/configure +++ b/qemu/configure @@ -175,6 +175,8 @@ solaris="no" softmmu="yes" pie="" tcg="yes" +cpuid_h="no" +avx2_opt="no" # parse CC options first for opt do @@ -1043,7 +1045,6 @@ fi ######################################## # check if cpuid.h is usable. -cpuid_h=no cat > $TMPC << EOF #include int main(void) { @@ -1065,6 +1066,29 @@ if compile_prog "" "" ; then cpuid_h=yes fi +########################################## +# avx2 optimization requirement check +# +# There is no point enabling this if cpuid.h is not usable, +# since we won't be able to select the new routines. + +if test $cpuid_h = yes; then + cat > $TMPC << EOF +#pragma GCC push_options +#pragma GCC target("avx2") +#include +#include +static int bar(void *a) { + __m256i x = *(__m256i *)a; + return _mm256_testz_si256(x, x); +} +int main(int argc, char *argv[]) { return bar(argv[0]); } +EOF + if compile_object "" ; then + avx2_opt="yes" + fi +fi + ######################################## # check if __[u]int128_t is usable. @@ -1279,6 +1303,7 @@ if test "$tcg" = "yes" ; then echo "TCG debug enabled $debug_tcg" echo "TCG interpreter $tcg_interpreter" fi +echo "avx2 optimization $avx2_opt" config_host_mak="config-host.mak" @@ -1343,6 +1368,10 @@ if test "$tcg" = "yes"; then fi fi +if test "$avx2_opt" = "yes" ; then + echo "CONFIG_AVX2_OPT=y" >> $config_host_mak +fi + # XXX: suppress that if [ "$bsd" = "yes" ] ; then echo "CONFIG_BSD=y" >> $config_host_mak diff --git a/qemu/include/qemu/cpuid.h b/qemu/include/qemu/cpuid.h new file mode 100644 index 00000000..ade841cb --- /dev/null +++ b/qemu/include/qemu/cpuid.h @@ -0,0 +1,59 @@ +/* cpuid.h: Macros to identify the properties of an x86 host. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_CPUID_H +#define QEMU_CPUID_H + +#if !defined(CONFIG_CPUID_H) && !defined(_MSC_VER) +# error " is unusable with this compiler" +#endif + +#if defined(CONFIG_CPUID_H) && !defined(_MSC_VER) +#include +#endif + +/* Cover the uses that we have within qemu. */ +/* ??? Irritating that we have the same information in target/i386/. */ + +/* Leaf 1, %edx */ +#ifndef bit_CMOV +#define bit_CMOV (1 << 15) +#endif +#ifndef bit_SSE2 +#define bit_SSE2 (1 << 26) +#endif + +/* Leaf 1, %ecx */ +#ifndef bit_SSE4_1 +#define bit_SSE4_1 (1 << 19) +#endif +#ifndef bit_MOVBE +#define bit_MOVBE (1 << 22) +#endif +#ifndef bit_OSXSAVE +#define bit_OSXSAVE (1 << 27) +#endif +#ifndef bit_AVX +#define bit_AVX (1 << 28) +#endif + +/* Leaf 7, %ebx */ +#ifndef bit_BMI +#define bit_BMI (1 << 3) +#endif +#ifndef bit_AVX2 +#define bit_AVX2 (1 << 5) +#endif +#ifndef bit_BMI2 +#define bit_BMI2 (1 << 8) +#endif + +/* Leaf 0x80000001, %ecx */ +#ifndef bit_LZCNT +#define bit_LZCNT (1 << 5) +#endif + +#endif /* QEMU_CPUID_H */ diff --git a/qemu/target/i386/cpu.c b/qemu/target/i386/cpu.c index fb5b1b49..418f8350 100644 --- a/qemu/target/i386/cpu.c +++ b/qemu/target/i386/cpu.c @@ -29,7 +29,7 @@ #include "qapi/qmp/qdict.h" #include "qapi/qmp/qerror.h" -#include "qapi-visit.h" +#include "qapi/qapi-visit.h" #include "qapi/visitor.h" #include "hw/hw.h" diff --git a/qemu/tcg/i386/tcg-target.inc.c b/qemu/tcg/i386/tcg-target.inc.c index 8fbf3728..6affa9d6 100644 --- a/qemu/tcg/i386/tcg-target.inc.c +++ b/qemu/tcg/i386/tcg-target.inc.c @@ -144,23 +144,14 @@ static const int tcg_target_call_oarg_regs[] = { #if defined(CONFIG_CPUID_H) #ifdef _MSC_VER #include -/* %ecx */ -#define bit_MOVBE (1 << 22) -/* %edx */ -#define bit_CMOV (1 << 15) -/* Extended Features (%eax == 7) */ -#define bit_BMI (1 << 3) -#define bit_BMI2 (1 << 8) -#else -#include #endif +#include "qemu/cpuid.h" #endif -/* For 32-bit, we are going to attempt to determine at runtime whether cmov - is available. */ +/* For 64-bit, we always know that CMOV is available. */ #if TCG_TARGET_REG_BITS == 64 # define have_cmov 1 -#elif defined(CONFIG_CPUID_H) && defined(bit_CMOV) +#elif defined(CONFIG_CPUID_H) static bool have_cmov; #else # define have_cmov 0 @@ -173,14 +164,13 @@ bool have_popcnt; bool have_avx1; bool have_avx2; -#if defined(CONFIG_CPUID_H) && defined(bit_BMI2) +#ifdef CONFIG_CPUID_H +static bool have_movbe; static bool have_bmi2; -#else -static bool have_bmi2 = 0; -#endif -#if defined(CONFIG_CPUID_H) && defined(bit_LZCNT) static bool have_lzcnt; #else +# define have_movbe 0 +# define have_bmi2 0 # define have_lzcnt 0 #endif @@ -3598,14 +3588,10 @@ static void tcg_target_init(TCGContext *s) available, we'll use a small forward branch. */ have_cmov = (d & bit_CMOV) != 0; #endif -#ifndef have_movbe /* MOVBE is only available on Intel Atom and Haswell CPUs, so we need to probe for it. */ s->have_movbe = (c & bit_MOVBE) != 0; -#endif -#ifdef bit_POPCNT have_popcnt = (c & bit_POPCNT) != 0; -#endif /* There are a number of things we must check before we can be sure of not hitting invalid opcode. */ @@ -3620,15 +3606,13 @@ static void tcg_target_init(TCGContext *s) } // TODO: MSVC-compatible equivalent -#ifndef have_lzcnt max = __get_cpuid_max(0x8000000, 0); if (max >= 1) { __cpuid(0x80000001, a, b, c, d); /* LZCNT was introduced with AMD Barcelona and Intel Haswell CPUs. */ have_lzcnt = (c & bit_LZCNT) != 0; } -#endif -#endif +#endif /* CONFIG_CPUID_H */ s->tcg_target_available_regs[TCG_TYPE_I32] = ALL_GENERAL_REGS;