From 806d72035e8816138fbfce1f164bb330bcdd5929 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Sat, 24 Feb 2018 16:49:51 -0500 Subject: [PATCH] target-arm: Don't try to set ESR IL bit in arm_cpu_do_interrupt_aarch64() Remove some incorrect code from arm_cpu_do_interrupt_aarch64() which attempts to set the IL bit in the syndrome register based on the value of env->thumb. This is wrong in several ways: * IL doesn't indicate Thumb-vs-ARM, it indicates instruction length (which may be 16 or 32 for Thumb and is always 32 for ARM) * not every syndrome format uses IL like this -- for some IL is always set, and for some it is always clear * the code is changing esr_el[new_el] even for interrupt entry, which is not supposed to modify ESR_ELx at all Delete the code, and instead rely on the syndrome value in env->exception.syndrome having already been set up with the correct value of IL. Backports commit 78f1edb19fe11fa0c5d0bf484db59a384f455d3c from qemu --- qemu/target-arm/helper.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c index 9315886e..1c938a41 100644 --- a/qemu/target-arm/helper.c +++ b/qemu/target-arm/helper.c @@ -5611,9 +5611,6 @@ static void arm_cpu_do_interrupt_aarch64_(CPUState *cs) env->elr_el[new_el] = env->pc; } else { env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env); - if (!env->thumb) { - env->cp15.esr_el[new_el] |= 1 << 25; - } env->elr_el[new_el] = env->regs[15]; aarch64_sync_32_to_64(env);