From 808d929d7c24aa5a5735b0f5ae15b69b771fc7f0 Mon Sep 17 00:00:00 2001 From: Peter Maydell Date: Thu, 13 Jun 2019 16:36:43 -0400 Subject: [PATCH] target/arm: Fix Cortex-R5F MVFR values The Cortex-R5F initfn was not correctly setting up the MVFR ID register values. Fill these in, since some subsequent patches will use ID register checks rather than CPU feature bit checks. Backports commit 3de79d335c9aa7d726865e3933d9b21781032183 from qemu --- qemu/target/arm/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/qemu/target/arm/cpu.c b/qemu/target/arm/cpu.c index 8db666ae..a01c7d1b 100644 --- a/qemu/target/arm/cpu.c +++ b/qemu/target/arm/cpu.c @@ -1304,6 +1304,8 @@ static void cortex_r5f_initfn(struct uc_struct *uc, Object *obj, void *opaque) cortex_r5_initfn(uc, obj, opaque); set_feature(&cpu->env, ARM_FEATURE_VFP3); + cpu->isar.mvfr0 = 0x10110221; + cpu->isar.mvfr1 = 0x00000011; } static const ARMCPRegInfo cortexa8_cp_reginfo[] = {