diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h
index 8e3cd183..b4377f41 100644
--- a/qemu/target/riscv/cpu.h
+++ b/qemu/target/riscv/cpu.h
@@ -136,7 +136,7 @@ struct CPURISCVState {
      * wuth the invariant that CPU_INTERRUPT_HARD is set iff mip is non-zero.
      * mip is 32-bits to allow atomic_read on 32-bit hosts.
      */
-    uint32_t mip;
+    target_ulong mip;
     uint32_t miclaim;
 
     target_ulong mie;