diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 19f540ab..4c7d28e9 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3287,6 +3287,9 @@ #define helper_sve_andv_d helper_sve_andv_d_aarch64 #define helper_sve_andv_h helper_sve_andv_h_aarch64 #define helper_sve_andv_s helper_sve_andv_s_aarch64 +#define helper_sve_asr_zpzw_b helper_sve_asr_zpzw_b_aarch64 +#define helper_sve_asr_zpzw_h helper_sve_asr_zpzw_h_aarch64 +#define helper_sve_asr_zpzw_s helper_sve_asr_zpzw_s_aarch64 #define helper_sve_asr_zpzz_b helper_sve_asr_zpzz_b_aarch64 #define helper_sve_asr_zpzz_d helper_sve_asr_zpzz_d_aarch64 #define helper_sve_asr_zpzz_h helper_sve_asr_zpzz_h_aarch64 @@ -3321,6 +3324,9 @@ #define helper_sve_lsl_zpzi_d helper_sve_lsl_zpzi_d_aarch64 #define helper_sve_lsl_zpzi_h helper_sve_lsl_zpzi_h_aarch64 #define helper_sve_lsl_zpzi_s helper_sve_lsl_zpzi_s_aarch64 +#define helper_sve_lsl_zpzw_b helper_sve_lsl_zpzw_b_aarch64 +#define helper_sve_lsl_zpzw_h helper_sve_lsl_zpzw_h_aarch64 +#define helper_sve_lsl_zpzw_s helper_sve_lsl_zpzw_s_aarch64 #define helper_sve_lsl_zpzz_b helper_sve_lsl_zpzz_b_aarch64 #define helper_sve_lsl_zpzz_d helper_sve_lsl_zpzz_d_aarch64 #define helper_sve_lsl_zpzz_h helper_sve_lsl_zpzz_h_aarch64 @@ -3329,6 +3335,9 @@ #define helper_sve_lsr_zpzi_d helper_sve_lsr_zpzi_d_aarch64 #define helper_sve_lsr_zpzi_h helper_sve_lsr_zpzi_h_aarch64 #define helper_sve_lsr_zpzi_s helper_sve_lsr_zpzi_s_aarch64 +#define helper_sve_lsr_zpzw_b helper_sve_lsr_zpzw_b_aarch64 +#define helper_sve_lsr_zpzw_h helper_sve_lsr_zpzw_h_aarch64 +#define helper_sve_lsr_zpzw_s helper_sve_lsr_zpzw_s_aarch64 #define helper_sve_lsr_zpzz_b helper_sve_lsr_zpzz_b_aarch64 #define helper_sve_lsr_zpzz_d helper_sve_lsr_zpzz_d_aarch64 #define helper_sve_lsr_zpzz_h helper_sve_lsr_zpzz_h_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 6ec07882..9b6317aa 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3287,6 +3287,9 @@ #define helper_sve_andv_d helper_sve_andv_d_aarch64eb #define helper_sve_andv_h helper_sve_andv_h_aarch64eb #define helper_sve_andv_s helper_sve_andv_s_aarch64eb +#define helper_sve_asr_zpzw_b helper_sve_asr_zpzw_b_aarch64eb +#define helper_sve_asr_zpzw_h helper_sve_asr_zpzw_h_aarch64eb +#define helper_sve_asr_zpzw_s helper_sve_asr_zpzw_s_aarch64eb #define helper_sve_asr_zpzz_b helper_sve_asr_zpzz_b_aarch64eb #define helper_sve_asr_zpzz_d helper_sve_asr_zpzz_d_aarch64eb #define helper_sve_asr_zpzz_h helper_sve_asr_zpzz_h_aarch64eb @@ -3321,6 +3324,9 @@ #define helper_sve_lsl_zpzi_d helper_sve_lsl_zpzi_d_aarch64eb #define helper_sve_lsl_zpzi_h helper_sve_lsl_zpzi_h_aarch64eb #define helper_sve_lsl_zpzi_s helper_sve_lsl_zpzi_s_aarch64eb +#define helper_sve_lsl_zpzw_b helper_sve_lsl_zpzw_b_aarch64eb +#define helper_sve_lsl_zpzw_h helper_sve_lsl_zpzw_h_aarch64eb +#define helper_sve_lsl_zpzw_s helper_sve_lsl_zpzw_s_aarch64eb #define helper_sve_lsl_zpzz_b helper_sve_lsl_zpzz_b_aarch64eb #define helper_sve_lsl_zpzz_d helper_sve_lsl_zpzz_d_aarch64eb #define helper_sve_lsl_zpzz_h helper_sve_lsl_zpzz_h_aarch64eb @@ -3329,6 +3335,9 @@ #define helper_sve_lsr_zpzi_d helper_sve_lsr_zpzi_d_aarch64eb #define helper_sve_lsr_zpzi_h helper_sve_lsr_zpzi_h_aarch64eb #define helper_sve_lsr_zpzi_s helper_sve_lsr_zpzi_s_aarch64eb +#define helper_sve_lsr_zpzw_b helper_sve_lsr_zpzw_b_aarch64eb +#define helper_sve_lsr_zpzw_h helper_sve_lsr_zpzw_h_aarch64eb +#define helper_sve_lsr_zpzw_s helper_sve_lsr_zpzw_s_aarch64eb #define helper_sve_lsr_zpzz_b helper_sve_lsr_zpzz_b_aarch64eb #define helper_sve_lsr_zpzz_d helper_sve_lsr_zpzz_d_aarch64eb #define helper_sve_lsr_zpzz_h helper_sve_lsr_zpzz_h_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index bd6a72a5..ce89e067 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3308,6 +3308,9 @@ aarch64_symbols = ( 'helper_sve_andv_d', 'helper_sve_andv_h', 'helper_sve_andv_s', + 'helper_sve_asr_zpzw_b', + 'helper_sve_asr_zpzw_h', + 'helper_sve_asr_zpzw_s', 'helper_sve_asr_zpzz_b', 'helper_sve_asr_zpzz_d', 'helper_sve_asr_zpzz_h', @@ -3342,6 +3345,9 @@ aarch64_symbols = ( 'helper_sve_lsl_zpzi_d', 'helper_sve_lsl_zpzi_h', 'helper_sve_lsl_zpzi_s', + 'helper_sve_lsl_zpzw_b', + 'helper_sve_lsl_zpzw_h', + 'helper_sve_lsl_zpzw_s', 'helper_sve_lsl_zpzz_b', 'helper_sve_lsl_zpzz_d', 'helper_sve_lsl_zpzz_h', @@ -3350,6 +3356,9 @@ aarch64_symbols = ( 'helper_sve_lsr_zpzi_d', 'helper_sve_lsr_zpzi_h', 'helper_sve_lsr_zpzi_s', + 'helper_sve_lsr_zpzw_b', + 'helper_sve_lsr_zpzw_h', + 'helper_sve_lsr_zpzw_s', 'helper_sve_lsr_zpzz_b', 'helper_sve_lsr_zpzz_d', 'helper_sve_lsr_zpzz_h', diff --git a/qemu/target/arm/helper-sve.h b/qemu/target/arm/helper-sve.h index 0cc02ee5..d5165801 100644 --- a/qemu/target/arm/helper-sve.h +++ b/qemu/target/arm/helper-sve.h @@ -195,6 +195,27 @@ DEF_HELPER_FLAGS_5(sve_lsl_zpzz_s, TCG_CALL_NO_RWG, DEF_HELPER_FLAGS_5(sve_lsl_zpzz_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_asr_zpzw_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_asr_zpzw_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_asr_zpzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_lsr_zpzw_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsr_zpzw_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsr_zpzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_5(sve_lsl_zpzw_b, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsl_zpzw_h, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_5(sve_lsl_zpzw_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_3(sve_orv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_orv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) DEF_HELPER_FLAGS_3(sve_orv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32) diff --git a/qemu/target/arm/sve.decode b/qemu/target/arm/sve.decode index 8267963b..1de289e5 100644 --- a/qemu/target/arm/sve.decode +++ b/qemu/target/arm/sve.decode @@ -157,6 +157,12 @@ ASR_zpzz 00000100 .. 010 100 100 ... ..... ..... @rdm_pg_rn # ASRR LSR_zpzz 00000100 .. 010 101 100 ... ..... ..... @rdm_pg_rn # LSRR LSL_zpzz 00000100 .. 010 111 100 ... ..... ..... @rdm_pg_rn # LSLR +# SVE bitwise shift by wide elements (predicated) +# Note these require size != 3. +ASR_zpzw 00000100 .. 011 000 100 ... ..... ..... @rdn_pg_rm +LSR_zpzw 00000100 .. 011 001 100 ... ..... ..... @rdn_pg_rm +LSL_zpzw 00000100 .. 011 011 100 ... ..... ..... @rdn_pg_rm + ### SVE Logical - Unpredicated Group # SVE bitwise logical operations (unpredicated) diff --git a/qemu/target/arm/sve_helper.c b/qemu/target/arm/sve_helper.c index 3aa6d3e1..56b0ea3b 100644 --- a/qemu/target/arm/sve_helper.c +++ b/qemu/target/arm/sve_helper.c @@ -464,6 +464,41 @@ DO_ZPZZ_D(sve_lsl_zpzz_d, uint64_t, DO_LSL) #undef DO_ZPZZ #undef DO_ZPZZ_D +/* Three-operand expander, controlled by a predicate, in which the + * third operand is "wide". That is, for D = N op M, the same 64-bit + * value of M is used with all of the narrower values of N. + */ +#define DO_ZPZW(NAME, TYPE, TYPEW, H, OP) \ +void HELPER(NAME)(void *vd, void *vn, void *vm, void *vg, uint32_t desc) \ +{ \ + intptr_t i, opr_sz = simd_oprsz(desc); \ + for (i = 0; i < opr_sz; ) { \ + uint8_t pg = *(uint8_t *)(vg + H1(i >> 3)); \ + TYPEW mm = *(TYPEW *)(vm + i); \ + do { \ + if (pg & 1) { \ + TYPE nn = *(TYPE *)(vn + H(i)); \ + *(TYPE *)(vd + H(i)) = OP(nn, mm); \ + } \ + i += sizeof(TYPE), pg >>= sizeof(TYPE); \ + } while (i & 7); \ + } \ +} + +DO_ZPZW(sve_asr_zpzw_b, int8_t, uint64_t, H1, DO_ASR) +DO_ZPZW(sve_lsr_zpzw_b, uint8_t, uint64_t, H1, DO_LSR) +DO_ZPZW(sve_lsl_zpzw_b, uint8_t, uint64_t, H1, DO_LSL) + +DO_ZPZW(sve_asr_zpzw_h, int16_t, uint64_t, H1_2, DO_ASR) +DO_ZPZW(sve_lsr_zpzw_h, uint16_t, uint64_t, H1_2, DO_LSR) +DO_ZPZW(sve_lsl_zpzw_h, uint16_t, uint64_t, H1_2, DO_LSL) + +DO_ZPZW(sve_asr_zpzw_s, int32_t, uint64_t, H1_4, DO_ASR) +DO_ZPZW(sve_lsr_zpzw_s, uint32_t, uint64_t, H1_4, DO_LSR) +DO_ZPZW(sve_lsl_zpzw_s, uint32_t, uint64_t, H1_4, DO_LSL) + +#undef DO_ZPZW + /* Two-operand reduction expander, controlled by a predicate. * The difference between TYPERED and TYPERET has to do with * sign-extension. E.g. for SMAX, TYPERED must be signed, diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index 6a68f95c..d008f216 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -506,6 +506,30 @@ static bool trans_ASRD(DisasContext *s, arg_rpri_esz *a, uint32_t insn) } } +/* + *** SVE Bitwise Shift - Predicated Group + */ + +#define DO_ZPZW(NAME, name) \ +static bool trans_##NAME##_zpzw(DisasContext *s, arg_rprr_esz *a, \ + uint32_t insn) \ +{ \ + static gen_helper_gvec_4 * const fns[3] = { \ + gen_helper_sve_##name##_zpzw_b, gen_helper_sve_##name##_zpzw_h, \ + gen_helper_sve_##name##_zpzw_s, \ + }; \ + if (a->esz < 0 || a->esz >= 3) { \ + return false; \ + } \ + return do_zpzz_ool(s, a, fns[a->esz]); \ +} + +DO_ZPZW(ASR, asr) +DO_ZPZW(LSR, lsr) +DO_ZPZW(LSL, lsl) + +#undef DO_ZPZW + /* *** SVE Predicate Logical Operations Group */