diff --git a/qemu/header_gen.py b/qemu/header_gen.py index efbdc7e5..7259987c 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7169,6 +7169,18 @@ riscv_symbols = ( 'helper_vfmerge_vfm_h', 'helper_vfmerge_vfm_w', 'helper_vfmerge_vfm_d', + 'helper_vfcvt_xu_f_v_h', + 'helper_vfcvt_xu_f_v_w', + 'helper_vfcvt_xu_f_v_d', + 'helper_vfcvt_x_f_v_h', + 'helper_vfcvt_x_f_v_w', + 'helper_vfcvt_x_f_v_d', + 'helper_vfcvt_f_xu_v_h', + 'helper_vfcvt_f_xu_v_w', + 'helper_vfcvt_f_xu_v_d', + 'helper_vfcvt_f_x_v_h', + 'helper_vfcvt_f_x_v_w', + 'helper_vfcvt_f_x_v_d', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 5fcdcfd7..841e1615 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4605,6 +4605,18 @@ #define helper_vfmerge_vfm_h helper_vfmerge_vfm_h_riscv32 #define helper_vfmerge_vfm_w helper_vfmerge_vfm_w_riscv32 #define helper_vfmerge_vfm_d helper_vfmerge_vfm_d_riscv32 +#define helper_vfcvt_xu_f_v_h helper_vfcvt_xu_f_v_h_riscv32 +#define helper_vfcvt_xu_f_v_w helper_vfcvt_xu_f_v_w_riscv32 +#define helper_vfcvt_xu_f_v_d helper_vfcvt_xu_f_v_d_riscv32 +#define helper_vfcvt_x_f_v_h helper_vfcvt_x_f_v_h_riscv32 +#define helper_vfcvt_x_f_v_w helper_vfcvt_x_f_v_w_riscv32 +#define helper_vfcvt_x_f_v_d helper_vfcvt_x_f_v_d_riscv32 +#define helper_vfcvt_f_xu_v_h helper_vfcvt_f_xu_v_h_riscv32 +#define helper_vfcvt_f_xu_v_w helper_vfcvt_f_xu_v_w_riscv32 +#define helper_vfcvt_f_xu_v_d helper_vfcvt_f_xu_v_d_riscv32 +#define helper_vfcvt_f_x_v_h helper_vfcvt_f_x_v_h_riscv32 +#define helper_vfcvt_f_x_v_w helper_vfcvt_f_x_v_w_riscv32 +#define helper_vfcvt_f_x_v_d helper_vfcvt_f_x_v_d_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 5b03635c..ff4229c0 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4605,6 +4605,18 @@ #define helper_vfmerge_vfm_h helper_vfmerge_vfm_h_riscv64 #define helper_vfmerge_vfm_w helper_vfmerge_vfm_w_riscv64 #define helper_vfmerge_vfm_d helper_vfmerge_vfm_d_riscv64 +#define helper_vfcvt_xu_f_v_h helper_vfcvt_xu_f_v_h_riscv64 +#define helper_vfcvt_xu_f_v_w helper_vfcvt_xu_f_v_w_riscv64 +#define helper_vfcvt_xu_f_v_d helper_vfcvt_xu_f_v_d_riscv64 +#define helper_vfcvt_x_f_v_h helper_vfcvt_x_f_v_h_riscv64 +#define helper_vfcvt_x_f_v_w helper_vfcvt_x_f_v_w_riscv64 +#define helper_vfcvt_x_f_v_d helper_vfcvt_x_f_v_d_riscv64 +#define helper_vfcvt_f_xu_v_h helper_vfcvt_f_xu_v_h_riscv64 +#define helper_vfcvt_f_xu_v_w helper_vfcvt_f_xu_v_w_riscv64 +#define helper_vfcvt_f_xu_v_d helper_vfcvt_f_xu_v_d_riscv64 +#define helper_vfcvt_f_x_v_h helper_vfcvt_f_x_v_h_riscv64 +#define helper_vfcvt_f_x_v_w helper_vfcvt_f_x_v_w_riscv64 +#define helper_vfcvt_f_x_v_d helper_vfcvt_f_x_v_d_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index fc1bd5ea..414e7d50 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -1007,3 +1007,16 @@ DEF_HELPER_5(vfclass_v_d, void, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vfmerge_vfm_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmerge_vfm_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfmerge_vfm_d, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_5(vfcvt_xu_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_xu_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_xu_f_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_x_f_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_x_f_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_x_f_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_xu_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_xu_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_xu_v_d, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_x_v_h, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_x_v_w, void, ptr, ptr, ptr, env, i32) +DEF_HELPER_5(vfcvt_f_x_v_d, void, ptr, ptr, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index 38e7445a..913c3b09 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -517,6 +517,10 @@ vmford_vf 011010 . ..... ..... 101 ..... 1010111 @r_vm vfclass_v 100011 . ..... 10000 001 ..... 1010111 @r2_vm vfmerge_vfm 010111 0 ..... ..... 101 ..... 1010111 @r_vm_0 vfmv_v_f 010111 1 00000 ..... 101 ..... 1010111 @r2 +vfcvt_xu_f_v 100010 . ..... 00000 001 ..... 1010111 @r2_vm +vfcvt_x_f_v 100010 . ..... 00001 001 ..... 1010111 @r2_vm +vfcvt_f_xu_v 100010 . ..... 00010 001 ..... 1010111 @r2_vm +vfcvt_f_x_v 100010 . ..... 00011 001 ..... 1010111 @r2_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index bfee1fc0..7ccff035 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2257,3 +2257,9 @@ static bool trans_vfmv_v_f(DisasContext *s, arg_vfmv_v_f *a) } return false; } + +/* Single-Width Floating-Point/Integer Type-Convert Instructions */ +GEN_OPFV_TRANS(vfcvt_xu_f_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_x_f_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_f_xu_v, opfv_check) +GEN_OPFV_TRANS(vfcvt_f_x_v, opfv_check) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 2a1c8914..34f08437 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -4194,3 +4194,36 @@ void HELPER(NAME)(void *vd, void *v0, uint64_t s1, void *vs2, \ GEN_VFMERGE_VF(vfmerge_vfm_h, int16_t, H2, clearh) GEN_VFMERGE_VF(vfmerge_vfm_w, int32_t, H4, clearl) GEN_VFMERGE_VF(vfmerge_vfm_d, int64_t, H8, clearq) + +/* Single-Width Floating-Point/Integer Type-Convert Instructions */ +/* vfcvt.xu.f.v vd, vs2, vm # Convert float to unsigned integer. */ +RVVCALL(OPFVV1, vfcvt_xu_f_v_h, OP_UU_H, H2, H2, float16_to_uint16) +RVVCALL(OPFVV1, vfcvt_xu_f_v_w, OP_UU_W, H4, H4, float32_to_uint32) +RVVCALL(OPFVV1, vfcvt_xu_f_v_d, OP_UU_D, H8, H8, float64_to_uint64) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_xu_f_v_d, 8, 8, clearq) + +/* vfcvt.x.f.v vd, vs2, vm # Convert float to signed integer. */ +RVVCALL(OPFVV1, vfcvt_x_f_v_h, OP_UU_H, H2, H2, float16_to_int16) +RVVCALL(OPFVV1, vfcvt_x_f_v_w, OP_UU_W, H4, H4, float32_to_int32) +RVVCALL(OPFVV1, vfcvt_x_f_v_d, OP_UU_D, H8, H8, float64_to_int64) +GEN_VEXT_V_ENV(vfcvt_x_f_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_x_f_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_x_f_v_d, 8, 8, clearq) + +/* vfcvt.f.xu.v vd, vs2, vm # Convert unsigned integer to float. */ +RVVCALL(OPFVV1, vfcvt_f_xu_v_h, OP_UU_H, H2, H2, uint16_to_float16) +RVVCALL(OPFVV1, vfcvt_f_xu_v_w, OP_UU_W, H4, H4, uint32_to_float32) +RVVCALL(OPFVV1, vfcvt_f_xu_v_d, OP_UU_D, H8, H8, uint64_to_float64) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_f_xu_v_d, 8, 8, clearq) + +/* vfcvt.f.x.v vd, vs2, vm # Convert integer to float. */ +RVVCALL(OPFVV1, vfcvt_f_x_v_h, OP_UU_H, H2, H2, int16_to_float16) +RVVCALL(OPFVV1, vfcvt_f_x_v_w, OP_UU_W, H4, H4, int32_to_float32) +RVVCALL(OPFVV1, vfcvt_f_x_v_d, OP_UU_D, H8, H8, int64_to_float64) +GEN_VEXT_V_ENV(vfcvt_f_x_v_h, 2, 2, clearh) +GEN_VEXT_V_ENV(vfcvt_f_x_v_w, 4, 4, clearl) +GEN_VEXT_V_ENV(vfcvt_f_x_v_d, 8, 8, clearq)