diff --git a/tests/regress/mips_single_step_sp.py b/tests/regress/mips_single_step_sp.py index bacdeb1f..b3c78400 100755 --- a/tests/regress/mips_single_step_sp.py +++ b/tests/regress/mips_single_step_sp.py @@ -3,6 +3,8 @@ from unicorn import * from unicorn.mips_const import * +import regress + def code_hook(uc, addr, size, user_data): print 'code hook: pc=%08x sp=%08x' % (addr, uc.reg_read(UC_MIPS_REG_SP)) @@ -36,6 +38,14 @@ def run(step=False): print 'sp =', hex(uc.reg_read(UC_MIPS_REG_SP)) print 'at =', hex(uc.reg_read(UC_MIPS_REG_AT)) print + return uc.reg_read(UC_MIPS_REG_SP) -run(step=False) -run(step=True) + +class MipsSingleStep(regress.RegressTest): + def test(self): + sp1 = run(step=False) + sp2 = run(step=True) + self.assertEqual(sp1, sp2) + +if __name__ == '__main__': + regress.main() diff --git a/tests/regress/mips_syscall_pc.py b/tests/regress/mips_syscall_pc.py index 3533f3ea..995b154f 100755 --- a/tests/regress/mips_syscall_pc.py +++ b/tests/regress/mips_syscall_pc.py @@ -3,16 +3,25 @@ from unicorn import * from unicorn.mips_const import * +import regress + def intr_hook(uc, intno, data): print 'interrupt=%d, v0=%d, pc=0x%08x' % (intno, uc.reg_read(UC_MIPS_REG_V0), uc.reg_read(UC_MIPS_REG_PC)) -addr = 0x40000 -code = '0c000000'.decode('hex') # syscall +class MipsSyscall(regress.RegressTest): + def test(self): + addr = 0x40000 + code = '0c000000'.decode('hex') # syscall -uc = Uc(UC_ARCH_MIPS, UC_MODE_MIPS32 + UC_MODE_LITTLE_ENDIAN) -uc.mem_map(addr, 0x1000) -uc.mem_write(addr, code) -uc.reg_write(UC_MIPS_REG_V0, 100) -uc.hook_add(UC_HOOK_INTR, intr_hook) + uc = Uc(UC_ARCH_MIPS, UC_MODE_MIPS32 + UC_MODE_LITTLE_ENDIAN) + uc.mem_map(addr, 0x1000) + uc.mem_write(addr, code) + uc.reg_write(UC_MIPS_REG_V0, 100) + uc.hook_add(UC_HOOK_INTR, intr_hook) -uc.emu_start(addr, addr+len(code)) + uc.emu_start(addr, addr+len(code)) + self.assertEqual(0x40004, uc.reg_read(UC_MIPS_REG_PC)) + + +if __name__ == '__main__': + regress.main()