diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 7ac16699..76373533 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_aarch64 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_aarch64 #define helper_gvec_sar8i helper_gvec_sar8i_aarch64 +#define helper_gvec_sar8v helper_gvec_sar8v_aarch64 #define helper_gvec_sar16i helper_gvec_sar16i_aarch64 +#define helper_gvec_sar16v helper_gvec_sar16v_aarch64 #define helper_gvec_sar32i helper_gvec_sar32i_aarch64 +#define helper_gvec_sar32v helper_gvec_sar32v_aarch64 #define helper_gvec_sar64i helper_gvec_sar64i_aarch64 +#define helper_gvec_sar64v helper_gvec_sar64v_aarch64 #define helper_gvec_sdot_b helper_gvec_sdot_b_aarch64 #define helper_gvec_sdot_h helper_gvec_sdot_h_aarch64 #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_aarch64 #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_aarch64 #define helper_gvec_shl8i helper_gvec_shl8i_aarch64 +#define helper_gvec_shl8v helper_gvec_shl8v_aarch64 #define helper_gvec_shl16i helper_gvec_shl16i_aarch64 +#define helper_gvec_shl16v helper_gvec_shl16v_aarch64 #define helper_gvec_shl32i helper_gvec_shl32i_aarch64 +#define helper_gvec_shl32v helper_gvec_shl32v_aarch64 #define helper_gvec_shl64i helper_gvec_shl64i_aarch64 +#define helper_gvec_shl64v helper_gvec_shl64v_aarch64 #define helper_gvec_shr8i helper_gvec_shr8i_aarch64 +#define helper_gvec_shr8v helper_gvec_shr8v_aarch64 #define helper_gvec_shr16i helper_gvec_shr16i_aarch64 +#define helper_gvec_shr16v helper_gvec_shr16v_aarch64 #define helper_gvec_shr32i helper_gvec_shr32i_aarch64 +#define helper_gvec_shr32v helper_gvec_shr32v_aarch64 #define helper_gvec_shr64i helper_gvec_shr64i_aarch64 +#define helper_gvec_shr64v helper_gvec_shr64v_aarch64 #define helper_gvec_smax8 helper_gvec_smax8_aarch64 #define helper_gvec_smax16 helper_gvec_smax16_aarch64 #define helper_gvec_smax32 helper_gvec_smax32_aarch64 @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64 #define tcg_gen_gvec_ori tcg_gen_gvec_ori_aarch64 #define tcg_gen_gvec_ors tcg_gen_gvec_ors_aarch64 +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_aarch64 +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_aarch64 +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64 +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_aarch64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64 +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_aarch64 +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_aarch64 +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_aarch64 +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_aarch64 +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_aarch64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64 +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_aarch64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64 +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_aarch64 +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_aarch64 +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_aarch64 +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_aarch64 +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_aarch64 #define tcg_gen_gvec_smax tcg_gen_gvec_smax_aarch64 #define tcg_gen_gvec_smin tcg_gen_gvec_smin_aarch64 #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_aarch64 @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64 #define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64 +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_aarch64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64 #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64 @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_aarch64 #define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64 +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_aarch64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_aarch64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64 #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64 +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_aarch64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64 #define tcg_gen_smax_vec tcg_gen_smax_vec_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index d0228505..60ca2a7a 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_aarch64eb #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_aarch64eb #define helper_gvec_sar8i helper_gvec_sar8i_aarch64eb +#define helper_gvec_sar8v helper_gvec_sar8v_aarch64eb #define helper_gvec_sar16i helper_gvec_sar16i_aarch64eb +#define helper_gvec_sar16v helper_gvec_sar16v_aarch64eb #define helper_gvec_sar32i helper_gvec_sar32i_aarch64eb +#define helper_gvec_sar32v helper_gvec_sar32v_aarch64eb #define helper_gvec_sar64i helper_gvec_sar64i_aarch64eb +#define helper_gvec_sar64v helper_gvec_sar64v_aarch64eb #define helper_gvec_sdot_b helper_gvec_sdot_b_aarch64eb #define helper_gvec_sdot_h helper_gvec_sdot_h_aarch64eb #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_aarch64eb #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_aarch64eb #define helper_gvec_shl8i helper_gvec_shl8i_aarch64eb +#define helper_gvec_shl8v helper_gvec_shl8v_aarch64eb #define helper_gvec_shl16i helper_gvec_shl16i_aarch64eb +#define helper_gvec_shl16v helper_gvec_shl16v_aarch64eb #define helper_gvec_shl32i helper_gvec_shl32i_aarch64eb +#define helper_gvec_shl32v helper_gvec_shl32v_aarch64eb #define helper_gvec_shl64i helper_gvec_shl64i_aarch64eb +#define helper_gvec_shl64v helper_gvec_shl64v_aarch64eb #define helper_gvec_shr8i helper_gvec_shr8i_aarch64eb +#define helper_gvec_shr8v helper_gvec_shr8v_aarch64eb #define helper_gvec_shr16i helper_gvec_shr16i_aarch64eb +#define helper_gvec_shr16v helper_gvec_shr16v_aarch64eb #define helper_gvec_shr32i helper_gvec_shr32i_aarch64eb +#define helper_gvec_shr32v helper_gvec_shr32v_aarch64eb #define helper_gvec_shr64i helper_gvec_shr64i_aarch64eb +#define helper_gvec_shr64v helper_gvec_shr64v_aarch64eb #define helper_gvec_smax8 helper_gvec_smax8_aarch64eb #define helper_gvec_smax16 helper_gvec_smax16_aarch64eb #define helper_gvec_smax32 helper_gvec_smax32_aarch64eb @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_aarch64eb #define tcg_gen_gvec_ori tcg_gen_gvec_ori_aarch64eb #define tcg_gen_gvec_ors tcg_gen_gvec_ors_aarch64eb +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_aarch64eb +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_aarch64eb +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_aarch64eb +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_aarch64eb #define tcg_gen_gvec_sari tcg_gen_gvec_sari_aarch64eb +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_aarch64eb +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_aarch64eb +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_aarch64eb +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_aarch64eb +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_aarch64eb #define tcg_gen_gvec_shli tcg_gen_gvec_shli_aarch64eb +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_aarch64eb #define tcg_gen_gvec_shri tcg_gen_gvec_shri_aarch64eb +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_aarch64eb +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_aarch64eb +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_aarch64eb +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_aarch64eb +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_aarch64eb #define tcg_gen_gvec_smax tcg_gen_gvec_smax_aarch64eb #define tcg_gen_gvec_smin tcg_gen_gvec_smin_aarch64eb #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_aarch64eb @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_aarch64eb #define tcg_gen_sari_i64 tcg_gen_sari_i64_aarch64eb #define tcg_gen_sari_vec tcg_gen_sari_vec_aarch64eb +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_aarch64eb #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_aarch64eb #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_aarch64eb #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_aarch64eb @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_aarch64eb #define tcg_gen_shli_i64 tcg_gen_shli_i64_aarch64eb #define tcg_gen_shli_vec tcg_gen_shli_vec_aarch64eb +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_aarch64eb #define tcg_gen_shr_i32 tcg_gen_shr_i32_aarch64eb #define tcg_gen_shr_i64 tcg_gen_shr_i64_aarch64eb #define tcg_gen_shri_i32 tcg_gen_shri_i32_aarch64eb #define tcg_gen_shri_i64 tcg_gen_shri_i64_aarch64eb #define tcg_gen_shri_vec tcg_gen_shri_vec_aarch64eb +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_aarch64eb #define tcg_gen_smax_i32 tcg_gen_smax_i32_aarch64eb #define tcg_gen_smax_i64 tcg_gen_smax_i64_aarch64eb #define tcg_gen_smax_vec tcg_gen_smax_vec_aarch64eb diff --git a/qemu/accel/tcg/tcg-runtime-gvec.c b/qemu/accel/tcg/tcg-runtime-gvec.c index e2c6f242..2152fb69 100644 --- a/qemu/accel/tcg/tcg-runtime-gvec.c +++ b/qemu/accel/tcg/tcg-runtime-gvec.c @@ -725,6 +725,150 @@ void HELPER(gvec_sar64i)(void *d, void *a, uint32_t desc) clear_high(d, oprsz, desc); } +void HELPER(gvec_shl8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { + uint8_t sh = *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { + uint8_t sh = *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { + uint8_t sh = *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shl64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { + uint8_t sh = *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) << sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint8_t)) { + uint8_t sh = *(uint8_t *)(b + i) & 7; + *(uint8_t *)(d + i) = *(uint8_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint16_t)) { + uint8_t sh = *(uint16_t *)(b + i) & 15; + *(uint16_t *)(d + i) = *(uint16_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint32_t)) { + uint8_t sh = *(uint32_t *)(b + i) & 31; + *(uint32_t *)(d + i) = *(uint32_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_shr64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(uint64_t)) { + uint8_t sh = *(uint64_t *)(b + i) & 63; + *(uint64_t *)(d + i) = *(uint64_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar8v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(vec8)) { + uint8_t sh = *(uint8_t *)(b + i) & 7; + *(int8_t *)(d + i) = *(int8_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar16v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(int16_t)) { + uint8_t sh = *(uint16_t *)(b + i) & 15; + *(int16_t *)(d + i) = *(int16_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar32v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(vec32)) { + uint8_t sh = *(uint32_t *)(b + i) & 31; + *(int32_t *)(d + i) = *(int32_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + +void HELPER(gvec_sar64v)(void *d, void *a, void *b, uint32_t desc) +{ + intptr_t oprsz = simd_oprsz(desc); + intptr_t i; + + for (i = 0; i < oprsz; i += sizeof(vec64)) { + uint8_t sh = *(uint64_t *)(b + i) & 63; + *(int64_t *)(d + i) = *(int64_t *)(a + i) >> sh; + } + clear_high(d, oprsz, desc); +} + /* If vectors are enabled, the compiler fills in -1 for true. Otherwise, we must take care of this by hand. */ #ifdef CONFIG_VECTOR16 diff --git a/qemu/accel/tcg/tcg-runtime.h b/qemu/accel/tcg/tcg-runtime.h index dfe32562..ed3ce5fd 100644 --- a/qemu/accel/tcg/tcg-runtime.h +++ b/qemu/accel/tcg/tcg-runtime.h @@ -254,6 +254,21 @@ DEF_HELPER_FLAGS_3(gvec_sar16i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar32i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) DEF_HELPER_FLAGS_3(gvec_sar64i, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shl64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_shr8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_shr64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(gvec_sar8v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar16v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar32v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_4(gvec_sar64v, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_eq8, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq16, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_eq32, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/qemu/arm.h b/qemu/arm.h index f2519224..1c47a570 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_arm #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_arm #define helper_gvec_sar8i helper_gvec_sar8i_arm +#define helper_gvec_sar8v helper_gvec_sar8v_arm #define helper_gvec_sar16i helper_gvec_sar16i_arm +#define helper_gvec_sar16v helper_gvec_sar16v_arm #define helper_gvec_sar32i helper_gvec_sar32i_arm +#define helper_gvec_sar32v helper_gvec_sar32v_arm #define helper_gvec_sar64i helper_gvec_sar64i_arm +#define helper_gvec_sar64v helper_gvec_sar64v_arm #define helper_gvec_sdot_b helper_gvec_sdot_b_arm #define helper_gvec_sdot_h helper_gvec_sdot_h_arm #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_arm #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_arm #define helper_gvec_shl8i helper_gvec_shl8i_arm +#define helper_gvec_shl8v helper_gvec_shl8v_arm #define helper_gvec_shl16i helper_gvec_shl16i_arm +#define helper_gvec_shl16v helper_gvec_shl16v_arm #define helper_gvec_shl32i helper_gvec_shl32i_arm +#define helper_gvec_shl32v helper_gvec_shl32v_arm #define helper_gvec_shl64i helper_gvec_shl64i_arm +#define helper_gvec_shl64v helper_gvec_shl64v_arm #define helper_gvec_shr8i helper_gvec_shr8i_arm +#define helper_gvec_shr8v helper_gvec_shr8v_arm #define helper_gvec_shr16i helper_gvec_shr16i_arm +#define helper_gvec_shr16v helper_gvec_shr16v_arm #define helper_gvec_shr32i helper_gvec_shr32i_arm +#define helper_gvec_shr32v helper_gvec_shr32v_arm #define helper_gvec_shr64i helper_gvec_shr64i_arm +#define helper_gvec_shr64v helper_gvec_shr64v_arm #define helper_gvec_smax8 helper_gvec_smax8_arm #define helper_gvec_smax16 helper_gvec_smax16_arm #define helper_gvec_smax32 helper_gvec_smax32_arm @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_arm #define tcg_gen_gvec_ori tcg_gen_gvec_ori_arm #define tcg_gen_gvec_ors tcg_gen_gvec_ors_arm +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_arm +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_arm +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_arm +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_arm #define tcg_gen_gvec_sari tcg_gen_gvec_sari_arm +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_arm +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_arm +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_arm +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_arm +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_arm #define tcg_gen_gvec_shli tcg_gen_gvec_shli_arm +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_arm #define tcg_gen_gvec_shri tcg_gen_gvec_shri_arm +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_arm +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_arm +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_arm +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_arm +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_arm #define tcg_gen_gvec_smax tcg_gen_gvec_smax_arm #define tcg_gen_gvec_smin tcg_gen_gvec_smin_arm #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_arm @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_arm #define tcg_gen_sari_i64 tcg_gen_sari_i64_arm #define tcg_gen_sari_vec tcg_gen_sari_vec_arm +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_arm #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_arm #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_arm #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_arm @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_arm #define tcg_gen_shli_i64 tcg_gen_shli_i64_arm #define tcg_gen_shli_vec tcg_gen_shli_vec_arm +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_arm #define tcg_gen_shr_i32 tcg_gen_shr_i32_arm #define tcg_gen_shr_i64 tcg_gen_shr_i64_arm #define tcg_gen_shri_i32 tcg_gen_shri_i32_arm #define tcg_gen_shri_i64 tcg_gen_shri_i64_arm #define tcg_gen_shri_vec tcg_gen_shri_vec_arm +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_arm #define tcg_gen_smax_i32 tcg_gen_smax_i32_arm #define tcg_gen_smax_i64 tcg_gen_smax_i64_arm #define tcg_gen_smax_vec tcg_gen_smax_vec_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 6128e7ca..6f40df4e 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_armeb #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_armeb #define helper_gvec_sar8i helper_gvec_sar8i_armeb +#define helper_gvec_sar8v helper_gvec_sar8v_armeb #define helper_gvec_sar16i helper_gvec_sar16i_armeb +#define helper_gvec_sar16v helper_gvec_sar16v_armeb #define helper_gvec_sar32i helper_gvec_sar32i_armeb +#define helper_gvec_sar32v helper_gvec_sar32v_armeb #define helper_gvec_sar64i helper_gvec_sar64i_armeb +#define helper_gvec_sar64v helper_gvec_sar64v_armeb #define helper_gvec_sdot_b helper_gvec_sdot_b_armeb #define helper_gvec_sdot_h helper_gvec_sdot_h_armeb #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_armeb #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_armeb #define helper_gvec_shl8i helper_gvec_shl8i_armeb +#define helper_gvec_shl8v helper_gvec_shl8v_armeb #define helper_gvec_shl16i helper_gvec_shl16i_armeb +#define helper_gvec_shl16v helper_gvec_shl16v_armeb #define helper_gvec_shl32i helper_gvec_shl32i_armeb +#define helper_gvec_shl32v helper_gvec_shl32v_armeb #define helper_gvec_shl64i helper_gvec_shl64i_armeb +#define helper_gvec_shl64v helper_gvec_shl64v_armeb #define helper_gvec_shr8i helper_gvec_shr8i_armeb +#define helper_gvec_shr8v helper_gvec_shr8v_armeb #define helper_gvec_shr16i helper_gvec_shr16i_armeb +#define helper_gvec_shr16v helper_gvec_shr16v_armeb #define helper_gvec_shr32i helper_gvec_shr32i_armeb +#define helper_gvec_shr32v helper_gvec_shr32v_armeb #define helper_gvec_shr64i helper_gvec_shr64i_armeb +#define helper_gvec_shr64v helper_gvec_shr64v_armeb #define helper_gvec_smax8 helper_gvec_smax8_armeb #define helper_gvec_smax16 helper_gvec_smax16_armeb #define helper_gvec_smax32 helper_gvec_smax32_armeb @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_armeb #define tcg_gen_gvec_ori tcg_gen_gvec_ori_armeb #define tcg_gen_gvec_ors tcg_gen_gvec_ors_armeb +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_armeb +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_armeb +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_armeb +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_armeb #define tcg_gen_gvec_sari tcg_gen_gvec_sari_armeb +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_armeb +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_armeb +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_armeb +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_armeb +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_armeb #define tcg_gen_gvec_shli tcg_gen_gvec_shli_armeb +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_armeb #define tcg_gen_gvec_shri tcg_gen_gvec_shri_armeb +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_armeb +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_armeb +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_armeb +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_armeb +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_armeb #define tcg_gen_gvec_smax tcg_gen_gvec_smax_armeb #define tcg_gen_gvec_smin tcg_gen_gvec_smin_armeb #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_armeb @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_armeb #define tcg_gen_sari_i64 tcg_gen_sari_i64_armeb #define tcg_gen_sari_vec tcg_gen_sari_vec_armeb +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_armeb #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_armeb #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_armeb #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_armeb @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_armeb #define tcg_gen_shli_i64 tcg_gen_shli_i64_armeb #define tcg_gen_shli_vec tcg_gen_shli_vec_armeb +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_armeb #define tcg_gen_shr_i32 tcg_gen_shr_i32_armeb #define tcg_gen_shr_i64 tcg_gen_shr_i64_armeb #define tcg_gen_shri_i32 tcg_gen_shri_i32_armeb #define tcg_gen_shri_i64 tcg_gen_shri_i64_armeb #define tcg_gen_shri_vec tcg_gen_shri_vec_armeb +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_armeb #define tcg_gen_smax_i32 tcg_gen_smax_i32_armeb #define tcg_gen_smax_i64 tcg_gen_smax_i64_armeb #define tcg_gen_smax_vec tcg_gen_smax_vec_armeb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index d7e13ce9..20cd473b 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -1219,21 +1219,33 @@ symbols = ( 'helper_gvec_qrdmlsh_s16', 'helper_gvec_qrdmlsh_s32', 'helper_gvec_sar8i', + 'helper_gvec_sar8v', 'helper_gvec_sar16i', + 'helper_gvec_sar16v', 'helper_gvec_sar32i', + 'helper_gvec_sar32v', 'helper_gvec_sar64i', + 'helper_gvec_sar64v', 'helper_gvec_sdot_b', 'helper_gvec_sdot_h', 'helper_gvec_sdot_idx_b', 'helper_gvec_sdot_idx_h', 'helper_gvec_shl8i', + 'helper_gvec_shl8v', 'helper_gvec_shl16i', + 'helper_gvec_shl16v', 'helper_gvec_shl32i', + 'helper_gvec_shl32v', 'helper_gvec_shl64i', + 'helper_gvec_shl64v', 'helper_gvec_shr8i', + 'helper_gvec_shr8v', 'helper_gvec_shr16i', + 'helper_gvec_shr16v', 'helper_gvec_shr32i', + 'helper_gvec_shr32v', 'helper_gvec_shr64i', + 'helper_gvec_shr64v', 'helper_gvec_smax8', 'helper_gvec_smax16', 'helper_gvec_smax32', @@ -2895,9 +2907,24 @@ symbols = ( 'tcg_gen_gvec_orc', 'tcg_gen_gvec_ori', 'tcg_gen_gvec_ors', + 'tcg_gen_gvec_sar8v', + 'tcg_gen_gvec_sar16v', + 'tcg_gen_gvec_sar32v', + 'tcg_gen_gvec_sar64v', 'tcg_gen_gvec_sari', + 'tcg_gen_gvec_sarv', + 'tcg_gen_gvec_shl8v', + 'tcg_gen_gvec_shl16v', + 'tcg_gen_gvec_shl32v', + 'tcg_gen_gvec_shl64v', 'tcg_gen_gvec_shli', + 'tcg_gen_gvec_shlv', 'tcg_gen_gvec_shri', + 'tcg_gen_gvec_shrv', + 'tcg_gen_gvec_shr8v', + 'tcg_gen_gvec_shr16v', + 'tcg_gen_gvec_shr32v', + 'tcg_gen_gvec_shr64v', 'tcg_gen_gvec_smax', 'tcg_gen_gvec_smin', 'tcg_gen_gvec_ssadd', @@ -3009,6 +3036,7 @@ symbols = ( 'tcg_gen_sari_i32', 'tcg_gen_sari_i64', 'tcg_gen_sari_vec', + 'tcg_gen_sarv_vec', 'tcg_gen_setcond_i32', 'tcg_gen_setcond_i64', 'tcg_gen_setcondi_i32', @@ -3021,11 +3049,13 @@ symbols = ( 'tcg_gen_shli_i32', 'tcg_gen_shli_i64', 'tcg_gen_shli_vec', + 'tcg_gen_shlv_vec', 'tcg_gen_shr_i32', 'tcg_gen_shr_i64', 'tcg_gen_shri_i32', 'tcg_gen_shri_i64', 'tcg_gen_shri_vec', + 'tcg_gen_shrv_vec', 'tcg_gen_smax_i32', 'tcg_gen_smax_i64', 'tcg_gen_smax_vec', diff --git a/qemu/m68k.h b/qemu/m68k.h index c20a3956..2231aa04 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_m68k #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_m68k #define helper_gvec_sar8i helper_gvec_sar8i_m68k +#define helper_gvec_sar8v helper_gvec_sar8v_m68k #define helper_gvec_sar16i helper_gvec_sar16i_m68k +#define helper_gvec_sar16v helper_gvec_sar16v_m68k #define helper_gvec_sar32i helper_gvec_sar32i_m68k +#define helper_gvec_sar32v helper_gvec_sar32v_m68k #define helper_gvec_sar64i helper_gvec_sar64i_m68k +#define helper_gvec_sar64v helper_gvec_sar64v_m68k #define helper_gvec_sdot_b helper_gvec_sdot_b_m68k #define helper_gvec_sdot_h helper_gvec_sdot_h_m68k #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_m68k #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_m68k #define helper_gvec_shl8i helper_gvec_shl8i_m68k +#define helper_gvec_shl8v helper_gvec_shl8v_m68k #define helper_gvec_shl16i helper_gvec_shl16i_m68k +#define helper_gvec_shl16v helper_gvec_shl16v_m68k #define helper_gvec_shl32i helper_gvec_shl32i_m68k +#define helper_gvec_shl32v helper_gvec_shl32v_m68k #define helper_gvec_shl64i helper_gvec_shl64i_m68k +#define helper_gvec_shl64v helper_gvec_shl64v_m68k #define helper_gvec_shr8i helper_gvec_shr8i_m68k +#define helper_gvec_shr8v helper_gvec_shr8v_m68k #define helper_gvec_shr16i helper_gvec_shr16i_m68k +#define helper_gvec_shr16v helper_gvec_shr16v_m68k #define helper_gvec_shr32i helper_gvec_shr32i_m68k +#define helper_gvec_shr32v helper_gvec_shr32v_m68k #define helper_gvec_shr64i helper_gvec_shr64i_m68k +#define helper_gvec_shr64v helper_gvec_shr64v_m68k #define helper_gvec_smax8 helper_gvec_smax8_m68k #define helper_gvec_smax16 helper_gvec_smax16_m68k #define helper_gvec_smax32 helper_gvec_smax32_m68k @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_m68k #define tcg_gen_gvec_ori tcg_gen_gvec_ori_m68k #define tcg_gen_gvec_ors tcg_gen_gvec_ors_m68k +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_m68k +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_m68k +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_m68k +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_m68k #define tcg_gen_gvec_sari tcg_gen_gvec_sari_m68k +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_m68k +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_m68k +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_m68k +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_m68k +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_m68k #define tcg_gen_gvec_shli tcg_gen_gvec_shli_m68k +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_m68k #define tcg_gen_gvec_shri tcg_gen_gvec_shri_m68k +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_m68k +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_m68k +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_m68k +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_m68k +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_m68k #define tcg_gen_gvec_smax tcg_gen_gvec_smax_m68k #define tcg_gen_gvec_smin tcg_gen_gvec_smin_m68k #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_m68k @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_m68k #define tcg_gen_sari_i64 tcg_gen_sari_i64_m68k #define tcg_gen_sari_vec tcg_gen_sari_vec_m68k +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_m68k #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_m68k #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_m68k #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_m68k @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_m68k #define tcg_gen_shli_i64 tcg_gen_shli_i64_m68k #define tcg_gen_shli_vec tcg_gen_shli_vec_m68k +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_m68k #define tcg_gen_shr_i32 tcg_gen_shr_i32_m68k #define tcg_gen_shr_i64 tcg_gen_shr_i64_m68k #define tcg_gen_shri_i32 tcg_gen_shri_i32_m68k #define tcg_gen_shri_i64 tcg_gen_shri_i64_m68k #define tcg_gen_shri_vec tcg_gen_shri_vec_m68k +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_m68k #define tcg_gen_smax_i32 tcg_gen_smax_i32_m68k #define tcg_gen_smax_i64 tcg_gen_smax_i64_m68k #define tcg_gen_smax_vec tcg_gen_smax_vec_m68k diff --git a/qemu/mips.h b/qemu/mips.h index 8e6a70c3..c3cce17f 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips #define helper_gvec_sar8i helper_gvec_sar8i_mips +#define helper_gvec_sar8v helper_gvec_sar8v_mips #define helper_gvec_sar16i helper_gvec_sar16i_mips +#define helper_gvec_sar16v helper_gvec_sar16v_mips #define helper_gvec_sar32i helper_gvec_sar32i_mips +#define helper_gvec_sar32v helper_gvec_sar32v_mips #define helper_gvec_sar64i helper_gvec_sar64i_mips +#define helper_gvec_sar64v helper_gvec_sar64v_mips #define helper_gvec_sdot_b helper_gvec_sdot_b_mips #define helper_gvec_sdot_h helper_gvec_sdot_h_mips #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_mips #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_mips #define helper_gvec_shl8i helper_gvec_shl8i_mips +#define helper_gvec_shl8v helper_gvec_shl8v_mips #define helper_gvec_shl16i helper_gvec_shl16i_mips +#define helper_gvec_shl16v helper_gvec_shl16v_mips #define helper_gvec_shl32i helper_gvec_shl32i_mips +#define helper_gvec_shl32v helper_gvec_shl32v_mips #define helper_gvec_shl64i helper_gvec_shl64i_mips +#define helper_gvec_shl64v helper_gvec_shl64v_mips #define helper_gvec_shr8i helper_gvec_shr8i_mips +#define helper_gvec_shr8v helper_gvec_shr8v_mips #define helper_gvec_shr16i helper_gvec_shr16i_mips +#define helper_gvec_shr16v helper_gvec_shr16v_mips #define helper_gvec_shr32i helper_gvec_shr32i_mips +#define helper_gvec_shr32v helper_gvec_shr32v_mips #define helper_gvec_shr64i helper_gvec_shr64i_mips +#define helper_gvec_shr64v helper_gvec_shr64v_mips #define helper_gvec_smax8 helper_gvec_smax8_mips #define helper_gvec_smax16 helper_gvec_smax16_mips #define helper_gvec_smax32 helper_gvec_smax32_mips @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips #define tcg_gen_gvec_ori tcg_gen_gvec_ori_mips #define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips #define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips #define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips #define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_mips +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_mips #define tcg_gen_gvec_smax tcg_gen_gvec_smax_mips #define tcg_gen_gvec_smin tcg_gen_gvec_smin_mips #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips #define tcg_gen_sari_i64 tcg_gen_sari_i64_mips #define tcg_gen_sari_vec tcg_gen_sari_vec_mips +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips #define tcg_gen_shli_i64 tcg_gen_shli_i64_mips #define tcg_gen_shli_vec tcg_gen_shli_vec_mips +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips #define tcg_gen_shr_i32 tcg_gen_shr_i32_mips #define tcg_gen_shr_i64 tcg_gen_shr_i64_mips #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips #define tcg_gen_shri_vec tcg_gen_shri_vec_mips +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips #define tcg_gen_smax_i32 tcg_gen_smax_i32_mips #define tcg_gen_smax_i64 tcg_gen_smax_i64_mips #define tcg_gen_smax_vec tcg_gen_smax_vec_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index f9750173..a3248a59 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips64 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips64 #define helper_gvec_sar8i helper_gvec_sar8i_mips64 +#define helper_gvec_sar8v helper_gvec_sar8v_mips64 #define helper_gvec_sar16i helper_gvec_sar16i_mips64 +#define helper_gvec_sar16v helper_gvec_sar16v_mips64 #define helper_gvec_sar32i helper_gvec_sar32i_mips64 +#define helper_gvec_sar32v helper_gvec_sar32v_mips64 #define helper_gvec_sar64i helper_gvec_sar64i_mips64 +#define helper_gvec_sar64v helper_gvec_sar64v_mips64 #define helper_gvec_sdot_b helper_gvec_sdot_b_mips64 #define helper_gvec_sdot_h helper_gvec_sdot_h_mips64 #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_mips64 #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_mips64 #define helper_gvec_shl8i helper_gvec_shl8i_mips64 +#define helper_gvec_shl8v helper_gvec_shl8v_mips64 #define helper_gvec_shl16i helper_gvec_shl16i_mips64 +#define helper_gvec_shl16v helper_gvec_shl16v_mips64 #define helper_gvec_shl32i helper_gvec_shl32i_mips64 +#define helper_gvec_shl32v helper_gvec_shl32v_mips64 #define helper_gvec_shl64i helper_gvec_shl64i_mips64 +#define helper_gvec_shl64v helper_gvec_shl64v_mips64 #define helper_gvec_shr8i helper_gvec_shr8i_mips64 +#define helper_gvec_shr8v helper_gvec_shr8v_mips64 #define helper_gvec_shr16i helper_gvec_shr16i_mips64 +#define helper_gvec_shr16v helper_gvec_shr16v_mips64 #define helper_gvec_shr32i helper_gvec_shr32i_mips64 +#define helper_gvec_shr32v helper_gvec_shr32v_mips64 #define helper_gvec_shr64i helper_gvec_shr64i_mips64 +#define helper_gvec_shr64v helper_gvec_shr64v_mips64 #define helper_gvec_smax8 helper_gvec_smax8_mips64 #define helper_gvec_smax16 helper_gvec_smax16_mips64 #define helper_gvec_smax32 helper_gvec_smax32_mips64 @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64 #define tcg_gen_gvec_ori tcg_gen_gvec_ori_mips64 #define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips64 +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips64 +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips64 +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64 +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64 +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips64 +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips64 +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips64 +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips64 +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64 +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64 +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips64 +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips64 +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips64 +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_mips64 +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_mips64 #define tcg_gen_gvec_smax tcg_gen_gvec_smax_mips64 #define tcg_gen_gvec_smin tcg_gen_gvec_smin_mips64 #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips64 @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64 #define tcg_gen_sari_vec tcg_gen_sari_vec_mips64 +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64 #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64 @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_mips64 #define tcg_gen_shli_vec tcg_gen_shli_vec_mips64 +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_mips64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_mips64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64 #define tcg_gen_shri_vec tcg_gen_shri_vec_mips64 +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64 #define tcg_gen_smax_vec tcg_gen_smax_vec_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 7ca488d6..813c9f4b 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mips64el #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mips64el #define helper_gvec_sar8i helper_gvec_sar8i_mips64el +#define helper_gvec_sar8v helper_gvec_sar8v_mips64el #define helper_gvec_sar16i helper_gvec_sar16i_mips64el +#define helper_gvec_sar16v helper_gvec_sar16v_mips64el #define helper_gvec_sar32i helper_gvec_sar32i_mips64el +#define helper_gvec_sar32v helper_gvec_sar32v_mips64el #define helper_gvec_sar64i helper_gvec_sar64i_mips64el +#define helper_gvec_sar64v helper_gvec_sar64v_mips64el #define helper_gvec_sdot_b helper_gvec_sdot_b_mips64el #define helper_gvec_sdot_h helper_gvec_sdot_h_mips64el #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_mips64el #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_mips64el #define helper_gvec_shl8i helper_gvec_shl8i_mips64el +#define helper_gvec_shl8v helper_gvec_shl8v_mips64el #define helper_gvec_shl16i helper_gvec_shl16i_mips64el +#define helper_gvec_shl16v helper_gvec_shl16v_mips64el #define helper_gvec_shl32i helper_gvec_shl32i_mips64el +#define helper_gvec_shl32v helper_gvec_shl32v_mips64el #define helper_gvec_shl64i helper_gvec_shl64i_mips64el +#define helper_gvec_shl64v helper_gvec_shl64v_mips64el #define helper_gvec_shr8i helper_gvec_shr8i_mips64el +#define helper_gvec_shr8v helper_gvec_shr8v_mips64el #define helper_gvec_shr16i helper_gvec_shr16i_mips64el +#define helper_gvec_shr16v helper_gvec_shr16v_mips64el #define helper_gvec_shr32i helper_gvec_shr32i_mips64el +#define helper_gvec_shr32v helper_gvec_shr32v_mips64el #define helper_gvec_shr64i helper_gvec_shr64i_mips64el +#define helper_gvec_shr64v helper_gvec_shr64v_mips64el #define helper_gvec_smax8 helper_gvec_smax8_mips64el #define helper_gvec_smax16 helper_gvec_smax16_mips64el #define helper_gvec_smax32 helper_gvec_smax32_mips64el @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_mips64el #define tcg_gen_gvec_ori tcg_gen_gvec_ori_mips64el #define tcg_gen_gvec_ors tcg_gen_gvec_ors_mips64el +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mips64el +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mips64el +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mips64el +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mips64el #define tcg_gen_gvec_sari tcg_gen_gvec_sari_mips64el +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mips64el +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mips64el +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mips64el +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mips64el +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mips64el #define tcg_gen_gvec_shli tcg_gen_gvec_shli_mips64el +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mips64el #define tcg_gen_gvec_shri tcg_gen_gvec_shri_mips64el +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mips64el +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mips64el +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mips64el +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_mips64el +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_mips64el #define tcg_gen_gvec_smax tcg_gen_gvec_smax_mips64el #define tcg_gen_gvec_smin tcg_gen_gvec_smin_mips64el #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mips64el @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_mips64el #define tcg_gen_sari_i64 tcg_gen_sari_i64_mips64el #define tcg_gen_sari_vec tcg_gen_sari_vec_mips64el +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_mips64el #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mips64el #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mips64el #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mips64el @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_mips64el #define tcg_gen_shli_i64 tcg_gen_shli_i64_mips64el #define tcg_gen_shli_vec tcg_gen_shli_vec_mips64el +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_mips64el #define tcg_gen_shr_i32 tcg_gen_shr_i32_mips64el #define tcg_gen_shr_i64 tcg_gen_shr_i64_mips64el #define tcg_gen_shri_i32 tcg_gen_shri_i32_mips64el #define tcg_gen_shri_i64 tcg_gen_shri_i64_mips64el #define tcg_gen_shri_vec tcg_gen_shri_vec_mips64el +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_mips64el #define tcg_gen_smax_i32 tcg_gen_smax_i32_mips64el #define tcg_gen_smax_i64 tcg_gen_smax_i64_mips64el #define tcg_gen_smax_vec tcg_gen_smax_vec_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 15ccd06c..46a17a70 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_mipsel #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_mipsel #define helper_gvec_sar8i helper_gvec_sar8i_mipsel +#define helper_gvec_sar8v helper_gvec_sar8v_mipsel #define helper_gvec_sar16i helper_gvec_sar16i_mipsel +#define helper_gvec_sar16v helper_gvec_sar16v_mipsel #define helper_gvec_sar32i helper_gvec_sar32i_mipsel +#define helper_gvec_sar32v helper_gvec_sar32v_mipsel #define helper_gvec_sar64i helper_gvec_sar64i_mipsel +#define helper_gvec_sar64v helper_gvec_sar64v_mipsel #define helper_gvec_sdot_b helper_gvec_sdot_b_mipsel #define helper_gvec_sdot_h helper_gvec_sdot_h_mipsel #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_mipsel #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_mipsel #define helper_gvec_shl8i helper_gvec_shl8i_mipsel +#define helper_gvec_shl8v helper_gvec_shl8v_mipsel #define helper_gvec_shl16i helper_gvec_shl16i_mipsel +#define helper_gvec_shl16v helper_gvec_shl16v_mipsel #define helper_gvec_shl32i helper_gvec_shl32i_mipsel +#define helper_gvec_shl32v helper_gvec_shl32v_mipsel #define helper_gvec_shl64i helper_gvec_shl64i_mipsel +#define helper_gvec_shl64v helper_gvec_shl64v_mipsel #define helper_gvec_shr8i helper_gvec_shr8i_mipsel +#define helper_gvec_shr8v helper_gvec_shr8v_mipsel #define helper_gvec_shr16i helper_gvec_shr16i_mipsel +#define helper_gvec_shr16v helper_gvec_shr16v_mipsel #define helper_gvec_shr32i helper_gvec_shr32i_mipsel +#define helper_gvec_shr32v helper_gvec_shr32v_mipsel #define helper_gvec_shr64i helper_gvec_shr64i_mipsel +#define helper_gvec_shr64v helper_gvec_shr64v_mipsel #define helper_gvec_smax8 helper_gvec_smax8_mipsel #define helper_gvec_smax16 helper_gvec_smax16_mipsel #define helper_gvec_smax32 helper_gvec_smax32_mipsel @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_mipsel #define tcg_gen_gvec_ori tcg_gen_gvec_ori_mipsel #define tcg_gen_gvec_ors tcg_gen_gvec_ors_mipsel +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_mipsel +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_mipsel +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_mipsel +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_mipsel #define tcg_gen_gvec_sari tcg_gen_gvec_sari_mipsel +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_mipsel +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_mipsel +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_mipsel +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_mipsel +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_mipsel #define tcg_gen_gvec_shli tcg_gen_gvec_shli_mipsel +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_mipsel #define tcg_gen_gvec_shri tcg_gen_gvec_shri_mipsel +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_mipsel +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_mipsel +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_mipsel +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_mipsel +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_mipsel #define tcg_gen_gvec_smax tcg_gen_gvec_smax_mipsel #define tcg_gen_gvec_smin tcg_gen_gvec_smin_mipsel #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_mipsel @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_mipsel #define tcg_gen_sari_i64 tcg_gen_sari_i64_mipsel #define tcg_gen_sari_vec tcg_gen_sari_vec_mipsel +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_mipsel #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_mipsel #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_mipsel #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_mipsel @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_mipsel #define tcg_gen_shli_i64 tcg_gen_shli_i64_mipsel #define tcg_gen_shli_vec tcg_gen_shli_vec_mipsel +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_mipsel #define tcg_gen_shr_i32 tcg_gen_shr_i32_mipsel #define tcg_gen_shr_i64 tcg_gen_shr_i64_mipsel #define tcg_gen_shri_i32 tcg_gen_shri_i32_mipsel #define tcg_gen_shri_i64 tcg_gen_shri_i64_mipsel #define tcg_gen_shri_vec tcg_gen_shri_vec_mipsel +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_mipsel #define tcg_gen_smax_i32 tcg_gen_smax_i32_mipsel #define tcg_gen_smax_i64 tcg_gen_smax_i64_mipsel #define tcg_gen_smax_vec tcg_gen_smax_vec_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index e409a4a8..e9822ba1 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_powerpc #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_powerpc #define helper_gvec_sar8i helper_gvec_sar8i_powerpc +#define helper_gvec_sar8v helper_gvec_sar8v_powerpc #define helper_gvec_sar16i helper_gvec_sar16i_powerpc +#define helper_gvec_sar16v helper_gvec_sar16v_powerpc #define helper_gvec_sar32i helper_gvec_sar32i_powerpc +#define helper_gvec_sar32v helper_gvec_sar32v_powerpc #define helper_gvec_sar64i helper_gvec_sar64i_powerpc +#define helper_gvec_sar64v helper_gvec_sar64v_powerpc #define helper_gvec_sdot_b helper_gvec_sdot_b_powerpc #define helper_gvec_sdot_h helper_gvec_sdot_h_powerpc #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_powerpc #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_powerpc #define helper_gvec_shl8i helper_gvec_shl8i_powerpc +#define helper_gvec_shl8v helper_gvec_shl8v_powerpc #define helper_gvec_shl16i helper_gvec_shl16i_powerpc +#define helper_gvec_shl16v helper_gvec_shl16v_powerpc #define helper_gvec_shl32i helper_gvec_shl32i_powerpc +#define helper_gvec_shl32v helper_gvec_shl32v_powerpc #define helper_gvec_shl64i helper_gvec_shl64i_powerpc +#define helper_gvec_shl64v helper_gvec_shl64v_powerpc #define helper_gvec_shr8i helper_gvec_shr8i_powerpc +#define helper_gvec_shr8v helper_gvec_shr8v_powerpc #define helper_gvec_shr16i helper_gvec_shr16i_powerpc +#define helper_gvec_shr16v helper_gvec_shr16v_powerpc #define helper_gvec_shr32i helper_gvec_shr32i_powerpc +#define helper_gvec_shr32v helper_gvec_shr32v_powerpc #define helper_gvec_shr64i helper_gvec_shr64i_powerpc +#define helper_gvec_shr64v helper_gvec_shr64v_powerpc #define helper_gvec_smax8 helper_gvec_smax8_powerpc #define helper_gvec_smax16 helper_gvec_smax16_powerpc #define helper_gvec_smax32 helper_gvec_smax32_powerpc @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_powerpc #define tcg_gen_gvec_ori tcg_gen_gvec_ori_powerpc #define tcg_gen_gvec_ors tcg_gen_gvec_ors_powerpc +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_powerpc +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_powerpc +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_powerpc +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_powerpc #define tcg_gen_gvec_sari tcg_gen_gvec_sari_powerpc +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_powerpc +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_powerpc +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_powerpc +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_powerpc +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_powerpc #define tcg_gen_gvec_shli tcg_gen_gvec_shli_powerpc +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_powerpc #define tcg_gen_gvec_shri tcg_gen_gvec_shri_powerpc +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_powerpc +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_powerpc +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_powerpc +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_powerpc +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_powerpc #define tcg_gen_gvec_smax tcg_gen_gvec_smax_powerpc #define tcg_gen_gvec_smin tcg_gen_gvec_smin_powerpc #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_powerpc @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_powerpc #define tcg_gen_sari_i64 tcg_gen_sari_i64_powerpc #define tcg_gen_sari_vec tcg_gen_sari_vec_powerpc +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_powerpc #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_powerpc #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_powerpc #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_powerpc @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_powerpc #define tcg_gen_shli_i64 tcg_gen_shli_i64_powerpc #define tcg_gen_shli_vec tcg_gen_shli_vec_powerpc +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_powerpc #define tcg_gen_shr_i32 tcg_gen_shr_i32_powerpc #define tcg_gen_shr_i64 tcg_gen_shr_i64_powerpc #define tcg_gen_shri_i32 tcg_gen_shri_i32_powerpc #define tcg_gen_shri_i64 tcg_gen_shri_i64_powerpc #define tcg_gen_shri_vec tcg_gen_shri_vec_powerpc +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_powerpc #define tcg_gen_smax_i32 tcg_gen_smax_i32_powerpc #define tcg_gen_smax_i64 tcg_gen_smax_i64_powerpc #define tcg_gen_smax_vec tcg_gen_smax_vec_powerpc diff --git a/qemu/riscv32.h b/qemu/riscv32.h index f50d6b49..08f45b0c 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv32 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_riscv32 #define helper_gvec_sar8i helper_gvec_sar8i_riscv32 +#define helper_gvec_sar8v helper_gvec_sar8v_riscv32 #define helper_gvec_sar16i helper_gvec_sar16i_riscv32 +#define helper_gvec_sar16v helper_gvec_sar16v_riscv32 #define helper_gvec_sar32i helper_gvec_sar32i_riscv32 +#define helper_gvec_sar32v helper_gvec_sar32v_riscv32 #define helper_gvec_sar64i helper_gvec_sar64i_riscv32 +#define helper_gvec_sar64v helper_gvec_sar64v_riscv32 #define helper_gvec_sdot_b helper_gvec_sdot_b_riscv32 #define helper_gvec_sdot_h helper_gvec_sdot_h_riscv32 #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_riscv32 #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_riscv32 #define helper_gvec_shl8i helper_gvec_shl8i_riscv32 +#define helper_gvec_shl8v helper_gvec_shl8v_riscv32 #define helper_gvec_shl16i helper_gvec_shl16i_riscv32 +#define helper_gvec_shl16v helper_gvec_shl16v_riscv32 #define helper_gvec_shl32i helper_gvec_shl32i_riscv32 +#define helper_gvec_shl32v helper_gvec_shl32v_riscv32 #define helper_gvec_shl64i helper_gvec_shl64i_riscv32 +#define helper_gvec_shl64v helper_gvec_shl64v_riscv32 #define helper_gvec_shr8i helper_gvec_shr8i_riscv32 +#define helper_gvec_shr8v helper_gvec_shr8v_riscv32 #define helper_gvec_shr16i helper_gvec_shr16i_riscv32 +#define helper_gvec_shr16v helper_gvec_shr16v_riscv32 #define helper_gvec_shr32i helper_gvec_shr32i_riscv32 +#define helper_gvec_shr32v helper_gvec_shr32v_riscv32 #define helper_gvec_shr64i helper_gvec_shr64i_riscv32 +#define helper_gvec_shr64v helper_gvec_shr64v_riscv32 #define helper_gvec_smax8 helper_gvec_smax8_riscv32 #define helper_gvec_smax16 helper_gvec_smax16_riscv32 #define helper_gvec_smax32 helper_gvec_smax32_riscv32 @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_riscv32 #define tcg_gen_gvec_ori tcg_gen_gvec_ori_riscv32 #define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv32 +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_riscv32 +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_riscv32 +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv32 +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_riscv32 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv32 +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_riscv32 +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_riscv32 +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_riscv32 +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_riscv32 +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_riscv32 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv32 +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_riscv32 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv32 +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_riscv32 +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_riscv32 +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_riscv32 +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_riscv32 +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_riscv32 #define tcg_gen_gvec_smax tcg_gen_gvec_smax_riscv32 #define tcg_gen_gvec_smin tcg_gen_gvec_smin_riscv32 #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_riscv32 @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv32 #define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv32 #define tcg_gen_sari_vec tcg_gen_sari_vec_riscv32 +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_riscv32 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv32 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv32 #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_riscv32 @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv32 #define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv32 #define tcg_gen_shli_vec tcg_gen_shli_vec_riscv32 +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_riscv32 #define tcg_gen_shr_i32 tcg_gen_shr_i32_riscv32 #define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv32 #define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv32 #define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv32 #define tcg_gen_shri_vec tcg_gen_shri_vec_riscv32 +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_riscv32 #define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv32 #define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv32 #define tcg_gen_smax_vec tcg_gen_smax_vec_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index 650ec7d3..9c831e59 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv64 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_riscv64 #define helper_gvec_sar8i helper_gvec_sar8i_riscv64 +#define helper_gvec_sar8v helper_gvec_sar8v_riscv64 #define helper_gvec_sar16i helper_gvec_sar16i_riscv64 +#define helper_gvec_sar16v helper_gvec_sar16v_riscv64 #define helper_gvec_sar32i helper_gvec_sar32i_riscv64 +#define helper_gvec_sar32v helper_gvec_sar32v_riscv64 #define helper_gvec_sar64i helper_gvec_sar64i_riscv64 +#define helper_gvec_sar64v helper_gvec_sar64v_riscv64 #define helper_gvec_sdot_b helper_gvec_sdot_b_riscv64 #define helper_gvec_sdot_h helper_gvec_sdot_h_riscv64 #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_riscv64 #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_riscv64 #define helper_gvec_shl8i helper_gvec_shl8i_riscv64 +#define helper_gvec_shl8v helper_gvec_shl8v_riscv64 #define helper_gvec_shl16i helper_gvec_shl16i_riscv64 +#define helper_gvec_shl16v helper_gvec_shl16v_riscv64 #define helper_gvec_shl32i helper_gvec_shl32i_riscv64 +#define helper_gvec_shl32v helper_gvec_shl32v_riscv64 #define helper_gvec_shl64i helper_gvec_shl64i_riscv64 +#define helper_gvec_shl64v helper_gvec_shl64v_riscv64 #define helper_gvec_shr8i helper_gvec_shr8i_riscv64 +#define helper_gvec_shr8v helper_gvec_shr8v_riscv64 #define helper_gvec_shr16i helper_gvec_shr16i_riscv64 +#define helper_gvec_shr16v helper_gvec_shr16v_riscv64 #define helper_gvec_shr32i helper_gvec_shr32i_riscv64 +#define helper_gvec_shr32v helper_gvec_shr32v_riscv64 #define helper_gvec_shr64i helper_gvec_shr64i_riscv64 +#define helper_gvec_shr64v helper_gvec_shr64v_riscv64 #define helper_gvec_smax8 helper_gvec_smax8_riscv64 #define helper_gvec_smax16 helper_gvec_smax16_riscv64 #define helper_gvec_smax32 helper_gvec_smax32_riscv64 @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_riscv64 #define tcg_gen_gvec_ori tcg_gen_gvec_ori_riscv64 #define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv64 +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_riscv64 +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_riscv64 +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_riscv64 +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_riscv64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv64 +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_riscv64 +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_riscv64 +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_riscv64 +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_riscv64 +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_riscv64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv64 +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_riscv64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv64 +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_riscv64 +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_riscv64 +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_riscv64 +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_riscv64 +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_riscv64 #define tcg_gen_gvec_smax tcg_gen_gvec_smax_riscv64 #define tcg_gen_gvec_smin tcg_gen_gvec_smin_riscv64 #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_riscv64 @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv64 #define tcg_gen_sari_vec tcg_gen_sari_vec_riscv64 +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_riscv64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv64 #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_riscv64 @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv64 #define tcg_gen_shli_vec tcg_gen_shli_vec_riscv64 +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_riscv64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_riscv64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv64 #define tcg_gen_shri_vec tcg_gen_shri_vec_riscv64 +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_riscv64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv64 #define tcg_gen_smax_vec tcg_gen_smax_vec_riscv64 diff --git a/qemu/sparc.h b/qemu/sparc.h index daf6ef06..35791c57 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_sparc #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_sparc #define helper_gvec_sar8i helper_gvec_sar8i_sparc +#define helper_gvec_sar8v helper_gvec_sar8v_sparc #define helper_gvec_sar16i helper_gvec_sar16i_sparc +#define helper_gvec_sar16v helper_gvec_sar16v_sparc #define helper_gvec_sar32i helper_gvec_sar32i_sparc +#define helper_gvec_sar32v helper_gvec_sar32v_sparc #define helper_gvec_sar64i helper_gvec_sar64i_sparc +#define helper_gvec_sar64v helper_gvec_sar64v_sparc #define helper_gvec_sdot_b helper_gvec_sdot_b_sparc #define helper_gvec_sdot_h helper_gvec_sdot_h_sparc #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_sparc #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_sparc #define helper_gvec_shl8i helper_gvec_shl8i_sparc +#define helper_gvec_shl8v helper_gvec_shl8v_sparc #define helper_gvec_shl16i helper_gvec_shl16i_sparc +#define helper_gvec_shl16v helper_gvec_shl16v_sparc #define helper_gvec_shl32i helper_gvec_shl32i_sparc +#define helper_gvec_shl32v helper_gvec_shl32v_sparc #define helper_gvec_shl64i helper_gvec_shl64i_sparc +#define helper_gvec_shl64v helper_gvec_shl64v_sparc #define helper_gvec_shr8i helper_gvec_shr8i_sparc +#define helper_gvec_shr8v helper_gvec_shr8v_sparc #define helper_gvec_shr16i helper_gvec_shr16i_sparc +#define helper_gvec_shr16v helper_gvec_shr16v_sparc #define helper_gvec_shr32i helper_gvec_shr32i_sparc +#define helper_gvec_shr32v helper_gvec_shr32v_sparc #define helper_gvec_shr64i helper_gvec_shr64i_sparc +#define helper_gvec_shr64v helper_gvec_shr64v_sparc #define helper_gvec_smax8 helper_gvec_smax8_sparc #define helper_gvec_smax16 helper_gvec_smax16_sparc #define helper_gvec_smax32 helper_gvec_smax32_sparc @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc #define tcg_gen_gvec_ori tcg_gen_gvec_ori_sparc #define tcg_gen_gvec_ors tcg_gen_gvec_ors_sparc +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_sparc +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_sparc +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_sparc #define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_sparc +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_sparc +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_sparc +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_sparc +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_sparc #define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_sparc #define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_sparc +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_sparc +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_sparc +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_sparc +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_sparc #define tcg_gen_gvec_smax tcg_gen_gvec_smax_sparc #define tcg_gen_gvec_smin tcg_gen_gvec_smin_sparc #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_sparc @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc #define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc #define tcg_gen_sari_vec tcg_gen_sari_vec_sparc +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_sparc #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc #define tcg_gen_shli_i64 tcg_gen_shli_i64_sparc #define tcg_gen_shli_vec tcg_gen_shli_vec_sparc +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_sparc #define tcg_gen_shr_i32 tcg_gen_shr_i32_sparc #define tcg_gen_shr_i64 tcg_gen_shr_i64_sparc #define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc #define tcg_gen_shri_vec tcg_gen_shri_vec_sparc +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_sparc #define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc #define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc #define tcg_gen_smax_vec tcg_gen_smax_vec_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 140af229..06417a02 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_sparc64 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_sparc64 #define helper_gvec_sar8i helper_gvec_sar8i_sparc64 +#define helper_gvec_sar8v helper_gvec_sar8v_sparc64 #define helper_gvec_sar16i helper_gvec_sar16i_sparc64 +#define helper_gvec_sar16v helper_gvec_sar16v_sparc64 #define helper_gvec_sar32i helper_gvec_sar32i_sparc64 +#define helper_gvec_sar32v helper_gvec_sar32v_sparc64 #define helper_gvec_sar64i helper_gvec_sar64i_sparc64 +#define helper_gvec_sar64v helper_gvec_sar64v_sparc64 #define helper_gvec_sdot_b helper_gvec_sdot_b_sparc64 #define helper_gvec_sdot_h helper_gvec_sdot_h_sparc64 #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_sparc64 #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_sparc64 #define helper_gvec_shl8i helper_gvec_shl8i_sparc64 +#define helper_gvec_shl8v helper_gvec_shl8v_sparc64 #define helper_gvec_shl16i helper_gvec_shl16i_sparc64 +#define helper_gvec_shl16v helper_gvec_shl16v_sparc64 #define helper_gvec_shl32i helper_gvec_shl32i_sparc64 +#define helper_gvec_shl32v helper_gvec_shl32v_sparc64 #define helper_gvec_shl64i helper_gvec_shl64i_sparc64 +#define helper_gvec_shl64v helper_gvec_shl64v_sparc64 #define helper_gvec_shr8i helper_gvec_shr8i_sparc64 +#define helper_gvec_shr8v helper_gvec_shr8v_sparc64 #define helper_gvec_shr16i helper_gvec_shr16i_sparc64 +#define helper_gvec_shr16v helper_gvec_shr16v_sparc64 #define helper_gvec_shr32i helper_gvec_shr32i_sparc64 +#define helper_gvec_shr32v helper_gvec_shr32v_sparc64 #define helper_gvec_shr64i helper_gvec_shr64i_sparc64 +#define helper_gvec_shr64v helper_gvec_shr64v_sparc64 #define helper_gvec_smax8 helper_gvec_smax8_sparc64 #define helper_gvec_smax16 helper_gvec_smax16_sparc64 #define helper_gvec_smax32 helper_gvec_smax32_sparc64 @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_sparc64 #define tcg_gen_gvec_ori tcg_gen_gvec_ori_sparc64 #define tcg_gen_gvec_ors tcg_gen_gvec_ors_sparc64 +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_sparc64 +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_sparc64 +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_sparc64 +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_sparc64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_sparc64 +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_sparc64 +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_sparc64 +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_sparc64 +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_sparc64 +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_sparc64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_sparc64 +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_sparc64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_sparc64 +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_sparc64 +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_sparc64 +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_sparc64 +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_sparc64 +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_sparc64 #define tcg_gen_gvec_smax tcg_gen_gvec_smax_sparc64 #define tcg_gen_gvec_smin tcg_gen_gvec_smin_sparc64 #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_sparc64 @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_sparc64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_sparc64 #define tcg_gen_sari_vec tcg_gen_sari_vec_sparc64 +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_sparc64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_sparc64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_sparc64 #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_sparc64 @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_sparc64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_sparc64 #define tcg_gen_shli_vec tcg_gen_shli_vec_sparc64 +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_sparc64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_sparc64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_sparc64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_sparc64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_sparc64 #define tcg_gen_shri_vec tcg_gen_shri_vec_sparc64 +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_sparc64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_sparc64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_sparc64 #define tcg_gen_smax_vec tcg_gen_smax_vec_sparc64 diff --git a/qemu/tcg/tcg-op-gvec.c b/qemu/tcg/tcg-op-gvec.c index 77decd1c..d0bf4cfe 100644 --- a/qemu/tcg/tcg-op-gvec.c +++ b/qemu/tcg/tcg-op-gvec.c @@ -2557,6 +2557,201 @@ void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof } } +/* + * Expand D = A << (B % element bits) + * + * Unlike scalar shifts, where it is easy for the target front end + * to include the modulo as part of the expansion. If the target + * naturally includes the modulo as part of the operation, great! + * If the target has some other behaviour from out-of-range shifts, + * then it could not use this function anyway, and would need to + * do it's own expansion with custom functions. + */ +static void tcg_gen_shlv_mod_vec(TCGContext *s, unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t = tcg_temp_new_vec_matching(s, d); + + tcg_gen_dupi_vec(s, vece, t, (8 << vece) - 1); + tcg_gen_and_vec(s, vece, t, t, b); + tcg_gen_shlv_vec(s, vece, d, a, t); + tcg_temp_free_vec(s, t); +} + +static void tcg_gen_shl_mod_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(s); + + tcg_gen_andi_i32(s, t, b, 31); + tcg_gen_shl_i32(s, d, a, t); + tcg_temp_free_i32(s, t); +} + +static void tcg_gen_shl_mod_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t = tcg_temp_new_i64(s); + + tcg_gen_andi_i64(s, t, b, 63); + tcg_gen_shl_i64(s, d, a, t); + tcg_temp_free_i64(s, t); +} + +void tcg_gen_gvec_shlv(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { INDEX_op_shlv_vec, 0 }; + static const GVecGen3 g[4] = { + { .fniv = tcg_gen_shlv_mod_vec, + .fno = gen_helper_gvec_shl8v, + .opt_opc = vecop_list, + .vece = MO_8 }, + { .fniv = tcg_gen_shlv_mod_vec, + .fno = gen_helper_gvec_shl16v, + .opt_opc = vecop_list, + .vece = MO_16 }, + { .fni4 = tcg_gen_shl_mod_i32, + .fniv = tcg_gen_shlv_mod_vec, + .fno = gen_helper_gvec_shl32v, + .opt_opc = vecop_list, + .vece = MO_32 }, + { .fni8 = tcg_gen_shl_mod_i64, + .fniv = tcg_gen_shlv_mod_vec, + .fno = gen_helper_gvec_shl64v, + .opt_opc = vecop_list, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .vece = MO_64 }, + }; + + tcg_debug_assert(vece <= MO_64); + tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +/* + * Similarly for logical right shifts. + */ + +static void tcg_gen_shrv_mod_vec(TCGContext *s, unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t = tcg_temp_new_vec_matching(s, d); + + tcg_gen_dupi_vec(s, vece, t, (8 << vece) - 1); + tcg_gen_and_vec(s, vece, t, t, b); + tcg_gen_shrv_vec(s, vece, d, a, t); + tcg_temp_free_vec(s, t); +} + +static void tcg_gen_shr_mod_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(s); + + tcg_gen_andi_i32(s, t, b, 31); + tcg_gen_shr_i32(s, d, a, t); + tcg_temp_free_i32(s, t); +} + +static void tcg_gen_shr_mod_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t = tcg_temp_new_i64(s); + + tcg_gen_andi_i64(s, t, b, 63); + tcg_gen_shr_i64(s, d, a, t); + tcg_temp_free_i64(s, t); +} + +void tcg_gen_gvec_shrv(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { INDEX_op_shrv_vec, 0 }; + static const GVecGen3 g[4] = { + { .fniv = tcg_gen_shrv_mod_vec, + .fno = gen_helper_gvec_shr8v, + .opt_opc = vecop_list, + .vece = MO_8 }, + { .fniv = tcg_gen_shrv_mod_vec, + .fno = gen_helper_gvec_shr16v, + .opt_opc = vecop_list, + .vece = MO_16 }, + { .fni4 = tcg_gen_shr_mod_i32, + .fniv = tcg_gen_shrv_mod_vec, + .fno = gen_helper_gvec_shr32v, + .opt_opc = vecop_list, + .vece = MO_32 }, + { .fni8 = tcg_gen_shr_mod_i64, + .fniv = tcg_gen_shrv_mod_vec, + .fno = gen_helper_gvec_shr64v, + .opt_opc = vecop_list, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .vece = MO_64 }, + }; + + tcg_debug_assert(vece <= MO_64); + tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + +/* + * Similarly for arithmetic right shifts. + */ + +static void tcg_gen_sarv_mod_vec(TCGContext *s, unsigned vece, TCGv_vec d, + TCGv_vec a, TCGv_vec b) +{ + TCGv_vec t = tcg_temp_new_vec_matching(s, d); + + tcg_gen_dupi_vec(s, vece, t, (8 << vece) - 1); + tcg_gen_and_vec(s, vece, t, t, b); + tcg_gen_sarv_vec(s, vece, d, a, t); + tcg_temp_free_vec(s, t); +} + +static void tcg_gen_sar_mod_i32(TCGContext *s, TCGv_i32 d, TCGv_i32 a, TCGv_i32 b) +{ + TCGv_i32 t = tcg_temp_new_i32(s); + + tcg_gen_andi_i32(s, t, b, 31); + tcg_gen_sar_i32(s, d, a, t); + tcg_temp_free_i32(s, t); +} + +static void tcg_gen_sar_mod_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) +{ + TCGv_i64 t = tcg_temp_new_i64(s); + + tcg_gen_andi_i64(s, t, b, 63); + tcg_gen_sar_i64(s, d, a, t); + tcg_temp_free_i64(s, t); +} + +void tcg_gen_gvec_sarv(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz) +{ + static const TCGOpcode vecop_list[] = { INDEX_op_sarv_vec, 0 }; + static const GVecGen3 g[4] = { + { .fniv = tcg_gen_sarv_mod_vec, + .fno = gen_helper_gvec_sar8v, + .opt_opc = vecop_list, + .vece = MO_8 }, + { .fniv = tcg_gen_sarv_mod_vec, + .fno = gen_helper_gvec_sar16v, + .opt_opc = vecop_list, + .vece = MO_16 }, + { .fni4 = tcg_gen_sar_mod_i32, + .fniv = tcg_gen_sarv_mod_vec, + .fno = gen_helper_gvec_sar32v, + .opt_opc = vecop_list, + .vece = MO_32 }, + { .fni8 = tcg_gen_sar_mod_i64, + .fniv = tcg_gen_sarv_mod_vec, + .fno = gen_helper_gvec_sar64v, + .opt_opc = vecop_list, + .prefer_i64 = TCG_TARGET_REG_BITS == 64, + .vece = MO_64 }, + }; + + tcg_debug_assert(vece <= MO_64); + tcg_gen_gvec_3(s, dofs, aofs, bofs, oprsz, maxsz, &g[vece]); +} + /* Expand OPSZ bytes worth of three-operand operations using i32 elements. */ static void expand_cmp_i32(TCGContext *s, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, TCGCond cond) diff --git a/qemu/tcg/tcg-op-gvec.h b/qemu/tcg/tcg-op-gvec.h index 520e4187..d4ea46aa 100644 --- a/qemu/tcg/tcg-op-gvec.h +++ b/qemu/tcg/tcg-op-gvec.h @@ -313,6 +313,17 @@ void tcg_gen_gvec_shri(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aof void tcg_gen_gvec_sari(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs, int64_t shift, uint32_t oprsz, uint32_t maxsz); +/* + * Perform vector shift by vector element, modulo the element size. + * E.g. D[i] = A[i] << (B[i] % (8 << vece)). + */ +void tcg_gen_gvec_shlv(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_shrv(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); +void tcg_gen_gvec_sarv(TCGContext *, unsigned vece, uint32_t dofs, uint32_t aofs, + uint32_t bofs, uint32_t oprsz, uint32_t maxsz); + void tcg_gen_gvec_cmp(TCGContext *s, TCGCond cond, unsigned vece, uint32_t dofs, uint32_t aofs, uint32_t bofs, uint32_t oprsz, uint32_t maxsz); diff --git a/qemu/tcg/tcg-op-vec.c b/qemu/tcg/tcg-op-vec.c index efe91093..cf0b0050 100644 --- a/qemu/tcg/tcg-op-vec.c +++ b/qemu/tcg/tcg-op-vec.c @@ -588,3 +588,18 @@ void tcg_gen_umax_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv { do_op3(s, vece, r, a, b, INDEX_op_umax_vec); } + +void tcg_gen_shlv_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(s, vece, r, a, b, INDEX_op_shlv_vec); +} + +void tcg_gen_shrv_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(s, vece, r, a, b, INDEX_op_shrv_vec); +} + +void tcg_gen_sarv_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b) +{ + do_op3(s, vece, r, a, b, INDEX_op_sarv_vec); +} diff --git a/qemu/tcg/tcg-op.h b/qemu/tcg/tcg-op.h index 4dec4135..cc6f5b5a 100644 --- a/qemu/tcg/tcg-op.h +++ b/qemu/tcg/tcg-op.h @@ -1000,6 +1000,10 @@ void tcg_gen_shli_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64 void tcg_gen_shri_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); void tcg_gen_sari_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, int64_t i); +void tcg_gen_shlv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_shrv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); +void tcg_gen_sarv_vec(TCGContext *, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec s); + void tcg_gen_cmp_vec(TCGContext *, TCGCond cond, unsigned vece, TCGv_vec r, TCGv_vec a, TCGv_vec b); diff --git a/qemu/x86_64.h b/qemu/x86_64.h index a6835abe..86058773 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -1213,21 +1213,33 @@ #define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_x86_64 #define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_x86_64 #define helper_gvec_sar8i helper_gvec_sar8i_x86_64 +#define helper_gvec_sar8v helper_gvec_sar8v_x86_64 #define helper_gvec_sar16i helper_gvec_sar16i_x86_64 +#define helper_gvec_sar16v helper_gvec_sar16v_x86_64 #define helper_gvec_sar32i helper_gvec_sar32i_x86_64 +#define helper_gvec_sar32v helper_gvec_sar32v_x86_64 #define helper_gvec_sar64i helper_gvec_sar64i_x86_64 +#define helper_gvec_sar64v helper_gvec_sar64v_x86_64 #define helper_gvec_sdot_b helper_gvec_sdot_b_x86_64 #define helper_gvec_sdot_h helper_gvec_sdot_h_x86_64 #define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_x86_64 #define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_x86_64 #define helper_gvec_shl8i helper_gvec_shl8i_x86_64 +#define helper_gvec_shl8v helper_gvec_shl8v_x86_64 #define helper_gvec_shl16i helper_gvec_shl16i_x86_64 +#define helper_gvec_shl16v helper_gvec_shl16v_x86_64 #define helper_gvec_shl32i helper_gvec_shl32i_x86_64 +#define helper_gvec_shl32v helper_gvec_shl32v_x86_64 #define helper_gvec_shl64i helper_gvec_shl64i_x86_64 +#define helper_gvec_shl64v helper_gvec_shl64v_x86_64 #define helper_gvec_shr8i helper_gvec_shr8i_x86_64 +#define helper_gvec_shr8v helper_gvec_shr8v_x86_64 #define helper_gvec_shr16i helper_gvec_shr16i_x86_64 +#define helper_gvec_shr16v helper_gvec_shr16v_x86_64 #define helper_gvec_shr32i helper_gvec_shr32i_x86_64 +#define helper_gvec_shr32v helper_gvec_shr32v_x86_64 #define helper_gvec_shr64i helper_gvec_shr64i_x86_64 +#define helper_gvec_shr64v helper_gvec_shr64v_x86_64 #define helper_gvec_smax8 helper_gvec_smax8_x86_64 #define helper_gvec_smax16 helper_gvec_smax16_x86_64 #define helper_gvec_smax32 helper_gvec_smax32_x86_64 @@ -2889,9 +2901,24 @@ #define tcg_gen_gvec_orc tcg_gen_gvec_orc_x86_64 #define tcg_gen_gvec_ori tcg_gen_gvec_ori_x86_64 #define tcg_gen_gvec_ors tcg_gen_gvec_ors_x86_64 +#define tcg_gen_gvec_sar8v tcg_gen_gvec_sar8v_x86_64 +#define tcg_gen_gvec_sar16v tcg_gen_gvec_sar16v_x86_64 +#define tcg_gen_gvec_sar32v tcg_gen_gvec_sar32v_x86_64 +#define tcg_gen_gvec_sar64v tcg_gen_gvec_sar64v_x86_64 #define tcg_gen_gvec_sari tcg_gen_gvec_sari_x86_64 +#define tcg_gen_gvec_sarv tcg_gen_gvec_sarv_x86_64 +#define tcg_gen_gvec_shl8v tcg_gen_gvec_shl8v_x86_64 +#define tcg_gen_gvec_shl16v tcg_gen_gvec_shl16v_x86_64 +#define tcg_gen_gvec_shl32v tcg_gen_gvec_shl32v_x86_64 +#define tcg_gen_gvec_shl64v tcg_gen_gvec_shl64v_x86_64 #define tcg_gen_gvec_shli tcg_gen_gvec_shli_x86_64 +#define tcg_gen_gvec_shlv tcg_gen_gvec_shlv_x86_64 #define tcg_gen_gvec_shri tcg_gen_gvec_shri_x86_64 +#define tcg_gen_gvec_shrv tcg_gen_gvec_shrv_x86_64 +#define tcg_gen_gvec_shr8v tcg_gen_gvec_shr8v_x86_64 +#define tcg_gen_gvec_shr16v tcg_gen_gvec_shr16v_x86_64 +#define tcg_gen_gvec_shr32v tcg_gen_gvec_shr32v_x86_64 +#define tcg_gen_gvec_shr64v tcg_gen_gvec_shr64v_x86_64 #define tcg_gen_gvec_smax tcg_gen_gvec_smax_x86_64 #define tcg_gen_gvec_smin tcg_gen_gvec_smin_x86_64 #define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_x86_64 @@ -3003,6 +3030,7 @@ #define tcg_gen_sari_i32 tcg_gen_sari_i32_x86_64 #define tcg_gen_sari_i64 tcg_gen_sari_i64_x86_64 #define tcg_gen_sari_vec tcg_gen_sari_vec_x86_64 +#define tcg_gen_sarv_vec tcg_gen_sarv_vec_x86_64 #define tcg_gen_setcond_i32 tcg_gen_setcond_i32_x86_64 #define tcg_gen_setcond_i64 tcg_gen_setcond_i64_x86_64 #define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_x86_64 @@ -3015,11 +3043,13 @@ #define tcg_gen_shli_i32 tcg_gen_shli_i32_x86_64 #define tcg_gen_shli_i64 tcg_gen_shli_i64_x86_64 #define tcg_gen_shli_vec tcg_gen_shli_vec_x86_64 +#define tcg_gen_shlv_vec tcg_gen_shlv_vec_x86_64 #define tcg_gen_shr_i32 tcg_gen_shr_i32_x86_64 #define tcg_gen_shr_i64 tcg_gen_shr_i64_x86_64 #define tcg_gen_shri_i32 tcg_gen_shri_i32_x86_64 #define tcg_gen_shri_i64 tcg_gen_shri_i64_x86_64 #define tcg_gen_shri_vec tcg_gen_shri_vec_x86_64 +#define tcg_gen_shrv_vec tcg_gen_shrv_vec_x86_64 #define tcg_gen_smax_i32 tcg_gen_smax_i32_x86_64 #define tcg_gen_smax_i64 tcg_gen_smax_i64_x86_64 #define tcg_gen_smax_vec tcg_gen_smax_vec_x86_64