From 8e2ac48ad033d4518053629c81a398dd1cc3649e Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Sat, 21 Mar 2020 15:31:47 -0400 Subject: [PATCH] target/arm: Update ctr_el0_access for EL2 Update to include checks against HCR_EL2.TID2. Backports commit 97475a89375d62a7722e04ced9fbdf0b992f4b83 from qemu --- qemu/target/arm/helper.c | 26 +++++++++++++++++++++----- 1 file changed, 21 insertions(+), 5 deletions(-) diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index c50fcd50..dcf92f26 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -5058,11 +5058,27 @@ static const ARMCPRegInfo el3_cp_reginfo[] = { static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64, - * but the AArch32 CTR has its own reginfo struct) - */ - if (arm_current_el(env) == 0 && !(env->cp15.sctlr_el[1] & SCTLR_UCT)) { - return CP_ACCESS_TRAP; + int cur_el = arm_current_el(env); + + if (cur_el < 2) { + uint64_t hcr = arm_hcr_el2_eff(env); + + if (cur_el == 0) { + if ((hcr & (HCR_E2H | HCR_TGE)) == (HCR_E2H | HCR_TGE)) { + if (!(env->cp15.sctlr_el[2] & SCTLR_UCT)) { + return CP_ACCESS_TRAP_EL2; + } + } else { + if (!(env->cp15.sctlr_el[1] & SCTLR_UCT)) { + return CP_ACCESS_TRAP; + } + if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } + } + } else if (hcr & HCR_TID2) { + return CP_ACCESS_TRAP_EL2; + } } if (arm_current_el(env) < 2 && arm_hcr_el2_eff(env) & HCR_TID2) {