From 907bb26e5f8f116a782089c82d57574bd77b95d2 Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Tue, 13 Feb 2018 13:35:42 -0500 Subject: [PATCH] target-mips: correct MFC0 for CP0.EntryLo in MIPS64 CP0.EntryLo bits 31:30 have to be cleared. Backports commit b435f3f3d174721382b55bbd0c785ec50c1796a9 from qemu --- qemu/target-mips/translate.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/qemu/target-mips/translate.c b/qemu/target-mips/translate.c index 8be9951c..d00e9f55 100644 --- a/qemu/target-mips/translate.c +++ b/qemu/target-mips/translate.c @@ -5029,10 +5029,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_tl(tcg_ctx, tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tcg_ctx, tmp, tmp, 32); - tcg_gen_or_tl(tcg_ctx, arg, arg, tmp); + tcg_gen_shri_tl(tcg_ctx, tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(tcg_ctx, arg, arg, tmp, 30, 2); tcg_temp_free(tcg_ctx, tmp); } #endif @@ -5084,10 +5084,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel) tcg_gen_ld_tl(tcg_ctx, arg, tcg_ctx->cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1)); #if defined(TARGET_MIPS64) if (ctx->rxi) { + /* Move RI/XI fields to bits 31:30 */ TCGv tmp = tcg_temp_new(tcg_ctx); - tcg_gen_andi_tl(tcg_ctx, tmp, arg, (3ull << CP0EnLo_XI)); - tcg_gen_shri_tl(tcg_ctx, tmp, tmp, 32); - tcg_gen_or_tl(tcg_ctx, arg, arg, tmp); + tcg_gen_shri_tl(tcg_ctx, tmp, arg, CP0EnLo_XI); + tcg_gen_deposit_tl(tcg_ctx, arg, arg, tmp, 30, 2); tcg_temp_free(tcg_ctx, tmp); } #endif