diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index a0dd91fb..50c15bab 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -4826,6 +4826,79 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc,
     tcg_temp_free(tcg_ctx, t1);
 }
 
+/*
+ * These MULT and MULTU instructions implemented in for example the
+ * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core
+ * architectures are special three-operand variants with the syntax
+ *
+ *     MULT[U] rd, rs, rt
+ *
+ * such that
+ *
+ *     (rd, LO, HI) <- rs * rt
+ *
+ * where the low-order 32-bits of the result is placed into both the
+ * GPR rd and the special register LO. The high-order 32-bits of the
+ * result is placed into the special register HI.
+ *
+ * If the GPR rd is omitted in assembly language, it is taken to be 0,
+ * which is the zero register that always reads as 0.
+ */
+static void gen_mul_txx9(DisasContext *ctx, uint32_t opc,
+                         int rd, int rs, int rt)
+{
+    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    TCGv t0 = tcg_temp_new(tcg_ctx);
+    TCGv t1 = tcg_temp_new(tcg_ctx);
+    int acc = 0;
+
+    gen_load_gpr(ctx, t0, rs);
+    gen_load_gpr(ctx, t1, rt);
+
+    switch (opc) {
+    case OPC_MULT:
+        {
+            TCGv_i32 t2 = tcg_temp_new_i32(tcg_ctx);
+            TCGv_i32 t3 = tcg_temp_new_i32(tcg_ctx);
+            tcg_gen_trunc_tl_i32(tcg_ctx, t2, t0);
+            tcg_gen_trunc_tl_i32(tcg_ctx, t3, t1);
+            tcg_gen_muls2_i32(tcg_ctx, t2, t3, t2, t3);
+            if (rd) {
+                tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_gpr[rd], t2);
+            }
+            tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
+            tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_HI[acc], t3);
+            tcg_temp_free_i32(tcg_ctx, t2);
+            tcg_temp_free_i32(tcg_ctx, t3);
+        }
+        break;
+    case OPC_MULTU:
+        {
+            TCGv_i32 t2 = tcg_temp_new_i32(tcg_ctx);
+            TCGv_i32 t3 = tcg_temp_new_i32(tcg_ctx);
+            tcg_gen_trunc_tl_i32(tcg_ctx, t2, t0);
+            tcg_gen_trunc_tl_i32(tcg_ctx, t3, t1);
+            tcg_gen_mulu2_i32(tcg_ctx, t2, t3, t2, t3);
+            if (rd) {
+                tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_gpr[rd], t2);
+            }
+            tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_LO[acc], t2);
+            tcg_gen_ext_i32_tl(tcg_ctx, tcg_ctx->cpu_HI[acc], t3);
+            tcg_temp_free_i32(tcg_ctx, t2);
+            tcg_temp_free_i32(tcg_ctx, t3);
+        }
+        break;
+    default:
+        MIPS_INVAL("mul TXx9");
+        generate_exception_end(ctx, EXCP_RI);
+        goto out;
+    }
+
+ out:
+    tcg_temp_free(tcg_ctx, t0);
+    tcg_temp_free(tcg_ctx, t1);
+}
+
 static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc,
                             int rd, int rs, int rt)
 {
@@ -23641,6 +23714,8 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx)
             check_insn(ctx, INSN_VR54XX);
             op1 = MASK_MUL_VR54XX(ctx->opcode);
             gen_mul_vr54xx(ctx, op1, rd, rs, rt);
+        } else if (ctx->insn_flags & INSN_R5900) {
+            gen_mul_txx9(ctx, op1, rd, rs, rt);
         } else {
             gen_muldiv(ctx, op1, rd & 3, rs, rt);
         }