diff --git a/qemu/target-arm/cpu64.c b/qemu/target-arm/cpu64.c
index a84fce58..07c55ca3 100644
--- a/qemu/target-arm/cpu64.c
+++ b/qemu/target-arm/cpu64.c
@@ -34,21 +34,21 @@ static inline QEMU_UNUSED_FUNC void unset_feature(CPUARMState *env, int feature)
 }
 
 #ifndef CONFIG_USER_ONLY
-static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 {
     /* Number of processors is in [25:24]; otherwise we RAZ */
     return (smp_cpus - 1) << 24;
 }
 #endif
 
-static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
+static const ARMCPRegInfo cortex_a57_a53_cp_reginfo[] = {
 #ifndef CONFIG_USER_ONLY
     { "L2CTLR_EL1", 0,11,0, 3,1,2, ARM_CP_STATE_AA64,
       0, PL1_RW, 0, NULL, 0, 0, {0, 0},
-      NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
+      NULL, a57_a53_l2ctlr_read, arm_cp_write_ignore, },
     { "L2CTLR", 15,9,0, 0,1,2, 0,
       0, PL1_RW, 0, NULL, 0, 0, {0, 0},
-      NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
+      NULL, a57_a53_l2ctlr_read, arm_cp_write_ignore, },
 #endif
     { "L2ECTLR_EL1", 0,11,0, 3,1,3, ARM_CP_STATE_AA64,
       ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
@@ -123,7 +123,7 @@ static void aarch64_a57_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     cpu->ccsidr[1] = 0x201fe012; /* 48KB L1 icache */
     cpu->ccsidr[2] = 0x70ffe07a; /* 2048KB L2 cache */
     cpu->dcz_blocksize = 4; /* 64 bytes */
-    define_arm_cp_regs(cpu, cortexa57_cp_reginfo);
+    define_arm_cp_regs(cpu, cortex_a57_a53_cp_reginfo);
 }
 
 #ifdef CONFIG_USER_ONLY