From 94b5aab8f86aa28e816c8772d9aa31ae1b8180c6 Mon Sep 17 00:00:00 2001
From: Richard Henderson <richard.henderson@linaro.org>
Date: Tue, 5 Mar 2019 23:04:05 -0500
Subject: [PATCH] target/arm: Implement ARMv8.5-CondM

Backports commit 5ef84f111483e3f7b57efc690e22081ca8f99544 from qemu
---
 qemu/target/arm/cpu.h           |  5 +++
 qemu/target/arm/cpu64.c         |  2 +-
 qemu/target/arm/translate-a64.c | 61 +++++++++++++++++++++++++++++++++
 3 files changed, 67 insertions(+), 1 deletion(-)

diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h
index bab79d5f..a04fe1fa 100644
--- a/qemu/target/arm/cpu.h
+++ b/qemu/target/arm/cpu.h
@@ -3416,6 +3416,11 @@ static inline bool isar_feature_aa64_condm_4(const ARMISARegisters *id)
     return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) != 0;
 }
 
+static inline bool isar_feature_aa64_condm_5(const ARMISARegisters *id)
+{
+    return FIELD_EX64(id->id_aa64isar0, ID_AA64ISAR0, TS) >= 2;
+}
+
 static inline bool isar_feature_aa64_jscvt(const ARMISARegisters *id)
 {
     return FIELD_EX64(id->id_aa64isar1, ID_AA64ISAR1, JSCVT) != 0;
diff --git a/qemu/target/arm/cpu64.c b/qemu/target/arm/cpu64.c
index 866aaf08..975d8d39 100644
--- a/qemu/target/arm/cpu64.c
+++ b/qemu/target/arm/cpu64.c
@@ -254,7 +254,7 @@ static void aarch64_max_initfn(struct uc_struct *uc, Object *obj, void *opaque)
     t = FIELD_DP64(t, ID_AA64ISAR0, SM4, 1);
     t = FIELD_DP64(t, ID_AA64ISAR0, DP, 1);
     t = FIELD_DP64(t, ID_AA64ISAR0, FHM, 1);
-    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 1);
+    t = FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */
     cpu->isar.id_aa64isar0 = t;
 
     t = cpu->isar.id_aa64isar1;
diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c
index 3e5de952..e7ccb4e6 100644
--- a/qemu/target/arm/translate-a64.c
+++ b/qemu/target/arm/translate-a64.c
@@ -1721,6 +1721,51 @@ static void handle_sync(DisasContext *s, uint32_t insn,
     }
 }
 
+static void gen_xaflag(DisasContext *s)
+{
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+    TCGv_i32 z = tcg_temp_new_i32(tcg_ctx);
+
+    tcg_gen_setcondi_i32(tcg_ctx, TCG_COND_EQ, z, tcg_ctx->cpu_ZF, 0);
+
+    /*
+     * (!C & !Z) << 31
+     * (!(C | Z)) << 31
+     * ~((C | Z) << 31)
+     * ~-(C | Z)
+     * (C | Z) - 1
+     */
+    tcg_gen_or_i32(tcg_ctx, tcg_ctx->cpu_NF, tcg_ctx->cpu_CF, z);
+    tcg_gen_subi_i32(tcg_ctx, tcg_ctx->cpu_NF, tcg_ctx->cpu_NF, 1);
+
+    /* !(Z & C) */
+    tcg_gen_and_i32(tcg_ctx, tcg_ctx->cpu_ZF, z, tcg_ctx->cpu_CF);
+    tcg_gen_xori_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_ZF, 1);
+
+    /* (!C & Z) << 31 -> -(Z & ~C) */
+    tcg_gen_andc_i32(tcg_ctx, tcg_ctx->cpu_VF, z, tcg_ctx->cpu_CF);
+    tcg_gen_neg_i32(tcg_ctx, tcg_ctx->cpu_VF, tcg_ctx->cpu_VF);
+
+    /* C | Z */
+    tcg_gen_or_i32(tcg_ctx, tcg_ctx->cpu_CF, tcg_ctx->cpu_CF, z);
+
+    tcg_temp_free_i32(tcg_ctx, z);
+}
+
+static void gen_axflag(DisasContext *s)
+{
+    TCGContext *tcg_ctx = s->uc->tcg_ctx;
+
+    tcg_gen_sari_i32(tcg_ctx, tcg_ctx->cpu_VF, tcg_ctx->cpu_VF, 31);         /* V ? -1 : 0 */
+    tcg_gen_andc_i32(tcg_ctx, tcg_ctx->cpu_CF, tcg_ctx->cpu_CF, tcg_ctx->cpu_VF);     /* C & !V */
+
+    /* !(Z | V) -> !(!ZF | V) -> ZF & !V -> ZF & ~VF */
+    tcg_gen_andc_i32(tcg_ctx, tcg_ctx->cpu_ZF, tcg_ctx->cpu_ZF, tcg_ctx->cpu_VF);
+
+    tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_NF, 0);
+    tcg_gen_movi_i32(tcg_ctx, tcg_ctx->cpu_VF, 0);
+}
+
 /* MSR (immediate) - move immediate to processor state field */
 static void handle_msr_i(DisasContext *s, uint32_t insn,
                          unsigned int op1, unsigned int op2, unsigned int crm)
@@ -1741,6 +1786,22 @@ static void handle_msr_i(DisasContext *s, uint32_t insn,
         s->base.is_jmp = DISAS_NEXT;
         break;
 
+    case 0x01: /* XAFlag */
+        if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
+            goto do_unallocated;
+        }
+        gen_xaflag(s);
+        s->base.is_jmp = DISAS_NEXT;
+        break;
+
+    case 0x02: /* AXFlag */
+        if (crm != 0 || !dc_isar_feature(aa64_condm_5, s)) {
+            goto do_unallocated;
+        }
+        gen_axflag(s);
+        s->base.is_jmp = DISAS_NEXT;
+        break;
+
     case 0x05: /* SPSel */
         if (s->current_el == 0) {
             goto do_unallocated;