From 94dbf9eb9630a6fe6191daad911e86cf1ced68be Mon Sep 17 00:00:00 2001 From: Lioncash Date: Sat, 6 Oct 2018 05:14:45 -0400 Subject: [PATCH] targets: Initial RISC-V port Functionally everything is here, however it crashes for some bizarre reason upon initialization. Yay for qemu having an overcomplicated initialization process that's difficult to keep a mental model of. --- .gitignore | 2 + Makefile | 11 +- include/uc_priv.h | 9 +- include/unicorn/riscv.h | 142 + include/unicorn/unicorn.h | 7 +- qemu/aarch64.h | 2 - qemu/aarch64eb.h | 2 - qemu/accel.c | 1 - qemu/arm.h | 2 - qemu/armeb.h | 2 - qemu/configure | 9 + qemu/default-configs/riscv32-softmmu.mak | 5 + qemu/default-configs/riscv64-softmmu.mak | 5 + qemu/header_gen.py | 85 +- qemu/hw/riscv/Makefile.objs | 1 + qemu/hw/riscv/spike.c | 55 + qemu/include/hw/riscv/spike.h | 16 + qemu/m68k.h | 2 - qemu/mips.h | 2 - qemu/mips64.h | 2 - qemu/mips64el.h | 2 - qemu/mipsel.h | 2 - qemu/powerpc.h | 2 - qemu/riscv32.h | 3343 ++++++++++++++++++++++ qemu/riscv64.h | 3343 ++++++++++++++++++++++ qemu/sparc.h | 2 - qemu/sparc64.h | 2 - qemu/target/riscv/Makefile.objs | 2 + qemu/target/riscv/cpu.c | 441 +++ qemu/target/riscv/cpu.h | 300 ++ qemu/target/riscv/cpu_bits.h | 409 +++ qemu/target/riscv/cpu_user.h | 13 + qemu/target/riscv/fpu_helper.c | 371 +++ qemu/target/riscv/helper.c | 526 ++++ qemu/target/riscv/helper.h | 82 + qemu/target/riscv/instmap.h | 364 +++ qemu/target/riscv/op_helper.c | 782 +++++ qemu/target/riscv/pmp.c | 380 +++ qemu/target/riscv/pmp.h | 64 + qemu/target/riscv/translate.c | 1974 +++++++++++++ qemu/target/riscv/unicorn.c | 114 + qemu/target/riscv/unicorn.h | 13 + qemu/tcg/tcg.h | 17 +- qemu/x86_64.h | 2 - samples/Makefile | 3 + samples/sample_riscv.c | 146 + uc.c | 54 +- 47 files changed, 13068 insertions(+), 47 deletions(-) create mode 100644 include/unicorn/riscv.h create mode 100644 qemu/default-configs/riscv32-softmmu.mak create mode 100644 qemu/default-configs/riscv64-softmmu.mak create mode 100644 qemu/hw/riscv/Makefile.objs create mode 100644 qemu/hw/riscv/spike.c create mode 100644 qemu/include/hw/riscv/spike.h create mode 100644 qemu/riscv32.h create mode 100644 qemu/riscv64.h create mode 100644 qemu/target/riscv/Makefile.objs create mode 100644 qemu/target/riscv/cpu.c create mode 100644 qemu/target/riscv/cpu.h create mode 100644 qemu/target/riscv/cpu_bits.h create mode 100644 qemu/target/riscv/cpu_user.h create mode 100644 qemu/target/riscv/fpu_helper.c create mode 100644 qemu/target/riscv/helper.c create mode 100644 qemu/target/riscv/helper.h create mode 100644 qemu/target/riscv/instmap.h create mode 100644 qemu/target/riscv/op_helper.c create mode 100644 qemu/target/riscv/pmp.c create mode 100644 qemu/target/riscv/pmp.h create mode 100644 qemu/target/riscv/translate.c create mode 100644 qemu/target/riscv/unicorn.c create mode 100644 qemu/target/riscv/unicorn.h create mode 100644 samples/sample_riscv.c diff --git a/.gitignore b/.gitignore index f71ae210..cfb54a03 100644 --- a/.gitignore +++ b/.gitignore @@ -23,6 +23,8 @@ qemu/mips64el-softmmu/ qemu/mips64-softmmu/ qemu/mipsel-softmmu/ qemu/mips-softmmu/ +qemu/riscv32-softmmu/ +qemu/riscv64-softmmu/ qemu/sparc64-softmmu/ qemu/sparc-softmmu/ qemu/i386-softmmu/ diff --git a/Makefile b/Makefile index 69f4fb41..612ca478 100644 --- a/Makefile +++ b/Makefile @@ -65,6 +65,15 @@ ifneq (,$(findstring sparc,$(UNICORN_ARCHS))) UNICORN_CFLAGS += -DUNICORN_HAS_SPARC UNICORN_TARGETS += sparc-softmmu,sparc64-softmmu, endif +ifneq (,$(findstring riscv,$(UNICORN_ARCHS))) + UC_TARGET_OBJ += $(call GENOBJ,riscv32-softmmu) + UC_TARGET_OBJ += $(call GENOBJ,riscv64-softmmu) + UNICORN_CFLAGS += -DUNICORN_HAS_RISCV + UNICORN_CFLAGS += -DUNICORN_HAS_RISCV32 + UNICORN_CFLAGS += -DUNICORN_HAS_RISCV64 + UNICORN_TARGETS += riscv32-softmmu + UNICORN_TARGETS += riscv64-softmmu +endif UNICORN_CFLAGS += -fPIC @@ -318,7 +327,7 @@ dist: # run "make header" whenever qemu/header_gen.py is modified header: $(eval TARGETS := m68k arm armeb aarch64 aarch64eb mips mipsel mips64 mips64el\ - powerpc sparc sparc64 x86_64) + powerpc riscv32 riscv64 sparc sparc64 x86_64) $(foreach var,$(TARGETS),\ $(shell python qemu/header_gen.py $(var) > qemu/$(var).h;)) @echo "Generated headers for $(TARGETS)." diff --git a/include/uc_priv.h b/include/uc_priv.h index 2a726cee..e4174f98 100644 --- a/include/uc_priv.h +++ b/include/uc_priv.h @@ -15,11 +15,12 @@ // These are masks of supported modes for each cpu/arch. // They should be updated when changes are made to the uc_mode enum typedef. #define UC_MODE_ARM_MASK (UC_MODE_ARM|UC_MODE_THUMB|UC_MODE_LITTLE_ENDIAN|UC_MODE_MCLASS|UC_MODE_BIG_ENDIAN) -#define UC_MODE_MIPS_MASK (UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN) -#define UC_MODE_X86_MASK (UC_MODE_16|UC_MODE_32|UC_MODE_64|UC_MODE_LITTLE_ENDIAN) -#define UC_MODE_PPC_MASK (UC_MODE_PPC64|UC_MODE_BIG_ENDIAN) -#define UC_MODE_SPARC_MASK (UC_MODE_SPARC32|UC_MODE_SPARC64|UC_MODE_BIG_ENDIAN) #define UC_MODE_M68K_MASK (UC_MODE_BIG_ENDIAN) +#define UC_MODE_MIPS_MASK (UC_MODE_MIPS32|UC_MODE_MIPS64|UC_MODE_LITTLE_ENDIAN|UC_MODE_BIG_ENDIAN) +#define UC_MODE_PPC_MASK (UC_MODE_PPC64|UC_MODE_BIG_ENDIAN) +#define UC_MODE_RISCV_MASK (UC_MODE_RISCV32|UC_MODE_RISCV64) +#define UC_MODE_SPARC_MASK (UC_MODE_SPARC32|UC_MODE_SPARC64|UC_MODE_BIG_ENDIAN) +#define UC_MODE_X86_MASK (UC_MODE_16|UC_MODE_32|UC_MODE_64|UC_MODE_LITTLE_ENDIAN) #define ARR_SIZE(a) (sizeof(a)/sizeof(a[0])) diff --git a/include/unicorn/riscv.h b/include/unicorn/riscv.h new file mode 100644 index 00000000..8aa385c0 --- /dev/null +++ b/include/unicorn/riscv.h @@ -0,0 +1,142 @@ +/* Unicorn Emulator Engine */ +/* By Nguyen Anh Quynh , 2015-2017 */ +/* This file is released under LGPL2. + See COPYING.LGPL2 in root directory for more details +*/ + +#ifndef UNICORN_RISCV_H +#define UNICORN_RISCV_H + +#ifdef __cplusplus +extern "C" { +#endif + +typedef enum uc_riscv_reg { + UC_RISCV_REG_INVALID = 0, + + /* General-purpose registers */ + UC_RISCV_REG_X0, + UC_RISCV_REG_X1, + UC_RISCV_REG_X2, + UC_RISCV_REG_X3, + UC_RISCV_REG_X4, + UC_RISCV_REG_X5, + UC_RISCV_REG_X6, + UC_RISCV_REG_X7, + UC_RISCV_REG_X8, + UC_RISCV_REG_X9, + UC_RISCV_REG_X10, + UC_RISCV_REG_X11, + UC_RISCV_REG_X12, + UC_RISCV_REG_X13, + UC_RISCV_REG_X14, + UC_RISCV_REG_X15, + UC_RISCV_REG_X16, + UC_RISCV_REG_X17, + UC_RISCV_REG_X18, + UC_RISCV_REG_X19, + UC_RISCV_REG_X20, + UC_RISCV_REG_X21, + UC_RISCV_REG_X22, + UC_RISCV_REG_X23, + UC_RISCV_REG_X24, + UC_RISCV_REG_X25, + UC_RISCV_REG_X26, + UC_RISCV_REG_X27, + UC_RISCV_REG_X28, + UC_RISCV_REG_X29, + UC_RISCV_REG_X30, + UC_RISCV_REG_X31, + + /* General-purpose register aliases */ + + /* Zero register */ + UC_RISCV_REG_ZERO = UC_RISCV_REG_X0, + /* Return address */ + UC_RISCV_REG_RA = UC_RISCV_REG_X1, + /* Stack pointer */ + UC_RISCV_REG_SP = UC_RISCV_REG_X2, + /* Global pointer */ + UC_RISCV_REG_GP = UC_RISCV_REG_X3, + /* Thread pointer */ + UC_RISCV_REG_TP = UC_RISCV_REG_X4, + /* Temporary registers */ + UC_RISCV_REG_T0 = UC_RISCV_REG_X5, + UC_RISCV_REG_T1 = UC_RISCV_REG_X6, + UC_RISCV_REG_T2 = UC_RISCV_REG_X7, + UC_RISCV_REG_T3 = UC_RISCV_REG_X28, + UC_RISCV_REG_T4 = UC_RISCV_REG_X29, + UC_RISCV_REG_T5 = UC_RISCV_REG_X30, + UC_RISCV_REG_T6 = UC_RISCV_REG_X31, + + /* Frame pointer */ + UC_RISCV_REG_FP = UC_RISCV_REG_X8, + + /* Saved registers */ + UC_RISCV_REG_S0 = UC_RISCV_REG_X8, + UC_RISCV_REG_S1 = UC_RISCV_REG_X9, + UC_RISCV_REG_S2 = UC_RISCV_REG_X18, + UC_RISCV_REG_S3 = UC_RISCV_REG_X19, + UC_RISCV_REG_S4 = UC_RISCV_REG_X20, + UC_RISCV_REG_S5 = UC_RISCV_REG_X21, + UC_RISCV_REG_S6 = UC_RISCV_REG_X22, + UC_RISCV_REG_S7 = UC_RISCV_REG_X23, + UC_RISCV_REG_S8 = UC_RISCV_REG_X24, + UC_RISCV_REG_S9 = UC_RISCV_REG_X25, + UC_RISCV_REG_S10 = UC_RISCV_REG_X26, + UC_RISCV_REG_S11 = UC_RISCV_REG_X27, + + /* Function argument registers */ + UC_RISCV_REG_A0 = UC_RISCV_REG_X10, + UC_RISCV_REG_A1 = UC_RISCV_REG_X11, + UC_RISCV_REG_A2 = UC_RISCV_REG_X12, + UC_RISCV_REG_A3 = UC_RISCV_REG_X13, + UC_RISCV_REG_A4 = UC_RISCV_REG_X14, + UC_RISCV_REG_A5 = UC_RISCV_REG_X15, + UC_RISCV_REG_A6 = UC_RISCV_REG_X16, + UC_RISCV_REG_A7 = UC_RISCV_REG_X17, + + /* Program counter */ + UC_RISCV_REG_PC, + + /* Floating-point registers */ + UC_RISCV_REG_F0, + UC_RISCV_REG_F1, + UC_RISCV_REG_F2, + UC_RISCV_REG_F3, + UC_RISCV_REG_F4, + UC_RISCV_REG_F5, + UC_RISCV_REG_F6, + UC_RISCV_REG_F7, + UC_RISCV_REG_F8, + UC_RISCV_REG_F9, + UC_RISCV_REG_F10, + UC_RISCV_REG_F11, + UC_RISCV_REG_F12, + UC_RISCV_REG_F13, + UC_RISCV_REG_F14, + UC_RISCV_REG_F15, + UC_RISCV_REG_F16, + UC_RISCV_REG_F17, + UC_RISCV_REG_F18, + UC_RISCV_REG_F19, + UC_RISCV_REG_F20, + UC_RISCV_REG_F21, + UC_RISCV_REG_F22, + UC_RISCV_REG_F23, + UC_RISCV_REG_F24, + UC_RISCV_REG_F25, + UC_RISCV_REG_F26, + UC_RISCV_REG_F27, + UC_RISCV_REG_F28, + UC_RISCV_REG_F29, + UC_RISCV_REG_F30, + UC_RISCV_REG_F31, +} uc_riscv_reg; + + +#ifdef __cplusplus +} +#endif + +#endif /* UNICORN_RISCV_H */ diff --git a/include/unicorn/unicorn.h b/include/unicorn/unicorn.h index ee307fac..de86d1cc 100644 --- a/include/unicorn/unicorn.h +++ b/include/unicorn/unicorn.h @@ -31,6 +31,7 @@ typedef size_t uc_hook; #include "arm.h" #include "arm64.h" #include "mips.h" +#include "riscv.h" #include "sparc.h" #ifdef __GNUC__ @@ -95,6 +96,7 @@ typedef enum uc_arch { UC_ARCH_PPC, // PowerPC architecture (currently unsupported) UC_ARCH_SPARC, // Sparc architecture UC_ARCH_M68K, // M68K architecture + UC_ARCH_RISCV, // RISC-V architecture UC_ARCH_MAX, } uc_arch; @@ -117,7 +119,7 @@ typedef enum uc_mode { UC_MODE_16 = 1 << 1, // 16-bit mode UC_MODE_32 = 1 << 2, // 32-bit mode UC_MODE_64 = 1 << 3, // 64-bit mode - // ppc + // ppc UC_MODE_PPC32 = 1 << 2, // 32-bit mode (currently unsupported) UC_MODE_PPC64 = 1 << 3, // 64-bit mode (currently unsupported) UC_MODE_QPX = 1 << 4, // Quad Processing eXtensions mode (currently unsupported) @@ -126,6 +128,9 @@ typedef enum uc_mode { UC_MODE_SPARC64 = 1 << 3, // 64-bit mode UC_MODE_V9 = 1 << 4, // SparcV9 mode (currently unsupported) // m68k + // risc-v + UC_MODE_RISCV32 = 1 << 2, // 32-bit mode + UC_MODE_RISCV64 = 1 << 3, // 64-bit mode } uc_mode; // All type of errors encountered by Unicorn API. diff --git a/qemu/aarch64.h b/qemu/aarch64.h index f75ad9e0..fd117a2c 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -217,7 +217,6 @@ #define clz32 clz32_aarch64 #define clz64 clz64_aarch64 #define cmp_flatrange_addr cmp_flatrange_addr_aarch64 -#define code_gen_alloc code_gen_alloc_aarch64 #define commonNaNToFloat128 commonNaNToFloat128_aarch64 #define commonNaNToFloat16 commonNaNToFloat16_aarch64 #define commonNaNToFloat32 commonNaNToFloat32_aarch64 @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_aarch64 #define cpu_exec_step_atomic cpu_exec_step_atomic_aarch64 #define cpu_flush_icache_range cpu_flush_icache_range_aarch64 -#define cpu_gen_init cpu_gen_init_aarch64 #define cpu_get_address_space cpu_get_address_space_aarch64 #define cpu_get_clock cpu_get_clock_aarch64 #define cpu_get_real_ticks cpu_get_real_ticks_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index 9a2f57be..a60981c7 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -217,7 +217,6 @@ #define clz32 clz32_aarch64eb #define clz64 clz64_aarch64eb #define cmp_flatrange_addr cmp_flatrange_addr_aarch64eb -#define code_gen_alloc code_gen_alloc_aarch64eb #define commonNaNToFloat128 commonNaNToFloat128_aarch64eb #define commonNaNToFloat16 commonNaNToFloat16_aarch64eb #define commonNaNToFloat32 commonNaNToFloat32_aarch64eb @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_aarch64eb #define cpu_exec_step_atomic cpu_exec_step_atomic_aarch64eb #define cpu_flush_icache_range cpu_flush_icache_range_aarch64eb -#define cpu_gen_init cpu_gen_init_aarch64eb #define cpu_get_address_space cpu_get_address_space_aarch64eb #define cpu_get_clock cpu_get_clock_aarch64eb #define cpu_get_real_ticks cpu_get_real_ticks_aarch64eb diff --git a/qemu/accel.c b/qemu/accel.c index 0260374b..d8659165 100644 --- a/qemu/accel.c +++ b/qemu/accel.c @@ -36,7 +36,6 @@ #define TCG_TB_SIZE 0 static bool tcg_allowed = true; -static int tcg_init(MachineState *ms); static AccelClass *accel_find(struct uc_struct *uc, const char *opt_name); static int accel_init_machine(AccelClass *acc, MachineState *ms); static void tcg_accel_class_init(struct uc_struct *uc, ObjectClass *oc, void *data); diff --git a/qemu/arm.h b/qemu/arm.h index 02a7bf5c..ee1028e1 100644 --- a/qemu/arm.h +++ b/qemu/arm.h @@ -217,7 +217,6 @@ #define clz32 clz32_arm #define clz64 clz64_arm #define cmp_flatrange_addr cmp_flatrange_addr_arm -#define code_gen_alloc code_gen_alloc_arm #define commonNaNToFloat128 commonNaNToFloat128_arm #define commonNaNToFloat16 commonNaNToFloat16_arm #define commonNaNToFloat32 commonNaNToFloat32_arm @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_arm #define cpu_exec_step_atomic cpu_exec_step_atomic_arm #define cpu_flush_icache_range cpu_flush_icache_range_arm -#define cpu_gen_init cpu_gen_init_arm #define cpu_get_address_space cpu_get_address_space_arm #define cpu_get_clock cpu_get_clock_arm #define cpu_get_real_ticks cpu_get_real_ticks_arm diff --git a/qemu/armeb.h b/qemu/armeb.h index 7f2473a9..d6c0cd5e 100644 --- a/qemu/armeb.h +++ b/qemu/armeb.h @@ -217,7 +217,6 @@ #define clz32 clz32_armeb #define clz64 clz64_armeb #define cmp_flatrange_addr cmp_flatrange_addr_armeb -#define code_gen_alloc code_gen_alloc_armeb #define commonNaNToFloat128 commonNaNToFloat128_armeb #define commonNaNToFloat16 commonNaNToFloat16_armeb #define commonNaNToFloat32 commonNaNToFloat32_armeb @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_armeb #define cpu_exec_step_atomic cpu_exec_step_atomic_armeb #define cpu_flush_icache_range cpu_flush_icache_range_armeb -#define cpu_gen_init cpu_gen_init_armeb #define cpu_get_address_space cpu_get_address_space_armeb #define cpu_get_clock cpu_get_clock_armeb #define cpu_get_real_ticks cpu_get_real_ticks_armeb diff --git a/qemu/configure b/qemu/configure index 4ea7cefc..d53ff09a 100755 --- a/qemu/configure +++ b/qemu/configure @@ -1659,6 +1659,15 @@ case "$target_name" in TARGET_BASE_ARCH=ppc echo "TARGET_ABI32=y" >> $config_target_mak ;; + riscv32) + TARGET_BASE_ARCH=riscv + TARGET_ABI_DIR=riscv + echo "TARGET_ABI32=y" >> $config_target_mak + ;; + riscv64) + TARGET_BASE_ARCH=riscv + TARGET_ABI_DIR=riscv + ;; sh4|sh4eb) TARGET_ARCH=sh4 bflt="yes" diff --git a/qemu/default-configs/riscv32-softmmu.mak b/qemu/default-configs/riscv32-softmmu.mak new file mode 100644 index 00000000..62fbfd64 --- /dev/null +++ b/qemu/default-configs/riscv32-softmmu.mak @@ -0,0 +1,5 @@ +# Default configuration for riscv-softmmu + +CONFIG_SERIAL=y +CONFIG_VIRTIO_MMIO=y +CONFIG_CADENCE=y diff --git a/qemu/default-configs/riscv64-softmmu.mak b/qemu/default-configs/riscv64-softmmu.mak new file mode 100644 index 00000000..62fbfd64 --- /dev/null +++ b/qemu/default-configs/riscv64-softmmu.mak @@ -0,0 +1,5 @@ +# Default configuration for riscv-softmmu + +CONFIG_SERIAL=y +CONFIG_VIRTIO_MMIO=y +CONFIG_CADENCE=y diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 89d52a6c..7f6e3a33 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -223,7 +223,6 @@ symbols = ( 'clz32', 'clz64', 'cmp_flatrange_addr', - 'code_gen_alloc', 'commonNaNToFloat128', 'commonNaNToFloat16', 'commonNaNToFloat32', @@ -287,7 +286,6 @@ symbols = ( 'cpu_exec_init_all', 'cpu_exec_step_atomic', 'cpu_flush_icache_range', - 'cpu_gen_init', 'cpu_get_address_space', 'cpu_get_clock', 'cpu_get_real_ticks', @@ -5134,6 +5132,85 @@ mips_symbols = ( 'sync_c0_status', ) +riscv_symbols = ( + 'RISCV32_REGS_STORAGE_SIZE', + 'RISCV64_REGS_STORAGE_SIZE', + 'cpu_riscv_get_fflags', + 'cpu_riscv_set_fflags', + 'csr_read_helper', + 'csr_write_helper', + 'do_raise_exception_err', + 'helper_csrrc', + 'helper_csrrs', + 'helper_csrrw', + 'helper_fadd_d', + 'helper_fadd_s', + 'helper_fclass_d', + 'helper_fclass_s', + 'helper_fcvt_d_s', + 'helper_fcvt_d_w', + 'helper_fcvt_d_wu', + 'helper_fcvt_s_d', + 'helper_fcvt_s_w', + 'helper_fcvt_s_wu', + 'helper_fcvt_w_d', + 'helper_fcvt_w_s', + 'helper_fcvt_wu_d', + 'helper_fcvt_wu_s', + 'helper_fdiv_d', + 'helper_fdiv_s', + 'helper_feq_d', + 'helper_feq_s', + 'helper_fle_d', + 'helper_fle_s', + 'helper_flt_d', + 'helper_flt_s', + 'helper_fmadd_d', + 'helper_fmadd_s', + 'helper_fmsub_d', + 'helper_fmsub_s', + 'helper_fmax_d', + 'helper_fmax_s', + 'helper_fmin_d', + 'helper_fmin_s', + 'helper_fmul_d', + 'helper_fmul_s', + 'helper_fnmadd_d', + 'helper_fnmadd_s', + 'helper_fnmsub_d', + 'helper_fnmsub_s', + 'helper_fsqrt_d', + 'helper_fsqrt_s', + 'helper_fsub_d', + 'helper_fsub_s', + 'helper_mret', + 'helper_riscv_tlb_flush', + 'helper_set_rounding_mode', + 'helper_sret', + 'pmp_hart_has_privs', + 'pmpaddr_csr_read', + 'pmpaddr_csr_write', + 'pmpcfg_csr_read', + 'pmpcfg_csr_write', + 'riscv_cpu_do_interrupt', + 'riscv_cpu_do_unaligned_access', + 'riscv_cpu_exec_interrupt', + 'riscv_cpu_get_phys_page_debug', + 'riscv_cpu_handle_mmu_fault', + 'riscv_cpu_list', + 'riscv_cpu_mmu_index', + 'riscv_cpu_register_types', + 'riscv_excp_names', + 'riscv_fpr_regnames', + 'riscv_int_regnames', + 'riscv_intr_names', + 'riscv_isa_string', + 'riscv_set_local_interrupt', + 'riscv_set_mode', + 'riscv_translate_init', + 'spike_v1_10_0_machine_init_register_types', +) + sparc_symbols = ( 'cpu_cwp_dec', 'cpu_cwp_inc', @@ -5232,6 +5309,10 @@ if __name__ == '__main__': for s in mips_symbols: print("#define %s %s_%s" %(s, s, arch)) + if 'riscv' in arch: + for s in riscv_symbols: + print("#define %s %s_%s" %(s, s, arch)) + if 'sparc' in arch: for s in sparc_symbols: print("#define %s %s_%s" %(s, s, arch)) diff --git a/qemu/hw/riscv/Makefile.objs b/qemu/hw/riscv/Makefile.objs new file mode 100644 index 00000000..2f669515 --- /dev/null +++ b/qemu/hw/riscv/Makefile.objs @@ -0,0 +1 @@ +obj-y += spike.o \ No newline at end of file diff --git a/qemu/hw/riscv/spike.c b/qemu/hw/riscv/spike.c new file mode 100644 index 00000000..d8f32233 --- /dev/null +++ b/qemu/hw/riscv/spike.c @@ -0,0 +1,55 @@ +/* + * QEMU RISC-V Spike Board + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This provides a RISC-V Board with the following devices: + * + * 0) HTIF Console and Poweroff + * 1) CLINT (Timer and IPI) + * 2) PLIC (Platform Level Interrupt Controller) + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu-common.h" +#include "cpu.h" +#include "hw/riscv/spike.h" +#include "hw/boards.h" +#include "exec/address-spaces.h" + +static int spike_v1_10_0_board_init(struct uc_struct *uc, MachineState *machine) +{ + uc->cpu = cpu_create(uc, machine->cpu_type); + + if (uc->cpu == NULL) { + fprintf(stderr, "Unable to make CPU definition\n"); + return -1; + } + + return 0; +} + +static void spike_v1_10_0_machine_init(struct uc_struct *uc, MachineClass *mc) +{ + mc->init = spike_v1_10_0_board_init; + mc->max_cpus = 1; + mc->is_default = 1; + mc->default_cpu_type = SPIKE_V1_10_0_CPU; + mc->arch = UC_ARCH_RISCV; +} + +DEFINE_MACHINE("spike_v1.10", spike_v1_10_0_machine_init) diff --git a/qemu/include/hw/riscv/spike.h b/qemu/include/hw/riscv/spike.h new file mode 100644 index 00000000..f8b5d5a3 --- /dev/null +++ b/qemu/include/hw/riscv/spike.h @@ -0,0 +1,16 @@ +#ifndef HW_RISCV_H +#define HW_RISCV_H + +#if defined(TARGET_RISCV32) +#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV32GCSU_V1_09_1 +#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 +#elif defined(TARGET_RISCV64) +#define SPIKE_V1_09_1_CPU TYPE_RISCV_CPU_RV64GCSU_V1_09_1 +#define SPIKE_V1_10_0_CPU TYPE_RISCV_CPU_RV64GCSU_V1_10_0 +#endif + +void spike_v1_10_0_machine_init_register_types(struct uc_struct *uc); + +void riscv_cpu_register_types(void *opaque); + +#endif /* HW_ARM_H */ diff --git a/qemu/m68k.h b/qemu/m68k.h index b6651d30..c4b77238 100644 --- a/qemu/m68k.h +++ b/qemu/m68k.h @@ -217,7 +217,6 @@ #define clz32 clz32_m68k #define clz64 clz64_m68k #define cmp_flatrange_addr cmp_flatrange_addr_m68k -#define code_gen_alloc code_gen_alloc_m68k #define commonNaNToFloat128 commonNaNToFloat128_m68k #define commonNaNToFloat16 commonNaNToFloat16_m68k #define commonNaNToFloat32 commonNaNToFloat32_m68k @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_m68k #define cpu_exec_step_atomic cpu_exec_step_atomic_m68k #define cpu_flush_icache_range cpu_flush_icache_range_m68k -#define cpu_gen_init cpu_gen_init_m68k #define cpu_get_address_space cpu_get_address_space_m68k #define cpu_get_clock cpu_get_clock_m68k #define cpu_get_real_ticks cpu_get_real_ticks_m68k diff --git a/qemu/mips.h b/qemu/mips.h index e29e8501..67cae3a6 100644 --- a/qemu/mips.h +++ b/qemu/mips.h @@ -217,7 +217,6 @@ #define clz32 clz32_mips #define clz64 clz64_mips #define cmp_flatrange_addr cmp_flatrange_addr_mips -#define code_gen_alloc code_gen_alloc_mips #define commonNaNToFloat128 commonNaNToFloat128_mips #define commonNaNToFloat16 commonNaNToFloat16_mips #define commonNaNToFloat32 commonNaNToFloat32_mips @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_mips #define cpu_exec_step_atomic cpu_exec_step_atomic_mips #define cpu_flush_icache_range cpu_flush_icache_range_mips -#define cpu_gen_init cpu_gen_init_mips #define cpu_get_address_space cpu_get_address_space_mips #define cpu_get_clock cpu_get_clock_mips #define cpu_get_real_ticks cpu_get_real_ticks_mips diff --git a/qemu/mips64.h b/qemu/mips64.h index 1d6e4589..7befc2bc 100644 --- a/qemu/mips64.h +++ b/qemu/mips64.h @@ -217,7 +217,6 @@ #define clz32 clz32_mips64 #define clz64 clz64_mips64 #define cmp_flatrange_addr cmp_flatrange_addr_mips64 -#define code_gen_alloc code_gen_alloc_mips64 #define commonNaNToFloat128 commonNaNToFloat128_mips64 #define commonNaNToFloat16 commonNaNToFloat16_mips64 #define commonNaNToFloat32 commonNaNToFloat32_mips64 @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_mips64 #define cpu_exec_step_atomic cpu_exec_step_atomic_mips64 #define cpu_flush_icache_range cpu_flush_icache_range_mips64 -#define cpu_gen_init cpu_gen_init_mips64 #define cpu_get_address_space cpu_get_address_space_mips64 #define cpu_get_clock cpu_get_clock_mips64 #define cpu_get_real_ticks cpu_get_real_ticks_mips64 diff --git a/qemu/mips64el.h b/qemu/mips64el.h index 42a3b825..179ac003 100644 --- a/qemu/mips64el.h +++ b/qemu/mips64el.h @@ -217,7 +217,6 @@ #define clz32 clz32_mips64el #define clz64 clz64_mips64el #define cmp_flatrange_addr cmp_flatrange_addr_mips64el -#define code_gen_alloc code_gen_alloc_mips64el #define commonNaNToFloat128 commonNaNToFloat128_mips64el #define commonNaNToFloat16 commonNaNToFloat16_mips64el #define commonNaNToFloat32 commonNaNToFloat32_mips64el @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_mips64el #define cpu_exec_step_atomic cpu_exec_step_atomic_mips64el #define cpu_flush_icache_range cpu_flush_icache_range_mips64el -#define cpu_gen_init cpu_gen_init_mips64el #define cpu_get_address_space cpu_get_address_space_mips64el #define cpu_get_clock cpu_get_clock_mips64el #define cpu_get_real_ticks cpu_get_real_ticks_mips64el diff --git a/qemu/mipsel.h b/qemu/mipsel.h index 1481951b..1f5b5ec2 100644 --- a/qemu/mipsel.h +++ b/qemu/mipsel.h @@ -217,7 +217,6 @@ #define clz32 clz32_mipsel #define clz64 clz64_mipsel #define cmp_flatrange_addr cmp_flatrange_addr_mipsel -#define code_gen_alloc code_gen_alloc_mipsel #define commonNaNToFloat128 commonNaNToFloat128_mipsel #define commonNaNToFloat16 commonNaNToFloat16_mipsel #define commonNaNToFloat32 commonNaNToFloat32_mipsel @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_mipsel #define cpu_exec_step_atomic cpu_exec_step_atomic_mipsel #define cpu_flush_icache_range cpu_flush_icache_range_mipsel -#define cpu_gen_init cpu_gen_init_mipsel #define cpu_get_address_space cpu_get_address_space_mipsel #define cpu_get_clock cpu_get_clock_mipsel #define cpu_get_real_ticks cpu_get_real_ticks_mipsel diff --git a/qemu/powerpc.h b/qemu/powerpc.h index 07d5f3c8..332c953e 100644 --- a/qemu/powerpc.h +++ b/qemu/powerpc.h @@ -217,7 +217,6 @@ #define clz32 clz32_powerpc #define clz64 clz64_powerpc #define cmp_flatrange_addr cmp_flatrange_addr_powerpc -#define code_gen_alloc code_gen_alloc_powerpc #define commonNaNToFloat128 commonNaNToFloat128_powerpc #define commonNaNToFloat16 commonNaNToFloat16_powerpc #define commonNaNToFloat32 commonNaNToFloat32_powerpc @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_powerpc #define cpu_exec_step_atomic cpu_exec_step_atomic_powerpc #define cpu_flush_icache_range cpu_flush_icache_range_powerpc -#define cpu_gen_init cpu_gen_init_powerpc #define cpu_get_address_space cpu_get_address_space_powerpc #define cpu_get_clock cpu_get_clock_powerpc #define cpu_get_real_ticks cpu_get_real_ticks_powerpc diff --git a/qemu/riscv32.h b/qemu/riscv32.h new file mode 100644 index 00000000..cbb0bde6 --- /dev/null +++ b/qemu/riscv32.h @@ -0,0 +1,3343 @@ +/* Autogen header for Unicorn Engine - DONOT MODIFY */ +#ifndef UNICORN_AUTOGEN_RISCV32_H +#define UNICORN_AUTOGEN_RISCV32_H +#define ErrorClass_lookup ErrorClass_lookup_riscv32 +#define S0 S0_riscv32 +#define S1 S1_riscv32 +#define X86CPURegister32_lookup X86CPURegister32_lookup_riscv32 +#define _DYNAMIC _DYNAMIC_riscv32 +#define _GLOBAL_OFFSET_TABLE_ _GLOBAL_OFFSET_TABLE__riscv32 +#define __jit_debug_descriptor __jit_debug_descriptor_riscv32 +#define __jit_debug_register_code __jit_debug_register_code_riscv32 +#define _edata _edata_riscv32 +#define _end _end_riscv32 +#define _fini _fini_riscv32 +#define _init _init_riscv32 +#define a15_l2ctlr_read a15_l2ctlr_read_riscv32 +#define a64_translate_init a64_translate_init_riscv32 +#define aa32_generate_debug_exceptions aa32_generate_debug_exceptions_riscv32 +#define aa64_cacheop_access aa64_cacheop_access_riscv32 +#define aa64_daif_access aa64_daif_access_riscv32 +#define aa64_daif_write aa64_daif_write_riscv32 +#define aa64_dczid_read aa64_dczid_read_riscv32 +#define aa64_fpcr_read aa64_fpcr_read_riscv32 +#define aa64_fpcr_write aa64_fpcr_write_riscv32 +#define aa64_fpsr_read aa64_fpsr_read_riscv32 +#define aa64_fpsr_write aa64_fpsr_write_riscv32 +#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_riscv32 +#define aa64_zva_access aa64_zva_access_riscv32 +#define aarch64_banked_spsr_index aarch64_banked_spsr_index_riscv32 +#define aarch64_restore_sp aarch64_restore_sp_riscv32 +#define aarch64_save_sp aarch64_save_sp_riscv32 +#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_riscv32 +#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_riscv32 +#define aarch64_tb_set_jmp_target aarch64_tb_set_jmp_target_riscv32 +#define accel_find accel_find_riscv32 +#define accel_init_machine accel_init_machine_riscv32 +#define accel_type accel_type_riscv32 +#define access_with_adjusted_size access_with_adjusted_size_riscv32 +#define add128 add128_riscv32 +#define add16_sat add16_sat_riscv32 +#define add16_usat add16_usat_riscv32 +#define add192 add192_riscv32 +#define add8_sat add8_sat_riscv32 +#define add8_usat add8_usat_riscv32 +#define addFloat128Sigs addFloat128Sigs_riscv32 +#define addFloat32Sigs addFloat32Sigs_riscv32 +#define addFloat64Sigs addFloat64Sigs_riscv32 +#define addFloatx80Sigs addFloatx80Sigs_riscv32 +#define add_cpreg_to_hashtable add_cpreg_to_hashtable_riscv32 +#define add_cpreg_to_list add_cpreg_to_list_riscv32 +#define add_qemu_ldst_label add_qemu_ldst_label_riscv32 +#define address_space_access_valid address_space_access_valid_riscv32 +#define address_space_cache_destroy address_space_cache_destroy_riscv32 +#define address_space_cache_init address_space_cache_init_riscv32 +#define address_space_cache_invalidate address_space_cache_invalidate_riscv32 +#define address_space_destroy address_space_destroy_riscv32 +#define address_space_dispatch_compact address_space_dispatch_compact_riscv32 +#define address_space_dispatch_free address_space_dispatch_free_riscv32 +#define address_space_dispatch_new address_space_dispatch_new_riscv32 +#define address_space_get_flatview address_space_get_flatview_riscv32 +#define address_space_init address_space_init_riscv32 +#define address_space_init_dispatch address_space_init_dispatch_riscv32 +#define address_space_get_iotlb_entry address_space_get_iotlb_entry_riscv32 +#define address_space_ldl address_space_ldl_riscv32 +#define address_space_ldl_be address_space_ldl_be_riscv32 +#define address_space_ldl_be_cached address_space_ldl_be_cached_riscv32 +#define address_space_ldl_cached address_space_ldl_cached_riscv32 +#define address_space_ldl_le address_space_ldl_le_riscv32 +#define address_space_ldl_le_cached address_space_ldl_le_cached_riscv32 +#define address_space_ldq address_space_ldq_riscv32 +#define address_space_ldq_be address_space_ldq_be_riscv32 +#define address_space_ldq_be_cached address_space_ldq_be_cached_riscv32 +#define address_space_ldq_cached address_space_ldq_cached_riscv32 +#define address_space_ldq_le address_space_ldq_le_riscv32 +#define address_space_ldq_le_cached address_space_ldq_le_cached_riscv32 +#define address_space_ldub address_space_ldub_riscv32 +#define address_space_ldub_cached address_space_ldub_cached_riscv32 +#define address_space_lduw address_space_lduw_riscv32 +#define address_space_lduw_be address_space_lduw_be_riscv32 +#define address_space_lduw_be_cached address_space_lduw_be_cached_riscv32 +#define address_space_lduw_cached address_space_lduw_cached_riscv32 +#define address_space_lduw_le address_space_lduw_le_riscv32 +#define address_space_lduw_le_cached address_space_lduw_le_cached_riscv32 +#define address_space_lookup_region address_space_lookup_region_riscv32 +#define address_space_map address_space_map_riscv32 +#define address_space_rw address_space_rw_riscv32 +#define address_space_stb address_space_stb_riscv32 +#define address_space_stb_cached address_space_stb_cached_riscv32 +#define address_space_stl address_space_stl_riscv32 +#define address_space_stl_be address_space_stl_be_riscv32 +#define address_space_stl_be_cached address_space_stl_be_cached_riscv32 +#define address_space_stl_cached address_space_stl_cached_riscv32 +#define address_space_stl_le address_space_stl_le_riscv32 +#define address_space_stl_le_cached address_space_stl_le_cached_riscv32 +#define address_space_stl_notdirty address_space_stl_notdirty_riscv32 +#define address_space_stl_notdirty_cached address_space_stl_notdirty_cached_riscv32 +#define address_space_stq address_space_stq_riscv32 +#define address_space_stq_be address_space_stq_be_riscv32 +#define address_space_stq_be_cached address_space_stq_be_cached_riscv32 +#define address_space_stq_cached address_space_stq_cached_riscv32 +#define address_space_stq_le address_space_stq_le_riscv32 +#define address_space_stq_le_cached address_space_stq_le_cached_riscv32 +#define address_space_stw address_space_stw_riscv32 +#define address_space_stw_be address_space_stw_be_riscv32 +#define address_space_stw_be_cached address_space_stw_be_cached_riscv32 +#define address_space_stw_cached address_space_stw_cached_riscv32 +#define address_space_stw_le address_space_stw_le_riscv32 +#define address_space_stw_le_cached address_space_stw_le_cached_riscv32 +#define address_space_to_dispatch address_space_to_dispatch_riscv32 +#define address_space_to_flatview address_space_to_flatview_riscv32 +#define address_space_translate_for_iotlb address_space_translate_for_iotlb_riscv32 +#define address_space_translate_internal address_space_translate_internal_riscv32 +#define address_space_unmap address_space_unmap_riscv32 +#define address_space_unregister address_space_unregister_riscv32 +#define address_space_update_topology address_space_update_topology_riscv32 +#define address_space_update_topology_pass address_space_update_topology_pass_riscv32 +#define address_space_write address_space_write_riscv32 +#define addrrange_contains addrrange_contains_riscv32 +#define addrrange_end addrrange_end_riscv32 +#define addrrange_equal addrrange_equal_riscv32 +#define addrrange_intersection addrrange_intersection_riscv32 +#define addrrange_intersects addrrange_intersects_riscv32 +#define addrrange_make addrrange_make_riscv32 +#define adjust_endianness adjust_endianness_riscv32 +#define all_helpers all_helpers_riscv32 +#define alloc_code_gen_buffer alloc_code_gen_buffer_riscv32 +#define alloc_entry alloc_entry_riscv32 +#define always_true always_true_riscv32 +#define arm1026_initfn arm1026_initfn_riscv32 +#define arm1136_initfn arm1136_initfn_riscv32 +#define arm1136_r2_initfn arm1136_r2_initfn_riscv32 +#define arm1176_initfn arm1176_initfn_riscv32 +#define arm11mpcore_initfn arm11mpcore_initfn_riscv32 +#define arm926_initfn arm926_initfn_riscv32 +#define arm946_initfn arm946_initfn_riscv32 +#define arm_adjust_watchpoint_address arm_adjust_watchpoint_address_riscv32 +#define arm_ccnt_enabled arm_ccnt_enabled_riscv32 +#define arm_cp_read_zero arm_cp_read_zero_riscv32 +#define arm_cp_reset_ignore arm_cp_reset_ignore_riscv32 +#define arm_cp_write_ignore arm_cp_write_ignore_riscv32 +#define arm_cpu_do_interrupt arm_cpu_do_interrupt_riscv32 +#define arm_cpu_do_transaction_failed arm_cpu_do_transaction_failed_riscv32 +#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_riscv32 +#define arm_cpu_exec_interrupt arm_cpu_exec_interrupt_riscv32 +#define arm_cpu_finalizefn arm_cpu_finalizefn_riscv32 +#define arm_cpu_get_phys_page_attrs_debug arm_cpu_get_phys_page_attrs_debug_riscv32 +#define arm_cpu_initfn arm_cpu_initfn_riscv32 +#define arm_cpu_list arm_cpu_list_riscv32 +#define arm_cpu_post_init arm_cpu_post_init_riscv32 +#define arm_cpu_realizefn arm_cpu_realizefn_riscv32 +#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_riscv32 +#define arm_cpu_register_types arm_cpu_register_types_riscv32 +#define arm_cpu_set_pc arm_cpu_set_pc_riscv32 +#define arm_cpus arm_cpus_riscv32 +#define arm_current_el arm_current_el_riscv32 +#define arm_dc_feature arm_dc_feature_riscv32 +#define arm_debug_check_watchpoint arm_debug_check_watchpoint_riscv32 +#define arm_debug_excp_handler arm_debug_excp_handler_riscv32 +#define arm_debug_target_el arm_debug_target_el_riscv32 +#define arm_el_is_aa64 arm_el_is_aa64_riscv32 +#define arm_env_get_cpu arm_env_get_cpu_riscv32 +#define arm_excp_unmasked arm_excp_unmasked_riscv32 +#define arm_feature arm_feature_riscv32 +#define arm_free_cc arm_free_cc_riscv32 +#define arm_gen_test_cc arm_gen_test_cc_riscv32 +#define arm_generate_debug_exceptions arm_generate_debug_exceptions_riscv32 +#define arm_gt_htimer_cb arm_gt_htimer_cb_riscv32 +#define arm_gt_ptimer_cb arm_gt_ptimer_cb_riscv32 +#define arm_gt_stimer_cb arm_gt_stimer_cb_riscv32 +#define arm_gt_vtimer_cb arm_gt_vtimer_cb_riscv32 +#define arm_handle_psci_call arm_handle_psci_call_riscv32 +#define arm_is_psci_call arm_is_psci_call_riscv32 +#define arm_is_secure arm_is_secure_riscv32 +#define arm_is_secure_below_el3 arm_is_secure_below_el3_riscv32 +#define arm_jump_cc arm_jump_cc_riscv32 +#define arm_ldl_code arm_ldl_code_riscv32 +#define arm_lduw_code arm_lduw_code_riscv32 +#define arm_log_exception arm_log_exception_riscv32 +#define arm_phys_excp_target_el arm_phys_excp_target_el_riscv32 +#define arm_reg_read arm_reg_read_riscv32 +#define arm_reg_reset arm_reg_reset_riscv32 +#define arm_reg_write arm_reg_write_riscv32 +#define arm_release arm_release_riscv32 +#define arm_rmode_to_sf arm_rmode_to_sf_riscv32 +#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_riscv32 +#define arm_singlestep_active arm_singlestep_active_riscv32 +#define arm_test_cc arm_test_cc_riscv32 +#define arm_tlb_fill arm_tlb_fill_riscv32 +#define arm_translate_init arm_translate_init_riscv32 +#define arm_v7m_class_init arm_v7m_class_init_riscv32 +#define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_riscv32 +#define ats_access ats_access_riscv32 +#define ats_write ats_write_riscv32 +#define bad_mode_switch bad_mode_switch_riscv32 +#define bank_number bank_number_riscv32 +#define bitmap_zero_extend bitmap_zero_extend_riscv32 +#define bp_wp_matches bp_wp_matches_riscv32 +#define breakpoint_invalidate breakpoint_invalidate_riscv32 +#define build_page_bitmap build_page_bitmap_riscv32 +#define bus_add_child bus_add_child_riscv32 +#define bus_class_init bus_class_init_riscv32 +#define bus_info bus_info_riscv32 +#define bus_unparent bus_unparent_riscv32 +#define cache_block_ops_cp_reginfo cache_block_ops_cp_reginfo_riscv32 +#define cache_dirty_status_cp_reginfo cache_dirty_status_cp_reginfo_riscv32 +#define cache_test_clean_cp_reginfo cache_test_clean_cp_reginfo_riscv32 +#define call_recip_estimate call_recip_estimate_riscv32 +#define can_merge can_merge_riscv32 +#define capacity_increase capacity_increase_riscv32 +#define ccsidr_read ccsidr_read_riscv32 +#define check_ap check_ap_riscv32 +#define check_breakpoints check_breakpoints_riscv32 +#define check_exit_request check_exit_request_riscv32 +#define check_watchpoints check_watchpoints_riscv32 +#define cho cho_riscv32 +#define clear_bit clear_bit_riscv32 +#define clz32 clz32_riscv32 +#define clz64 clz64_riscv32 +#define cmp_flatrange_addr cmp_flatrange_addr_riscv32 +#define commonNaNToFloat128 commonNaNToFloat128_riscv32 +#define commonNaNToFloat16 commonNaNToFloat16_riscv32 +#define commonNaNToFloat32 commonNaNToFloat32_riscv32 +#define commonNaNToFloat64 commonNaNToFloat64_riscv32 +#define commonNaNToFloatx80 commonNaNToFloatx80_riscv32 +#define compute_abs_deadline compute_abs_deadline_riscv32 +#define cond_name cond_name_riscv32 +#define configure_accelerator configure_accelerator_riscv32 +#define container_get container_get_riscv32 +#define container_info container_info_riscv32 +#define container_register_types container_register_types_riscv32 +#define contextidr_write contextidr_write_riscv32 +#define core_log_global_start core_log_global_start_riscv32 +#define core_log_global_stop core_log_global_stop_riscv32 +#define core_memory_listener core_memory_listener_riscv32 +#define cortex_a15_initfn cortex_a15_initfn_riscv32 +#define cortex_a8_initfn cortex_a8_initfn_riscv32 +#define cortex_a9_initfn cortex_a9_initfn_riscv32 +#define cortex_m3_initfn cortex_m3_initfn_riscv32 +#define cortexa15_cp_reginfo cortexa15_cp_reginfo_riscv32 +#define cortexa8_cp_reginfo cortexa8_cp_reginfo_riscv32 +#define cortexa9_cp_reginfo cortexa9_cp_reginfo_riscv32 +#define countLeadingZeros32 countLeadingZeros32_riscv32 +#define countLeadingZeros64 countLeadingZeros64_riscv32 +#define count_cpreg count_cpreg_riscv32 +#define cp_access_ok cp_access_ok_riscv32 +#define cp_reg_reset cp_reg_reset_riscv32 +#define cp_reginfo cp_reginfo_riscv32 +#define cpacr_write cpacr_write_riscv32 +#define cpreg_field_is_64bit cpreg_field_is_64bit_riscv32 +#define cpreg_key_compare cpreg_key_compare_riscv32 +#define cpreg_make_keylist cpreg_make_keylist_riscv32 +#define cpreg_to_kvm_id cpreg_to_kvm_id_riscv32 +#define cpsr_read cpsr_read_riscv32 +#define cpsr_write cpsr_write_riscv32 +#define cptype_valid cptype_valid_riscv32 +#define cpu_abort cpu_abort_riscv32 +#define cpu_address_space_init cpu_address_space_init_riscv32 +#define cpu_breakpoint_insert cpu_breakpoint_insert_riscv32 +#define cpu_breakpoint_remove cpu_breakpoint_remove_riscv32 +#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_riscv32 +#define cpu_breakpoint_remove_by_ref cpu_breakpoint_remove_by_ref_riscv32 +#define cpu_can_do_io cpu_can_do_io_riscv32 +#define cpu_can_run cpu_can_run_riscv32 +#define cpu_class_init cpu_class_init_riscv32 +#define cpu_common_class_by_name cpu_common_class_by_name_riscv32 +#define cpu_common_exec_interrupt cpu_common_exec_interrupt_riscv32 +#define cpu_common_get_arch_id cpu_common_get_arch_id_riscv32 +#define cpu_common_get_memory_mapping cpu_common_get_memory_mapping_riscv32 +#define cpu_common_get_paging_enabled cpu_common_get_paging_enabled_riscv32 +#define cpu_common_has_work cpu_common_has_work_riscv32 +#define cpu_common_initfn cpu_common_initfn_riscv32 +#define cpu_common_noop cpu_common_noop_riscv32 +#define cpu_common_parse_features cpu_common_parse_features_riscv32 +#define cpu_common_realizefn cpu_common_realizefn_riscv32 +#define cpu_common_reset cpu_common_reset_riscv32 +#define cpu_dump_statistics cpu_dump_statistics_riscv32 +#define cpu_exec cpu_exec_riscv32 +#define cpu_exec_exit cpu_exec_exit_riscv32 +#define cpu_exec_init cpu_exec_init_riscv32 +#define cpu_exec_init_all cpu_exec_init_all_riscv32 +#define cpu_exec_step_atomic cpu_exec_step_atomic_riscv32 +#define cpu_flush_icache_range cpu_flush_icache_range_riscv32 +#define cpu_get_address_space cpu_get_address_space_riscv32 +#define cpu_get_clock cpu_get_clock_riscv32 +#define cpu_get_real_ticks cpu_get_real_ticks_riscv32 +#define cpu_get_tb_cpu_state cpu_get_tb_cpu_state_riscv32 +#define cpu_handle_debug_exception cpu_handle_debug_exception_riscv32 +#define cpu_handle_guest_debug cpu_handle_guest_debug_riscv32 +#define cpu_inb cpu_inb_riscv32 +#define cpu_inl cpu_inl_riscv32 +#define cpu_interrupt cpu_interrupt_riscv32 +#define cpu_interrupt_handler cpu_interrupt_handler_riscv32 +#define cpu_inw cpu_inw_riscv32 +#define cpu_io_recompile cpu_io_recompile_riscv32 +#define cpu_is_stopped cpu_is_stopped_riscv32 +#define cpu_ldl_code cpu_ldl_code_riscv32 +#define cpu_ldub_code cpu_ldub_code_riscv32 +#define cpu_lduw_code cpu_lduw_code_riscv32 +#define cpu_loop_exit cpu_loop_exit_riscv32 +#define cpu_loop_exit_atomic cpu_loop_exit_atomic_riscv32 +#define cpu_loop_exit_noexc cpu_loop_exit_noexc_riscv32 +#define cpu_loop_exit_restore cpu_loop_exit_restore_riscv32 +#define cpu_memory_rw_debug cpu_memory_rw_debug_riscv32 +#define cpu_mmu_index cpu_mmu_index_riscv32 +#define cpu_outb cpu_outb_riscv32 +#define cpu_outl cpu_outl_riscv32 +#define cpu_outw cpu_outw_riscv32 +#define cpu_physical_memory_all_dirty cpu_physical_memory_all_dirty_riscv32 +#define cpu_physical_memory_clear_dirty_range cpu_physical_memory_clear_dirty_range_riscv32 +#define cpu_physical_memory_is_clean cpu_physical_memory_is_clean_riscv32 +#define cpu_physical_memory_is_io cpu_physical_memory_is_io_riscv32 +#define cpu_physical_memory_map cpu_physical_memory_map_riscv32 +#define cpu_physical_memory_range_includes_clean cpu_physical_memory_range_includes_clean_riscv32 +#define cpu_physical_memory_reset_dirty cpu_physical_memory_reset_dirty_riscv32 +#define cpu_physical_memory_rw cpu_physical_memory_rw_riscv32 +#define cpu_physical_memory_unmap cpu_physical_memory_unmap_riscv32 +#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_riscv32 +#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_riscv32 +#define cpu_register cpu_register_riscv32 +#define cpu_register_types cpu_register_types_riscv32 +#define cpu_restore_state cpu_restore_state_riscv32 +#define cpu_restore_state_from_tb cpu_restore_state_from_tb_riscv32 +#define cpu_single_step cpu_single_step_riscv32 +#define cpu_tb_exec cpu_tb_exec_riscv32 +#define cpu_to_be64 cpu_to_be64_riscv32 +#define cpu_to_le32 cpu_to_le32_riscv32 +#define cpu_to_le64 cpu_to_le64_riscv32 +#define cpu_type_info cpu_type_info_riscv32 +#define cpu_unassigned_access cpu_unassigned_access_riscv32 +#define cpu_watchpoint_address_matches cpu_watchpoint_address_matches_riscv32 +#define cpu_watchpoint_insert cpu_watchpoint_insert_riscv32 +#define cpu_watchpoint_remove cpu_watchpoint_remove_riscv32 +#define cpu_watchpoint_remove_all cpu_watchpoint_remove_all_riscv32 +#define cpu_watchpoint_remove_by_ref cpu_watchpoint_remove_by_ref_riscv32 +#define crc32c_table crc32c_table_riscv32 +#define create_new_memory_mapping create_new_memory_mapping_riscv32 +#define csselr_write csselr_write_riscv32 +#define cto32 cto32_riscv32 +#define ctr_el0_access ctr_el0_access_riscv32 +#define ctz32 ctz32_riscv32 +#define ctz64 ctz64_riscv32 +#define dacr_write dacr_write_riscv32 +#define dbgbcr_write dbgbcr_write_riscv32 +#define dbgbvr_write dbgbvr_write_riscv32 +#define dbgwcr_write dbgwcr_write_riscv32 +#define dbgwvr_write dbgwvr_write_riscv32 +#define debug_cp_reginfo debug_cp_reginfo_riscv32 +#define debug_frame debug_frame_riscv32 +#define debug_lpae_cp_reginfo debug_lpae_cp_reginfo_riscv32 +#define define_arm_cp_regs define_arm_cp_regs_riscv32 +#define define_arm_cp_regs_with_opaque define_arm_cp_regs_with_opaque_riscv32 +#define define_debug_regs define_debug_regs_riscv32 +#define define_one_arm_cp_reg define_one_arm_cp_reg_riscv32 +#define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_riscv32 +#define deposit32 deposit32_riscv32 +#define deposit64 deposit64_riscv32 +#define deregister_tm_clones deregister_tm_clones_riscv32 +#define device_class_base_init device_class_base_init_riscv32 +#define device_class_init device_class_init_riscv32 +#define device_finalize device_finalize_riscv32 +#define device_get_realized device_get_realized_riscv32 +#define device_initfn device_initfn_riscv32 +#define device_post_init device_post_init_riscv32 +#define device_reset device_reset_riscv32 +#define device_set_realized device_set_realized_riscv32 +#define device_type_info device_type_info_riscv32 +#define disas_arm_insn disas_arm_insn_riscv32 +#define disas_coproc_insn disas_coproc_insn_riscv32 +#define disas_dsp_insn disas_dsp_insn_riscv32 +#define disas_iwmmxt_insn disas_iwmmxt_insn_riscv32 +#define disas_neon_data_insn disas_neon_data_insn_riscv32 +#define disas_neon_ls_insn disas_neon_ls_insn_riscv32 +#define disas_thumb2_insn disas_thumb2_insn_riscv32 +#define disas_thumb_insn disas_thumb_insn_riscv32 +#define disas_vfp_insn disas_vfp_insn_riscv32 +#define disas_vfp_v8_insn disas_vfp_v8_insn_riscv32 +#define do_arm_semihosting do_arm_semihosting_riscv32 +#define do_clz16 do_clz16_riscv32 +#define do_clz8 do_clz8_riscv32 +#define do_constant_folding do_constant_folding_riscv32 +#define do_constant_folding_2 do_constant_folding_2_riscv32 +#define do_constant_folding_cond do_constant_folding_cond_riscv32 +#define do_constant_folding_cond2 do_constant_folding_cond2_riscv32 +#define do_constant_folding_cond_32 do_constant_folding_cond_32_riscv32 +#define do_constant_folding_cond_64 do_constant_folding_cond_64_riscv32 +#define do_constant_folding_cond_eq do_constant_folding_cond_eq_riscv32 +#define do_fcvt_f16_to_f32 do_fcvt_f16_to_f32_riscv32 +#define do_fcvt_f32_to_f16 do_fcvt_f32_to_f16_riscv32 +#define do_ssat do_ssat_riscv32 +#define do_usad do_usad_riscv32 +#define do_usat do_usat_riscv32 +#define do_v7m_exception_exit do_v7m_exception_exit_riscv32 +#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_riscv32 +#define dummy_func dummy_func_riscv32 +#define dummy_section dummy_section_riscv32 +#define dup_const_impl dup_const_impl_riscv32 +#define end_list end_list_riscv32 +#define ensure_writable_pages ensure_writable_pages_riscv32 +#define eq128 eq128_riscv32 +#define error_copy error_copy_riscv32 +#define error_exit error_exit_riscv32 +#define error_get_class error_get_class_riscv32 +#define error_get_pretty error_get_pretty_riscv32 +#define error_setg_file_open_internal error_setg_file_open_internal_riscv32 +#define estimateDiv128To64 estimateDiv128To64_riscv32 +#define estimateSqrt32 estimateSqrt32_riscv32 +#define excnames excnames_riscv32 +#define excp_is_internal excp_is_internal_riscv32 +#define extended_addresses_enabled extended_addresses_enabled_riscv32 +#define extended_mpu_ap_bits extended_mpu_ap_bits_riscv32 +#define extract32 extract32_riscv32 +#define extract64 extract64_riscv32 +#define extractFloat128Exp extractFloat128Exp_riscv32 +#define extractFloat128Frac0 extractFloat128Frac0_riscv32 +#define extractFloat128Frac1 extractFloat128Frac1_riscv32 +#define extractFloat128Sign extractFloat128Sign_riscv32 +#define extractFloat16Exp extractFloat16Exp_riscv32 +#define extractFloat16Frac extractFloat16Frac_riscv32 +#define extractFloat16Sign extractFloat16Sign_riscv32 +#define extractFloat32Exp extractFloat32Exp_riscv32 +#define extractFloat32Frac extractFloat32Frac_riscv32 +#define extractFloat32Sign extractFloat32Sign_riscv32 +#define extractFloat64Exp extractFloat64Exp_riscv32 +#define extractFloat64Frac extractFloat64Frac_riscv32 +#define extractFloat64Sign extractFloat64Sign_riscv32 +#define extractFloatx80Exp extractFloatx80Exp_riscv32 +#define extractFloatx80Frac extractFloatx80Frac_riscv32 +#define extractFloatx80Sign extractFloatx80Sign_riscv32 +#define fcse_write fcse_write_riscv32 +#define find_better_copy find_better_copy_riscv32 +#define find_default_machine find_default_machine_riscv32 +#define find_desc_by_name find_desc_by_name_riscv32 +#define find_first_bit find_first_bit_riscv32 +#define find_paging_enabled_cpu find_paging_enabled_cpu_riscv32 +#define find_ram_block find_ram_block_riscv32 +#define find_ram_offset find_ram_offset_riscv32 +#define find_string find_string_riscv32 +#define find_type find_type_riscv32 +#define flatrange_equal flatrange_equal_riscv32 +#define flatview_add_to_dispatch flatview_add_to_dispatch_riscv32 +#define flatview_destroy flatview_destroy_riscv32 +#define flatview_init flatview_init_riscv32 +#define flatview_insert flatview_insert_riscv32 +#define flatview_lookup flatview_lookup_riscv32 +#define flatview_read flatview_read_riscv32 +#define flatview_read_continue flatview_read_continue_riscv32 +#define flatview_read_full flatview_read_full_riscv32 +#define flatview_ref flatview_ref_riscv32 +#define flatview_simplify flatview_simplify_riscv32 +#define flatview_to_dispatch flatview_to_dispatch_riscv32 +#define flatview_translate flatview_translate_riscv32 +#define flatview_unref flatview_unref_riscv32 +#define float128ToCommonNaN float128ToCommonNaN_riscv32 +#define float128_add float128_add_riscv32 +#define float128_compare float128_compare_riscv32 +#define float128_compare_internal float128_compare_internal_riscv32 +#define float128_compare_quiet float128_compare_quiet_riscv32 +#define float128_default_nan float128_default_nan_riscv32 +#define float128_div float128_div_riscv32 +#define float128_eq float128_eq_riscv32 +#define float128_eq_quiet float128_eq_quiet_riscv32 +#define float128_is_quiet_nan float128_is_quiet_nan_riscv32 +#define float128_is_signaling_nan float128_is_signaling_nan_riscv32 +#define float128_le float128_le_riscv32 +#define float128_le_quiet float128_le_quiet_riscv32 +#define float128_lt float128_lt_riscv32 +#define float128_lt_quiet float128_lt_quiet_riscv32 +#define float128_maybe_silence_nan float128_maybe_silence_nan_riscv32 +#define float128_mul float128_mul_riscv32 +#define float128_rem float128_rem_riscv32 +#define float128_round_to_int float128_round_to_int_riscv32 +#define float128_scalbn float128_scalbn_riscv32 +#define float128_silence_nan float128_silence_nan_riscv32 +#define float128_sqrt float128_sqrt_riscv32 +#define float128_sub float128_sub_riscv32 +#define float128_to_float32 float128_to_float32_riscv32 +#define float128_to_float64 float128_to_float64_riscv32 +#define float128_to_floatx80 float128_to_floatx80_riscv32 +#define float128_to_int32 float128_to_int32_riscv32 +#define float128_to_int32_round_to_zero float128_to_int32_round_to_zero_riscv32 +#define float128_to_int64 float128_to_int64_riscv32 +#define float128_to_int64_round_to_zero float128_to_int64_round_to_zero_riscv32 +#define float128_to_uint32_round_to_zero float128_to_uint32_round_to_zero_riscv32 +#define float128_to_uint64 float128_to_uint64_riscv32 +#define float128_to_uint64_round_to_zero float128_to_uint64_round_to_zero_riscv32 +#define float128_unordered float128_unordered_riscv32 +#define float128_unordered_quiet float128_unordered_quiet_riscv32 +#define float16ToCommonNaN float16ToCommonNaN_riscv32 +#define float16_add float16_add_riscv32 +#define float16_compare float16_compare_riscv32 +#define float16_compare_quiet float16_compare_quiet_riscv32 +#define float16_default_nan float16_default_nan_riscv32 +#define float16_div float16_div_riscv32 +#define float16_is_quiet_nan float16_is_quiet_nan_riscv32 +#define float16_is_signaling_nan float16_is_signaling_nan_riscv32 +#define float16_max float16_max_riscv32 +#define float16_maxnum float16_maxnum_riscv32 +#define float16_maxnummag float16_maxnummag_riscv32 +#define float16_maybe_silence_nan float16_maybe_silence_nan_riscv32 +#define float16_min float16_min_riscv32 +#define float16_minnum float16_minnum_riscv32 +#define float16_minnummag float16_minnummag_riscv32 +#define float16_mul float16_mul_riscv32 +#define float16_muladd float16_muladd_riscv32 +#define float16_round_to_int float16_round_to_int_riscv32 +#define float16_scalbn float16_scalbn_riscv32 +#define float16_silence_nan float16_silence_nan_riscv32 +#define float16_sqrt float16_sqrt_riscv32 +#define float16_squash_input_denormal float16_squash_input_denormal_riscv32 +#define float16_sub float16_sub_riscv32 +#define float16_to_int16 float16_to_int16_riscv32 +#define float16_to_int16_round_to_zero float16_to_int16_round_to_zero_riscv32 +#define float16_to_int16_scalbn float16_to_int16_scalbn_riscv32 +#define float16_to_int32 float16_to_int32_riscv32 +#define float16_to_int32_round_to_zero float16_to_int32_round_to_zero_riscv32 +#define float16_to_int32_scalbn float16_to_int32_scalbn_riscv32 +#define float16_to_int64 float16_to_int64_riscv32 +#define float16_to_int64_round_to_zero float16_to_int64_round_to_zero_riscv32 +#define float16_to_int64_scalbn float16_to_int64_scalbn_riscv32 +#define float16_to_float32 float16_to_float32_riscv32 +#define float16_to_float64 float16_to_float64_riscv32 +#define float16_to_uint16 float16_to_uint16_riscv32 +#define float16_to_uint16_round_to_zero float16_to_uint16_round_to_zero_riscv32 +#define float16_to_uint16_scalbn float16_to_uint16_scalbn_riscv32 +#define float16_to_uint32 float16_to_uint32_riscv32 +#define float16_to_uint32_round_to_zero float16_to_uint32_round_to_zero_riscv32 +#define float16_to_uint32_scalbn float16_to_uint32_scalbn_riscv32 +#define float16_to_uint64 float16_to_uint64_riscv32 +#define float16_to_uint64_round_to_zero float16_to_uint64_round_to_zero_riscv32 +#define float16_to_uint64_scalbn float16_to_uint64_scalbn_riscv32 +#define float32ToCommonNaN float32ToCommonNaN_riscv32 +#define float32_abs float32_abs_riscv32 +#define float32_add float32_add_riscv32 +#define float32_chs float32_chs_riscv32 +#define float32_compare float32_compare_riscv32 +#define float32_compare_internal float32_compare_internal_riscv32 +#define float32_compare_quiet float32_compare_quiet_riscv32 +#define float32_default_nan float32_default_nan_riscv32 +#define float32_div float32_div_riscv32 +#define float32_eq float32_eq_riscv32 +#define float32_eq_quiet float32_eq_quiet_riscv32 +#define float32_exp2 float32_exp2_riscv32 +#define float32_exp2_coefficients float32_exp2_coefficients_riscv32 +#define float32_is_any_nan float32_is_any_nan_riscv32 +#define float32_is_infinity float32_is_infinity_riscv32 +#define float32_is_neg float32_is_neg_riscv32 +#define float32_is_quiet_nan float32_is_quiet_nan_riscv32 +#define float32_is_signaling_nan float32_is_signaling_nan_riscv32 +#define float32_is_zero float32_is_zero_riscv32 +#define float32_is_zero_or_denormal float32_is_zero_or_denormal_riscv32 +#define float32_le float32_le_riscv32 +#define float32_le_quiet float32_le_quiet_riscv32 +#define float32_log2 float32_log2_riscv32 +#define float32_lt float32_lt_riscv32 +#define float32_lt_quiet float32_lt_quiet_riscv32 +#define float32_max float32_max_riscv32 +#define float32_maxnum float32_maxnum_riscv32 +#define float32_maxnummag float32_maxnummag_riscv32 +#define float32_maybe_silence_nan float32_maybe_silence_nan_riscv32 +#define float32_min float32_min_riscv32 +#define float32_minmax float32_minmax_riscv32 +#define float32_minnum float32_minnum_riscv32 +#define float32_minnummag float32_minnummag_riscv32 +#define float32_mul float32_mul_riscv32 +#define float32_muladd float32_muladd_riscv32 +#define float32_rem float32_rem_riscv32 +#define float32_round_to_int float32_round_to_int_riscv32 +#define float32_scalbn float32_scalbn_riscv32 +#define float32_set_sign float32_set_sign_riscv32 +#define float32_silence_nan float32_silence_nan_riscv32 +#define float32_sqrt float32_sqrt_riscv32 +#define float32_squash_input_denormal float32_squash_input_denormal_riscv32 +#define float32_sub float32_sub_riscv32 +#define float32_to_float128 float32_to_float128_riscv32 +#define float32_to_float16 float32_to_float16_riscv32 +#define float32_to_float64 float32_to_float64_riscv32 +#define float32_to_floatx80 float32_to_floatx80_riscv32 +#define float32_to_int16 float32_to_int16_riscv32 +#define float32_to_int16_round_to_zero float32_to_int16_round_to_zero_riscv32 +#define float32_to_int16_scalbn float32_to_int16_scalbn_riscv32 +#define float32_to_int32 float32_to_int32_riscv32 +#define float32_to_int32_round_to_zero float32_to_int32_round_to_zero_riscv32 +#define float32_to_int32_scalbn float32_to_int32_scalbn_riscv32 +#define float32_to_int64 float32_to_int64_riscv32 +#define float32_to_int64_round_to_zero float32_to_int64_round_to_zero_riscv32 +#define float32_to_int64_scalbn float32_to_int64_scalbn_riscv32 +#define float32_to_uint16 float32_to_uint16_riscv32 +#define float32_to_uint16_round_to_zero float32_to_uint16_round_to_zero_riscv32 +#define float32_to_uint16_scalbn float32_to_uint16_scalbn_riscv32 +#define float32_to_uint32 float32_to_uint32_riscv32 +#define float32_to_uint32_round_to_zero float32_to_uint32_round_to_zero_riscv32 +#define float32_to_uint32_scalbn float32_to_uint32_scalbn_riscv32 +#define float32_to_uint64 float32_to_uint64_riscv32 +#define float32_to_uint64_round_to_zero float32_to_uint64_round_to_zero_riscv32 +#define float32_to_uint64_scalbn float32_to_uint64_scalbn_riscv32 +#define float32_unordered float32_unordered_riscv32 +#define float32_unordered_quiet float32_unordered_quiet_riscv32 +#define float64ToCommonNaN float64ToCommonNaN_riscv32 +#define float64_abs float64_abs_riscv32 +#define float64_add float64_add_riscv32 +#define float64_chs float64_chs_riscv32 +#define float64_compare float64_compare_riscv32 +#define float64_compare_internal float64_compare_internal_riscv32 +#define float64_compare_quiet float64_compare_quiet_riscv32 +#define float64_default_nan float64_default_nan_riscv32 +#define float64_div float64_div_riscv32 +#define float64_eq float64_eq_riscv32 +#define float64_eq_quiet float64_eq_quiet_riscv32 +#define float64_is_any_nan float64_is_any_nan_riscv32 +#define float64_is_infinity float64_is_infinity_riscv32 +#define float64_is_neg float64_is_neg_riscv32 +#define float64_is_quiet_nan float64_is_quiet_nan_riscv32 +#define float64_is_signaling_nan float64_is_signaling_nan_riscv32 +#define float64_is_zero float64_is_zero_riscv32 +#define float64_le float64_le_riscv32 +#define float64_le_quiet float64_le_quiet_riscv32 +#define float64_log2 float64_log2_riscv32 +#define float64_lt float64_lt_riscv32 +#define float64_lt_quiet float64_lt_quiet_riscv32 +#define float64_max float64_max_riscv32 +#define float64_maxnum float64_maxnum_riscv32 +#define float64_maxnummag float64_maxnummag_riscv32 +#define float64_maybe_silence_nan float64_maybe_silence_nan_riscv32 +#define float64_min float64_min_riscv32 +#define float64_minmax float64_minmax_riscv32 +#define float64_minnum float64_minnum_riscv32 +#define float64_minnummag float64_minnummag_riscv32 +#define float64_mul float64_mul_riscv32 +#define float64_muladd float64_muladd_riscv32 +#define float64_rem float64_rem_riscv32 +#define float64_round_to_int float64_round_to_int_riscv32 +#define float64_scalbn float64_scalbn_riscv32 +#define float64_set_sign float64_set_sign_riscv32 +#define float64_silence_nan float64_silence_nan_riscv32 +#define float64_sqrt float64_sqrt_riscv32 +#define float64_squash_input_denormal float64_squash_input_denormal_riscv32 +#define float64_sub float64_sub_riscv32 +#define float64_to_float128 float64_to_float128_riscv32 +#define float64_to_float16 float64_to_float16_riscv32 +#define float64_to_float32 float64_to_float32_riscv32 +#define float64_to_floatx80 float64_to_floatx80_riscv32 +#define float64_to_int16 float64_to_int16_riscv32 +#define float64_to_int16_round_to_zero float64_to_int16_round_to_zero_riscv32 +#define float64_to_int16_scalbn float64_to_int16_scalbn_riscv32 +#define float64_to_int32 float64_to_int32_riscv32 +#define float64_to_int32_round_to_zero float64_to_int32_round_to_zero_riscv32 +#define float64_to_int32_scalbn float64_to_int32_scalbn_riscv32 +#define float64_to_int64 float64_to_int64_riscv32 +#define float64_to_int64_round_to_zero float64_to_int64_round_to_zero_riscv32 +#define float64_to_int64_scalbn float64_to_int64_scalbn_riscv32 +#define float64_to_uint16 float64_to_uint16_riscv32 +#define float64_to_uint16_round_to_zero float64_to_uint16_round_to_zero_riscv32 +#define float64_to_uint16_scalbn float64_to_uint16_scalbn_riscv32 +#define float64_to_uint32 float64_to_uint32_riscv32 +#define float64_to_uint32_round_to_zero float64_to_uint32_round_to_zero_riscv32 +#define float64_to_uint32_scalbn float64_to_uint32_scalbn_riscv32 +#define float64_to_uint64 float64_to_uint64_riscv32 +#define float64_to_uint64_round_to_zero float64_to_uint64_round_to_zero_riscv32 +#define float64_to_uint64_scalbn float64_to_uint64_scalbn_riscv32 +#define float64_trunc_to_int float64_trunc_to_int_riscv32 +#define float64_unordered float64_unordered_riscv32 +#define float64_unordered_quiet float64_unordered_quiet_riscv32 +#define float_raise float_raise_riscv32 +#define floatx80ToCommonNaN floatx80ToCommonNaN_riscv32 +#define floatx80_add floatx80_add_riscv32 +#define floatx80_compare floatx80_compare_riscv32 +#define floatx80_compare_internal floatx80_compare_internal_riscv32 +#define floatx80_compare_quiet floatx80_compare_quiet_riscv32 +#define floatx80_default_nan floatx80_default_nan_riscv32 +#define floatx80_div floatx80_div_riscv32 +#define floatx80_eq floatx80_eq_riscv32 +#define floatx80_eq_quiet floatx80_eq_quiet_riscv32 +#define floatx80_infinity floatx80_infinity_riscv32 +#define floatx80_is_quiet_nan floatx80_is_quiet_nan_riscv32 +#define floatx80_is_signaling_nan floatx80_is_signaling_nan_riscv32 +#define floatx80_le floatx80_le_riscv32 +#define floatx80_le_quiet floatx80_le_quiet_riscv32 +#define floatx80_lt floatx80_lt_riscv32 +#define floatx80_lt_quiet floatx80_lt_quiet_riscv32 +#define floatx80_maybe_silence_nan floatx80_maybe_silence_nan_riscv32 +#define floatx80_mul floatx80_mul_riscv32 +#define floatx80_rem floatx80_rem_riscv32 +#define floatx80_round floatx80_round_riscv32 +#define floatx80_round_to_int floatx80_round_to_int_riscv32 +#define floatx80_scalbn floatx80_scalbn_riscv32 +#define floatx80_silence_nan floatx80_silence_nan_riscv32 +#define floatx80_sqrt floatx80_sqrt_riscv32 +#define floatx80_sub floatx80_sub_riscv32 +#define floatx80_to_float128 floatx80_to_float128_riscv32 +#define floatx80_to_float32 floatx80_to_float32_riscv32 +#define floatx80_to_float64 floatx80_to_float64_riscv32 +#define floatx80_to_int32 floatx80_to_int32_riscv32 +#define floatx80_to_int32_round_to_zero floatx80_to_int32_round_to_zero_riscv32 +#define floatx80_to_int64 floatx80_to_int64_riscv32 +#define floatx80_to_int64_round_to_zero floatx80_to_int64_round_to_zero_riscv32 +#define floatx80_unordered floatx80_unordered_riscv32 +#define floatx80_unordered_quiet floatx80_unordered_quiet_riscv32 +#define flush_icache_range flush_icache_range_riscv32 +#define format_string format_string_riscv32 +#define fp_decode_rm fp_decode_rm_riscv32 +#define frame_dummy frame_dummy_riscv32 +#define free_code_gen_buffer free_code_gen_buffer_riscv32 +#define free_range free_range_riscv32 +#define fstat64 fstat64_riscv32 +#define futex_wait futex_wait_riscv32 +#define futex_wake futex_wake_riscv32 +#define g_list_insert_sorted_merged g_list_insert_sorted_merged_riscv32 +#define gen_goto_tb gen_goto_tb_riscv32 +#define gen_helper_access_check_cp_reg gen_helper_access_check_cp_reg_riscv32 +#define gen_helper_check_breakpoints gen_helper_check_breakpoints_riscv32 +#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_riscv32 +#define gen_helper_cpsr_read gen_helper_cpsr_read_riscv32 +#define gen_helper_cpsr_write gen_helper_cpsr_write_riscv32 +#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_riscv32 +#define gen_helper_get_cp_reg gen_helper_get_cp_reg_riscv32 +#define gen_helper_get_cp_reg64 gen_helper_get_cp_reg64_riscv32 +#define gen_helper_get_r13_banked gen_helper_get_r13_banked_riscv32 +#define gen_helper_get_user_reg gen_helper_get_user_reg_riscv32 +#define gen_helper_sel_flags gen_helper_sel_flags_riscv32 +#define gen_helper_set_cp_reg gen_helper_set_cp_reg_riscv32 +#define gen_helper_set_cp_reg64 gen_helper_set_cp_reg64_riscv32 +#define gen_helper_set_neon_rmode gen_helper_set_neon_rmode_riscv32 +#define gen_helper_set_r13_banked gen_helper_set_r13_banked_riscv32 +#define gen_helper_set_rmode gen_helper_set_rmode_riscv32 +#define gen_helper_set_user_reg gen_helper_set_user_reg_riscv32 +#define gen_helper_vfp_get_fpscr gen_helper_vfp_get_fpscr_riscv32 +#define gen_helper_vfp_set_fpscr gen_helper_vfp_set_fpscr_riscv32 +#define gen_intermediate_code gen_intermediate_code_riscv32 +#define gen_lookup_tb gen_lookup_tb_riscv32 +#define gen_new_label gen_new_label_riscv32 +#define gen_set_label gen_set_label_riscv32 +#define gen_step_complete_exception gen_step_complete_exception_riscv32 +#define generate_memory_topology generate_memory_topology_riscv32 +#define generic_timer_cp_reginfo generic_timer_cp_reginfo_riscv32 +#define get_arm_cp_reginfo get_arm_cp_reginfo_riscv32 +#define get_clock get_clock_riscv32 +#define get_clock_realtime get_clock_realtime_riscv32 +#define get_constraint_priority get_constraint_priority_riscv32 +#define get_float_exception_flags get_float_exception_flags_riscv32 +#define get_float_rounding_mode get_float_rounding_mode_riscv32 +#define get_fpstatus_ptr get_fpstatus_ptr_riscv32 +#define get_level1_table_address get_level1_table_address_riscv32 +#define get_mem_index get_mem_index_riscv32 +#define get_next_param_value get_next_param_value_riscv32 +#define get_opt_name get_opt_name_riscv32 +#define get_opt_value get_opt_value_riscv32 +#define get_page_addr_code get_page_addr_code_riscv32 +#define get_param_value get_param_value_riscv32 +#define get_phys_addr get_phys_addr_riscv32 +#define get_phys_addr_lpae get_phys_addr_lpae_riscv32 +#define get_phys_addr_mpu get_phys_addr_mpu_riscv32 +#define get_phys_addr_v5 get_phys_addr_v5_riscv32 +#define get_phys_addr_v6 get_phys_addr_v6_riscv32 +#define get_system_memory get_system_memory_riscv32 +#define gt_cnt_read gt_cnt_read_riscv32 +#define gt_cnt_reset gt_cnt_reset_riscv32 +#define gt_cntfrq_access gt_cntfrq_access_riscv32 +#define gt_counter_access gt_counter_access_riscv32 +#define gt_ctl_write gt_ctl_write_riscv32 +#define gt_cval_write gt_cval_write_riscv32 +#define gt_get_countervalue gt_get_countervalue_riscv32 +#define gt_pct_access gt_pct_access_riscv32 +#define gt_ptimer_access gt_ptimer_access_riscv32 +#define gt_recalc_timer gt_recalc_timer_riscv32 +#define gt_timer_access gt_timer_access_riscv32 +#define gt_tval_read gt_tval_read_riscv32 +#define gt_tval_write gt_tval_write_riscv32 +#define gt_vct_access gt_vct_access_riscv32 +#define gt_vtimer_access gt_vtimer_access_riscv32 +#define guest_phys_blocks_free guest_phys_blocks_free_riscv32 +#define guest_phys_blocks_init guest_phys_blocks_init_riscv32 +#define handle_vcvt handle_vcvt_riscv32 +#define handle_vminmaxnm handle_vminmaxnm_riscv32 +#define handle_vrint handle_vrint_riscv32 +#define handle_vsel handle_vsel_riscv32 +#define has_help_option has_help_option_riscv32 +#define have_avx1 have_avx1_riscv32 +#define have_avx2 have_avx2_riscv32 +#define have_bmi1 have_bmi1_riscv32 +#define have_bmi2 have_bmi2_riscv32 +#define have_popcnt have_popcnt_riscv32 +#define hcr_write hcr_write_riscv32 +#define helper_access_check_cp_reg helper_access_check_cp_reg_riscv32 +#define helper_add_saturate helper_add_saturate_riscv32 +#define helper_add_setq helper_add_setq_riscv32 +#define helper_add_usaturate helper_add_usaturate_riscv32 +#define helper_atomic_add_fetchb helper_atomic_add_fetchb_riscv32 +#define helper_atomic_add_fetchb_mmu helper_atomic_add_fetchb_mmu_riscv32 +#define helper_atomic_add_fetchl_be helper_atomic_add_fetchl_be_riscv32 +#define helper_atomic_add_fetchl_be_mmu helper_atomic_add_fetchl_be_mmu_riscv32 +#define helper_atomic_add_fetchl_le helper_atomic_add_fetchl_le_riscv32 +#define helper_atomic_add_fetchl_le_mmu helper_atomic_add_fetchl_le_mmu_riscv32 +#define helper_atomic_add_fetchq_be helper_atomic_add_fetchq_be_riscv32 +#define helper_atomic_add_fetchq_be_mmu helper_atomic_add_fetchq_be_mmu_riscv32 +#define helper_atomic_add_fetchq_le helper_atomic_add_fetchq_le_riscv32 +#define helper_atomic_add_fetchq_le_mmu helper_atomic_add_fetchq_le_mmu_riscv32 +#define helper_atomic_add_fetchw_be helper_atomic_add_fetchw_be_riscv32 +#define helper_atomic_add_fetchw_be_mmu helper_atomic_add_fetchw_be_mmu_riscv32 +#define helper_atomic_add_fetchw_le helper_atomic_add_fetchw_le_riscv32 +#define helper_atomic_add_fetchw_le_mmu helper_atomic_add_fetchw_le_mmu_riscv32 +#define helper_atomic_and_fetchb helper_atomic_and_fetchb_riscv32 +#define helper_atomic_and_fetchb_le_mmu helper_atomic_and_fetchb_le_mmu_riscv32 +#define helper_atomic_and_fetchb_mmu helper_atomic_and_fetchb_mmu_riscv32 +#define helper_atomic_and_fetchl_be helper_atomic_and_fetchl_be_riscv32 +#define helper_atomic_and_fetchl_be_mmu helper_atomic_and_fetchl_be_mmu_riscv32 +#define helper_atomic_and_fetchl_le helper_atomic_and_fetchl_le_riscv32 +#define helper_atomic_and_fetchl_le_mmu helper_atomic_and_fetchl_le_mmu_riscv32 +#define helper_atomic_and_fetchq_be helper_atomic_and_fetchq_be_riscv32 +#define helper_atomic_and_fetchq_be_mmu helper_atomic_and_fetchq_be_mmu_riscv32 +#define helper_atomic_and_fetchq_le helper_atomic_and_fetchq_le_riscv32 +#define helper_atomic_and_fetchq_le_mmu helper_atomic_and_fetchq_le_mmu_riscv32 +#define helper_atomic_and_fetchw_be helper_atomic_and_fetchw_be_riscv32 +#define helper_atomic_and_fetchw_be_mmu helper_atomic_and_fetchw_be_mmu_riscv32 +#define helper_atomic_and_fetchw_le helper_atomic_and_fetchw_le_riscv32 +#define helper_atomic_and_fetchw_le_mmu helper_atomic_and_fetchw_le_mmu_riscv32 +#define helper_atomic_cmpxchgb helper_atomic_cmpxchgb_riscv32 +#define helper_atomic_cmpxchgb helper_atomic_cmpxchgb_riscv32 +#define helper_atomic_cmpxchgb_mmu helper_atomic_cmpxchgb_mmu_riscv32 +#define helper_atomic_cmpxchgl_be helper_atomic_cmpxchgl_be_riscv32 +#define helper_atomic_cmpxchgl_be_mmu helper_atomic_cmpxchgl_be_mmu_riscv32 +#define helper_atomic_cmpxchgl_le helper_atomic_cmpxchgl_le_riscv32 +#define helper_atomic_cmpxchgl_le_mmu helper_atomic_cmpxchgl_le_mmu_riscv32 +#define helper_atomic_cmpxchgo_be helper_atomic_cmpxchgo_be_riscv32 +#define helper_atomic_cmpxchgo_be_mmu helper_atomic_cmpxchgo_be_mmu_riscv32 +#define helper_atomic_cmpxchgo_le helper_atomic_cmpxchgo_le_riscv32 +#define helper_atomic_cmpxchgo_le_mmu helper_atomic_cmpxchgo_le_mmu_riscv32 +#define helper_atomic_cmpxchgq_be helper_atomic_cmpxchgq_be_riscv32 +#define helper_atomic_cmpxchgq_be_mmu helper_atomic_cmpxchgq_be_mmu_riscv32 +#define helper_atomic_cmpxchgq_le helper_atomic_cmpxchgq_le_riscv32 +#define helper_atomic_cmpxchgq_le_mmu helper_atomic_cmpxchgq_le_mmu_riscv32 +#define helper_atomic_cmpxchgw_be helper_atomic_cmpxchgw_be_riscv32 +#define helper_atomic_cmpxchgw_be_mmu helper_atomic_cmpxchgw_be_mmu_riscv32 +#define helper_atomic_cmpxchgw_le helper_atomic_cmpxchgw_le_riscv32 +#define helper_atomic_cmpxchgw_le_mmu helper_atomic_cmpxchgw_le_mmu_riscv32 +#define helper_atomic_fetch_addb helper_atomic_fetch_addb_riscv32 +#define helper_atomic_fetch_addb_mmu helper_atomic_fetch_addb_mmu_riscv32 +#define helper_atomic_fetch_addl_be helper_atomic_fetch_addl_be_riscv32 +#define helper_atomic_fetch_addl_be_mmu helper_atomic_fetch_addl_be_mmu_riscv32 +#define helper_atomic_fetch_addl_le helper_atomic_fetch_addl_le_riscv32 +#define helper_atomic_fetch_addl_le_mmu helper_atomic_fetch_addl_le_mmu_riscv32 +#define helper_atomic_fetch_addq_be helper_atomic_fetch_addq_be_riscv32 +#define helper_atomic_fetch_addq_be_mmu helper_atomic_fetch_addq_be_mmu_riscv32 +#define helper_atomic_fetch_addq_le helper_atomic_fetch_addq_le_riscv32 +#define helper_atomic_fetch_addq_le_mmu helper_atomic_fetch_addq_le_mmu_riscv32 +#define helper_atomic_fetch_addw_be helper_atomic_fetch_addw_be_riscv32 +#define helper_atomic_fetch_addw_be_mmu helper_atomic_fetch_addw_be_mmu_riscv32 +#define helper_atomic_fetch_addw_le helper_atomic_fetch_addw_le_riscv32 +#define helper_atomic_fetch_addw_le_mmu helper_atomic_fetch_addw_le_mmu_riscv32 +#define helper_atomic_fetch_andb helper_atomic_fetch_andb_riscv32 +#define helper_atomic_fetch_andb_mmu helper_atomic_fetch_andb_mmu_riscv32 +#define helper_atomic_fetch_andl_be helper_atomic_fetch_andl_be_riscv32 +#define helper_atomic_fetch_andl_be_mmu helper_atomic_fetch_andl_be_mmu_riscv32 +#define helper_atomic_fetch_andl_le helper_atomic_fetch_andl_le_riscv32 +#define helper_atomic_fetch_andl_le_mmu helper_atomic_fetch_andl_le_mmu_riscv32 +#define helper_atomic_fetch_andq_be helper_atomic_fetch_andq_be_riscv32 +#define helper_atomic_fetch_andq_be_mmu helper_atomic_fetch_andq_be_mmu_riscv32 +#define helper_atomic_fetch_andq_le helper_atomic_fetch_andq_le_riscv32 +#define helper_atomic_fetch_andq_le_mmu helper_atomic_fetch_andq_le_mmu_riscv32 +#define helper_atomic_fetch_andw_be helper_atomic_fetch_andw_be_riscv32 +#define helper_atomic_fetch_andw_be_mmu helper_atomic_fetch_andw_be_mmu_riscv32 +#define helper_atomic_fetch_andw_le helper_atomic_fetch_andw_le_riscv32 +#define helper_atomic_fetch_andw_le_mmu helper_atomic_fetch_andw_le_mmu_riscv32 +#define helper_atomic_fetch_orb helper_atomic_fetch_orb_riscv32 +#define helper_atomic_fetch_orb_mmu helper_atomic_fetch_orb_mmu_riscv32 +#define helper_atomic_fetch_orl_be helper_atomic_fetch_orl_be_riscv32 +#define helper_atomic_fetch_orl_be_mmu helper_atomic_fetch_orl_be_mmu_riscv32 +#define helper_atomic_fetch_orl_le helper_atomic_fetch_orl_le_riscv32 +#define helper_atomic_fetch_orl_le_mmu helper_atomic_fetch_orl_le_mmu_riscv32 +#define helper_atomic_fetch_orq_be helper_atomic_fetch_orq_be_riscv32 +#define helper_atomic_fetch_orq_be_mmu helper_atomic_fetch_orq_be_mmu_riscv32 +#define helper_atomic_fetch_orq_le helper_atomic_fetch_orq_le_riscv32 +#define helper_atomic_fetch_orq_le_mmu helper_atomic_fetch_orq_le_mmu_riscv32 +#define helper_atomic_fetch_orw_be helper_atomic_fetch_orw_be_riscv32 +#define helper_atomic_fetch_orw_be_mmu helper_atomic_fetch_orw_be_mmu_riscv32 +#define helper_atomic_fetch_orw_le helper_atomic_fetch_orw_le_riscv32 +#define helper_atomic_fetch_orw_le_mmu helper_atomic_fetch_orw_le_mmu_riscv32 +#define helper_atomic_fetch_smaxb_mmu helper_atomic_fetch_smaxb_mmu_riscv32 +#define helper_atomic_fetch_smaxb helper_atomic_fetch_smaxb_riscv32 +#define helper_atomic_fetch_smaxl_be_mmu helper_atomic_fetch_smaxl_be_mmu_riscv32 +#define helper_atomic_fetch_smaxl_be helper_atomic_fetch_smaxl_be_riscv32 +#define helper_atomic_fetch_smaxq_be_mmu helper_atomic_fetch_smaxq_be_mmu_riscv32 +#define helper_atomic_fetch_smaxq_be helper_atomic_fetch_smaxq_be_riscv32 +#define helper_atomic_fetch_smaxw_be_mmu helper_atomic_fetch_smaxw_be_mmu_riscv32 +#define helper_atomic_fetch_smaxw_be helper_atomic_fetch_smaxw_be_riscv32 +#define helper_atomic_fetch_sminb_mmu helper_atomic_fetch_sminb_mmu_riscv32 +#define helper_atomic_fetch_sminb helper_atomic_fetch_sminb_riscv32 +#define helper_atomic_fetch_sminl_be_mmu helper_atomic_fetch_sminl_be_mmu_riscv32 +#define helper_atomic_fetch_sminl_be helper_atomic_fetch_sminl_be_riscv32 +#define helper_atomic_fetch_sminq_be_mmu helper_atomic_fetch_sminq_be_mmu_riscv32 +#define helper_atomic_fetch_sminq_be helper_atomic_fetch_sminq_be_riscv32 +#define helper_atomic_fetch_sminw_be_mmu helper_atomic_fetch_sminw_be_mmu_riscv32 +#define helper_atomic_fetch_sminw_be helper_atomic_fetch_sminw_be_riscv32 +#define helper_atomic_fetch_umaxb_mmu helper_atomic_fetch_umaxb_mmu_riscv32 +#define helper_atomic_fetch_umaxb helper_atomic_fetch_umaxb_riscv32 +#define helper_atomic_fetch_umaxl_be_mmu helper_atomic_fetch_umaxl_be_mmu_riscv32 +#define helper_atomic_fetch_umaxl_be helper_atomic_fetch_umaxl_be_riscv32 +#define helper_atomic_fetch_umaxq_be_mmu helper_atomic_fetch_umaxq_be_mmu_riscv32 +#define helper_atomic_fetch_umaxq_be helper_atomic_fetch_umaxq_be_riscv32 +#define helper_atomic_fetch_umaxw_be_mmu helper_atomic_fetch_umaxw_be_mmu_riscv32 +#define helper_atomic_fetch_umaxw_be helper_atomic_fetch_umaxw_be_riscv32 +#define helper_atomic_fetch_uminb_mmu helper_atomic_fetch_uminb_mmu_riscv32 +#define helper_atomic_fetch_uminb helper_atomic_fetch_uminb_riscv32 +#define helper_atomic_fetch_uminl_be_mmu helper_atomic_fetch_uminl_be_mmu_riscv32 +#define helper_atomic_fetch_uminl_be helper_atomic_fetch_uminl_be_riscv32 +#define helper_atomic_fetch_uminq_be_mmu helper_atomic_fetch_uminq_be_mmu_riscv32 +#define helper_atomic_fetch_uminq_be helper_atomic_fetch_uminq_be_riscv32 +#define helper_atomic_fetch_uminw_be_mmu helper_atomic_fetch_uminw_be_mmu_riscv32 +#define helper_atomic_fetch_uminw_be helper_atomic_fetch_uminw_be_riscv32 +#define helper_atomic_fetch_smaxl_le_mmu helper_atomic_fetch_smaxl_le_mmu_riscv32 +#define helper_atomic_fetch_smaxl_le helper_atomic_fetch_smaxl_le_riscv32 +#define helper_atomic_fetch_smaxq_le_mmu helper_atomic_fetch_smaxq_le_mmu_riscv32 +#define helper_atomic_fetch_smaxq_le helper_atomic_fetch_smaxq_le_riscv32 +#define helper_atomic_fetch_smaxw_le_mmu helper_atomic_fetch_smaxw_le_mmu_riscv32 +#define helper_atomic_fetch_smaxw_le helper_atomic_fetch_smaxw_le_riscv32 +#define helper_atomic_fetch_sminl_le_mmu helper_atomic_fetch_sminl_le_mmu_riscv32 +#define helper_atomic_fetch_sminl_le helper_atomic_fetch_sminl_le_riscv32 +#define helper_atomic_fetch_sminq_le_mmu helper_atomic_fetch_sminq_le_mmu_riscv32 +#define helper_atomic_fetch_sminq_le helper_atomic_fetch_sminq_le_riscv32 +#define helper_atomic_fetch_sminw_le_mmu helper_atomic_fetch_sminw_le_mmu_riscv32 +#define helper_atomic_fetch_sminw_le helper_atomic_fetch_sminw_le_riscv32 +#define helper_atomic_fetch_umaxl_le_mmu helper_atomic_fetch_umaxl_le_mmu_riscv32 +#define helper_atomic_fetch_umaxl_le helper_atomic_fetch_umaxl_le_riscv32 +#define helper_atomic_fetch_umaxq_le_mmu helper_atomic_fetch_umaxq_le_mmu_riscv32 +#define helper_atomic_fetch_umaxq_le helper_atomic_fetch_umaxq_le_riscv32 +#define helper_atomic_fetch_umaxw_le_mmu helper_atomic_fetch_umaxw_le_mmu_riscv32 +#define helper_atomic_fetch_umaxw_le helper_atomic_fetch_umaxw_le_riscv32 +#define helper_atomic_fetch_uminl_le_mmu helper_atomic_fetch_uminl_le_mmu_riscv32 +#define helper_atomic_fetch_uminl_le helper_atomic_fetch_uminl_le_riscv32 +#define helper_atomic_fetch_uminq_le_mmu helper_atomic_fetch_uminq_le_mmu_riscv32 +#define helper_atomic_fetch_uminq_le helper_atomic_fetch_uminq_le_riscv32 +#define helper_atomic_fetch_uminw_le_mmu helper_atomic_fetch_uminw_le_mmu_riscv32 +#define helper_atomic_fetch_uminw_le helper_atomic_fetch_uminw_le_riscv32 +#define helper_atomic_fetch_xorb helper_atomic_fetch_xorb_riscv32 +#define helper_atomic_fetch_xorb_mmu helper_atomic_fetch_xorb_mmu_riscv32 +#define helper_atomic_fetch_xorl_be helper_atomic_fetch_xorl_be_riscv32 +#define helper_atomic_fetch_xorl_be_mmu helper_atomic_fetch_xorl_be_mmu_riscv32 +#define helper_atomic_fetch_xorl_le helper_atomic_fetch_xorl_le_riscv32 +#define helper_atomic_fetch_xorl_le_mmu helper_atomic_fetch_xorl_le_mmu_riscv32 +#define helper_atomic_fetch_xorq_be helper_atomic_fetch_xorq_be_riscv32 +#define helper_atomic_fetch_xorq_be_mmu helper_atomic_fetch_xorq_be_mmu_riscv32 +#define helper_atomic_fetch_xorq_le helper_atomic_fetch_xorq_le_riscv32 +#define helper_atomic_fetch_xorq_le_mmu helper_atomic_fetch_xorq_le_mmu_riscv32 +#define helper_atomic_fetch_xorw_be helper_atomic_fetch_xorw_be_riscv32 +#define helper_atomic_fetch_xorw_be_mmu helper_atomic_fetch_xorw_be_mmu_riscv32 +#define helper_atomic_fetch_xorw_le helper_atomic_fetch_xorw_le_riscv32 +#define helper_atomic_fetch_xorw_le_mmu helper_atomic_fetch_xorw_le_mmu_riscv32 +#define helper_atomic_ldo_be helper_atomic_ldo_be_riscv32 +#define helper_atomic_ldo_be_mmu helper_atomic_ldo_be_mmu_riscv32 +#define helper_atomic_ldo_le helper_atomic_ldo_le_riscv32 +#define helper_atomic_ldo_le_mmu helper_atomic_ldo_le_mmu_riscv32 +#define helper_atomic_or_fetchb helper_atomic_or_fetchb_riscv32 +#define helper_atomic_or_fetchb_mmu helper_atomic_or_fetchb_mmu_riscv32 +#define helper_atomic_or_fetchl_be helper_atomic_or_fetchl_be_riscv32 +#define helper_atomic_or_fetchl_be_mmu helper_atomic_or_fetchl_be_mmu_riscv32 +#define helper_atomic_or_fetchl_le helper_atomic_or_fetchl_le_riscv32 +#define helper_atomic_or_fetchl_le_mmu helper_atomic_or_fetchl_le_mmu_riscv32 +#define helper_atomic_or_fetchq_be helper_atomic_or_fetchq_be_riscv32 +#define helper_atomic_or_fetchq_be_mmu helper_atomic_or_fetchq_be_mmu_riscv32 +#define helper_atomic_or_fetchq_le helper_atomic_or_fetchq_le_riscv32 +#define helper_atomic_or_fetchq_le_mmu helper_atomic_or_fetchq_le_mmu_riscv32 +#define helper_atomic_or_fetchw_be helper_atomic_or_fetchw_be_riscv32 +#define helper_atomic_or_fetchw_be_mmu helper_atomic_or_fetchw_be_mmu_riscv32 +#define helper_atomic_or_fetchw_le helper_atomic_or_fetchw_le_riscv32 +#define helper_atomic_or_fetchw_le_mmu helper_atomic_or_fetchw_le_mmu_riscv32 +#define helper_atomic_smax_fetchb_mmu helper_atomic_smax_fetchb_mmu_riscv32 +#define helper_atomic_smax_fetchb helper_atomic_smax_fetchb_riscv32 +#define helper_atomic_smax_fetchl_be_mmu helper_atomic_smax_fetchl_be_mmu_riscv32 +#define helper_atomic_smax_fetchl_be helper_atomic_smax_fetchl_be_riscv32 +#define helper_atomic_smax_fetchq_be_mmu helper_atomic_smax_fetchq_be_mmu_riscv32 +#define helper_atomic_smax_fetchq_be helper_atomic_smax_fetchq_be_riscv32 +#define helper_atomic_smax_fetchw_be_mmu helper_atomic_smax_fetchw_be_mmu_riscv32 +#define helper_atomic_smax_fetchw_be helper_atomic_smax_fetchw_be_riscv32 +#define helper_atomic_smin_fetchb_mmu helper_atomic_smin_fetchb_mmu_riscv32 +#define helper_atomic_smin_fetchb helper_atomic_smin_fetchb_riscv32 +#define helper_atomic_smin_fetchl_be_mmu helper_atomic_smin_fetchl_be_mmu_riscv32 +#define helper_atomic_smin_fetchl_be helper_atomic_smin_fetchl_be_riscv32 +#define helper_atomic_smin_fetchq_be_mmu helper_atomic_smin_fetchq_be_mmu_riscv32 +#define helper_atomic_smin_fetchq_be helper_atomic_smin_fetchq_be_riscv32 +#define helper_atomic_smin_fetchw_be_mmu helper_atomic_smin_fetchw_be_mmu_riscv32 +#define helper_atomic_smin_fetchw_be helper_atomic_smin_fetchw_be_riscv32 +#define helper_atomic_smax_fetchl_le_mmu helper_atomic_smax_fetchl_le_mmu_riscv32 +#define helper_atomic_smax_fetchl_le helper_atomic_smax_fetchl_le_riscv32 +#define helper_atomic_smax_fetchq_le_mmu helper_atomic_smax_fetchq_le_mmu_riscv32 +#define helper_atomic_smax_fetchq_le helper_atomic_smax_fetchq_le_riscv32 +#define helper_atomic_smax_fetchw_le_mmu helper_atomic_smax_fetchw_le_mmu_riscv32 +#define helper_atomic_smax_fetchw_le helper_atomic_smax_fetchw_le_riscv32 +#define helper_atomic_smin_fetchl_le_mmu helper_atomic_smin_fetchl_le_mmu_riscv32 +#define helper_atomic_smin_fetchl_le helper_atomic_smin_fetchl_le_riscv32 +#define helper_atomic_smin_fetchq_le_mmu helper_atomic_smin_fetchq_le_mmu_riscv32 +#define helper_atomic_smin_fetchq_le helper_atomic_smin_fetchq_le_riscv32 +#define helper_atomic_smin_fetchw_le_mmu helper_atomic_smin_fetchw_le_mmu_riscv32 +#define helper_atomic_smin_fetchw_le helper_atomic_smin_fetchw_le_riscv32 +#define helper_atomic_sto_be helper_atomic_sto_be_riscv32 +#define helper_atomic_sto_be_mmu helper_atomic_sto_be_mmu_riscv32 +#define helper_atomic_sto_le helper_atomic_sto_le_riscv32 +#define helper_atomic_sto_le_mmu helper_atomic_sto_le_mmu_riscv32 +#define helper_atomic_umax_fetchb_mmu helper_atomic_umax_fetchb_mmu_riscv32 +#define helper_atomic_umax_fetchb helper_atomic_umax_fetchb_riscv32 +#define helper_atomic_umax_fetchl_be_mmu helper_atomic_umax_fetchl_be_mmu_riscv32 +#define helper_atomic_umax_fetchl_be helper_atomic_umax_fetchl_be_riscv32 +#define helper_atomic_umax_fetchq_be_mmu helper_atomic_umax_fetchq_be_mmu_riscv32 +#define helper_atomic_umax_fetchq_be helper_atomic_umax_fetchq_be_riscv32 +#define helper_atomic_umax_fetchw_be_mmu helper_atomic_umax_fetchw_be_mmu_riscv32 +#define helper_atomic_umax_fetchw_be helper_atomic_umax_fetchw_be_riscv32 +#define helper_atomic_umin_fetchb_mmu helper_atomic_umin_fetchb_mmu_riscv32 +#define helper_atomic_umin_fetchb helper_atomic_umin_fetchb_riscv32 +#define helper_atomic_umin_fetchl_be_mmu helper_atomic_umin_fetchl_be_mmu_riscv32 +#define helper_atomic_umin_fetchl_be helper_atomic_umin_fetchl_be_riscv32 +#define helper_atomic_umin_fetchq_be_mmu helper_atomic_umin_fetchq_be_mmu_riscv32 +#define helper_atomic_umin_fetchq_be helper_atomic_umin_fetchq_be_riscv32 +#define helper_atomic_umin_fetchw_be_mmu helper_atomic_umin_fetchw_be_mmu_riscv32 +#define helper_atomic_umin_fetchw_be helper_atomic_umin_fetchw_be_riscv32 +#define helper_atomic_umax_fetchl_le_mmu helper_atomic_umax_fetchl_le_mmu_riscv32 +#define helper_atomic_umax_fetchl_le helper_atomic_umax_fetchl_le_riscv32 +#define helper_atomic_umax_fetchq_le_mmu helper_atomic_umax_fetchq_le_mmu_riscv32 +#define helper_atomic_umax_fetchq_le helper_atomic_umax_fetchq_le_riscv32 +#define helper_atomic_umax_fetchw_le_mmu helper_atomic_umax_fetchw_le_mmu_riscv32 +#define helper_atomic_umax_fetchw_le helper_atomic_umax_fetchw_le_riscv32 +#define helper_atomic_umin_fetchl_le_mmu helper_atomic_umin_fetchl_le_mmu_riscv32 +#define helper_atomic_umin_fetchl_le helper_atomic_umin_fetchl_le_riscv32 +#define helper_atomic_umin_fetchq_le_mmu helper_atomic_umin_fetchq_le_mmu_riscv32 +#define helper_atomic_umin_fetchq_le helper_atomic_umin_fetchq_le_riscv32 +#define helper_atomic_umin_fetchw_le_mmu helper_atomic_umin_fetchw_le_mmu_riscv32 +#define helper_atomic_umin_fetchw_le helper_atomic_umin_fetchw_le_riscv32 +#define helper_atomic_xchgb helper_atomic_xchgb_riscv32 +#define helper_atomic_xchgb helper_atomic_xchgb_riscv32 +#define helper_atomic_xchgb_mmu helper_atomic_xchgb_mmu_riscv32 +#define helper_atomic_xchgl_be helper_atomic_xchgl_be_riscv32 +#define helper_atomic_xchgl_be_mmu helper_atomic_xchgl_be_mmu_riscv32 +#define helper_atomic_xchgl_le helper_atomic_xchgl_le_riscv32 +#define helper_atomic_xchgl_le_mmu helper_atomic_xchgl_le_mmu_riscv32 +#define helper_atomic_xchgq_be helper_atomic_xchgq_be_riscv32 +#define helper_atomic_xchgq_be_mmu helper_atomic_xchgq_be_mmu_riscv32 +#define helper_atomic_xchgq_le helper_atomic_xchgq_le_riscv32 +#define helper_atomic_xchgq_le_mmu helper_atomic_xchgq_le_mmu_riscv32 +#define helper_atomic_xchgw_be helper_atomic_xchgw_be_riscv32 +#define helper_atomic_xchgw_be_mmu helper_atomic_xchgw_be_mmu_riscv32 +#define helper_atomic_xchgw_le helper_atomic_xchgw_le_riscv32 +#define helper_atomic_xchgw_le_mmu helper_atomic_xchgw_le_mmu_riscv32 +#define helper_atomic_xor_fetchb helper_atomic_xor_fetchb_riscv32 +#define helper_atomic_xor_fetchb_mmu helper_atomic_xor_fetchb_mmu_riscv32 +#define helper_atomic_xor_fetchl_be helper_atomic_xor_fetchl_be_riscv32 +#define helper_atomic_xor_fetchl_be_mmu helper_atomic_xor_fetchl_be_mmu_riscv32 +#define helper_atomic_xor_fetchl_le helper_atomic_xor_fetchl_le_riscv32 +#define helper_atomic_xor_fetchl_le_mmu helper_atomic_xor_fetchl_le_mmu_riscv32 +#define helper_atomic_xor_fetchq_be helper_atomic_xor_fetchq_be_riscv32 +#define helper_atomic_xor_fetchq_be_mmu helper_atomic_xor_fetchq_be_mmu_riscv32 +#define helper_atomic_xor_fetchq_le helper_atomic_xor_fetchq_le_riscv32 +#define helper_atomic_xor_fetchq_le_mmu helper_atomic_xor_fetchq_le_mmu_riscv32 +#define helper_atomic_xor_fetchw_be helper_atomic_xor_fetchw_be_riscv32 +#define helper_atomic_xor_fetchw_be_mmu helper_atomic_xor_fetchw_be_mmu_riscv32 +#define helper_atomic_xor_fetchw_le helper_atomic_xor_fetchw_le_riscv32 +#define helper_atomic_xor_fetchw_le_mmu helper_atomic_xor_fetchw_le_mmu_riscv32 +#define helper_be_ldl_cmmu helper_be_ldl_cmmu_riscv32 +#define helper_be_ldq_cmmu helper_be_ldq_cmmu_riscv32 +#define helper_be_ldq_mmu helper_be_ldq_mmu_riscv32 +#define helper_be_ldsl_mmu helper_be_ldsl_mmu_riscv32 +#define helper_be_ldsw_mmu helper_be_ldsw_mmu_riscv32 +#define helper_be_ldul_mmu helper_be_ldul_mmu_riscv32 +#define helper_be_lduw_mmu helper_be_lduw_mmu_riscv32 +#define helper_be_ldw_cmmu helper_be_ldw_cmmu_riscv32 +#define helper_be_stl_mmu helper_be_stl_mmu_riscv32 +#define helper_be_stq_mmu helper_be_stq_mmu_riscv32 +#define helper_be_stw_mmu helper_be_stw_mmu_riscv32 +#define helper_clear_pstate_ss helper_clear_pstate_ss_riscv32 +#define helper_clrsb_i32 helper_clrsb_i32_riscv32 +#define helper_clrsb_i64 helper_clrsb_i64_riscv32 +#define helper_clz_i32 helper_clz_i32_riscv32 +#define helper_clz_i64 helper_clz_i64_riscv32 +#define helper_ctpop_i32 helper_ctpop_i32_riscv32 +#define helper_ctpop_i64 helper_ctpop_i64_riscv32 +#define helper_ctz_i32 helper_ctz_i32_riscv32 +#define helper_ctz_i64 helper_ctz_i64_riscv32 +#define helper_cpsr_read helper_cpsr_read_riscv32 +#define helper_cpsr_write helper_cpsr_write_riscv32 +#define helper_cpsr_write_eret helper_cpsr_write_eret_riscv32 +#define helper_crc32_arm helper_crc32_arm_riscv32 +#define helper_crc32c helper_crc32c_riscv32 +#define helper_crypto_aese helper_crypto_aese_riscv32 +#define helper_crypto_aesmc helper_crypto_aesmc_riscv32 +#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_riscv32 +#define helper_crypto_sha1h helper_crypto_sha1h_riscv32 +#define helper_crypto_sha1su1 helper_crypto_sha1su1_riscv32 +#define helper_crypto_sha256h helper_crypto_sha256h_riscv32 +#define helper_crypto_sha256h2 helper_crypto_sha256h2_riscv32 +#define helper_crypto_sha256su0 helper_crypto_sha256su0_riscv32 +#define helper_crypto_sha256su1 helper_crypto_sha256su1_riscv32 +#define helper_crypto_sha512h helper_crypto_sha512h_riscv32 +#define helper_crypto_sha512h2 helper_crypto_sha512h2_riscv32 +#define helper_crypto_sha512su0 helper_crypto_sha512su0_riscv32 +#define helper_crypto_sha512su1 helper_crypto_sha512su1_riscv32 +#define helper_crypto_sm3partw1 helper_crypto_sm3partw1_riscv32 +#define helper_crypto_sm3partw2 helper_crypto_sm3partw2_riscv32 +#define helper_crypto_sm3tt helper_crypto_sm3tt_riscv32 +#define helper_crypto_sm4e helper_crypto_sm4e_riscv32 +#define helper_crypto_sm4ekey helper_crypto_sm4ekey_riscv32 +#define helper_dc_zva helper_dc_zva_riscv32 +#define helper_div_i32 helper_div_i32_riscv32 +#define helper_div_i64 helper_div_i64_riscv32 +#define helper_divu_i32 helper_divu_i32_riscv32 +#define helper_divu_i64 helper_divu_i64_riscv32 +#define helper_double_saturate helper_double_saturate_riscv32 +#define helper_exception_bkpt_insn helper_exception_bkpt_insn_riscv32 +#define helper_exception_internal helper_exception_internal_riscv32 +#define helper_exception_return helper_exception_return_riscv32 +#define helper_exception_with_syndrome helper_exception_with_syndrome_riscv32 +#define helper_exit_atomic helper_exit_atomic_riscv32 +#define helper_get_cp_reg helper_get_cp_reg_riscv32 +#define helper_get_cp_reg64 helper_get_cp_reg64_riscv32 +#define helper_get_r13_banked helper_get_r13_banked_riscv32 +#define helper_get_user_reg helper_get_user_reg_riscv32 +#define helper_gvec_add8 helper_gvec_add8_riscv32 +#define helper_gvec_add16 helper_gvec_add16_riscv32 +#define helper_gvec_add32 helper_gvec_add32_riscv32 +#define helper_gvec_add64 helper_gvec_add64_riscv32 +#define helper_gvec_adds8 helper_gvec_adds8_riscv32 +#define helper_gvec_adds16 helper_gvec_adds16_riscv32 +#define helper_gvec_adds32 helper_gvec_adds32_riscv32 +#define helper_gvec_adds64 helper_gvec_adds64_riscv32 +#define helper_gvec_and helper_gvec_and_riscv32 +#define helper_gvec_andc helper_gvec_andc_riscv32 +#define helper_gvec_ands helper_gvec_ands_riscv32 +#define helper_gvec_dup8 helper_gvec_dup8_riscv32 +#define helper_gvec_dup16 helper_gvec_dup16_riscv32 +#define helper_gvec_dup32 helper_gvec_dup32_riscv32 +#define helper_gvec_dup64 helper_gvec_dup64_riscv32 +#define helper_gvec_eq8 helper_gvec_eq8_riscv32 +#define helper_gvec_eq16 helper_gvec_eq16_riscv32 +#define helper_gvec_eq32 helper_gvec_eq32_riscv32 +#define helper_gvec_eq64 helper_gvec_eq64_riscv32 +#define helper_gvec_fadd_d helper_gvec_fadd_d_riscv32 +#define helper_gvec_fadd_h helper_gvec_fadd_h_riscv32 +#define helper_gvec_fadd_s helper_gvec_fadd_s_riscv32 +#define helper_gvec_fcaddh helper_gvec_fcaddh_riscv32 +#define helper_gvec_fcadds helper_gvec_fcadds_riscv32 +#define helper_gvec_fcaddd helper_gvec_fcaddd_riscv32 +#define helper_gvec_fcmlad helper_gvec_fcmlad_riscv32 +#define helper_gvec_fcmlah helper_gvec_fcmlah_riscv32 +#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_riscv32 +#define helper_gvec_fcmlas helper_gvec_fcmlas_riscv32 +#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_riscv32 +#define helper_gvec_fmla_idx_d helper_gvec_fmla_idx_d_riscv32 +#define helper_gvec_fmla_idx_h helper_gvec_fmla_idx_h_riscv32 +#define helper_gvec_fmla_idx_s helper_gvec_fmla_idx_s_riscv32 +#define helper_gvec_fmul_d helper_gvec_fmul_d_riscv32 +#define helper_gvec_fmul_h helper_gvec_fmul_h_riscv32 +#define helper_gvec_fmul_s helper_gvec_fmul_s_riscv32 +#define helper_gvec_fmul_idx_d helper_gvec_fmul_idx_d_riscv32 +#define helper_gvec_fmul_idx_h helper_gvec_fmul_idx_h_riscv32 +#define helper_gvec_fmul_idx_s helper_gvec_fmul_idx_s_riscv32 +#define helper_gvec_frecpe_d helper_gvec_frecpe_d_riscv32 +#define helper_gvec_frecpe_h helper_gvec_frecpe_h_riscv32 +#define helper_gvec_frecpe_s helper_gvec_frecpe_s_riscv32 +#define helper_gvec_frsqrte_d helper_gvec_frsqrte_d_riscv32 +#define helper_gvec_frsqrte_h helper_gvec_frsqrte_h_riscv32 +#define helper_gvec_frsqrte_s helper_gvec_frsqrte_s_riscv32 +#define helper_gvec_fsub_d helper_gvec_fsub_d_riscv32 +#define helper_gvec_fsub_h helper_gvec_fsub_h_riscv32 +#define helper_gvec_fsub_s helper_gvec_fsub_s_riscv32 +#define helper_gvec_ftsmul_d helper_gvec_ftsmul_d_riscv32 +#define helper_gvec_ftsmul_h helper_gvec_ftsmul_h_riscv32 +#define helper_gvec_ftsmul_s helper_gvec_ftsmul_s_riscv32 +#define helper_gvec_le8 helper_gvec_le8_riscv32 +#define helper_gvec_le16 helper_gvec_le16_riscv32 +#define helper_gvec_le32 helper_gvec_le32_riscv32 +#define helper_gvec_le64 helper_gvec_le64_riscv32 +#define helper_gvec_leu8 helper_gvec_leu8_riscv32 +#define helper_gvec_leu16 helper_gvec_leu16_riscv32 +#define helper_gvec_leu32 helper_gvec_leu32_riscv32 +#define helper_gvec_leu64 helper_gvec_leu64_riscv32 +#define helper_gvec_lt8 helper_gvec_lt8_riscv32 +#define helper_gvec_lt16 helper_gvec_lt16_riscv32 +#define helper_gvec_lt32 helper_gvec_lt32_riscv32 +#define helper_gvec_lt64 helper_gvec_lt64_riscv32 +#define helper_gvec_ltu8 helper_gvec_ltu8_riscv32 +#define helper_gvec_ltu16 helper_gvec_ltu16_riscv32 +#define helper_gvec_ltu32 helper_gvec_ltu32_riscv32 +#define helper_gvec_ltu64 helper_gvec_ltu64_riscv32 +#define helper_gvec_mov helper_gvec_mov_riscv32 +#define helper_gvec_mul8 helper_gvec_mul8_riscv32 +#define helper_gvec_mul16 helper_gvec_mul16_riscv32 +#define helper_gvec_mul32 helper_gvec_mul32_riscv32 +#define helper_gvec_mul64 helper_gvec_mul64_riscv32 +#define helper_gvec_muls8 helper_gvec_muls8_riscv32 +#define helper_gvec_muls16 helper_gvec_muls16_riscv32 +#define helper_gvec_muls32 helper_gvec_muls32_riscv32 +#define helper_gvec_muls64 helper_gvec_muls64_riscv32 +#define helper_gvec_ne8 helper_gvec_ne8_riscv32 +#define helper_gvec_ne16 helper_gvec_ne16_riscv32 +#define helper_gvec_ne32 helper_gvec_ne32_riscv32 +#define helper_gvec_ne64 helper_gvec_ne64_riscv32 +#define helper_gvec_neg8 helper_gvec_neg8_riscv32 +#define helper_gvec_neg16 helper_gvec_neg16_riscv32 +#define helper_gvec_neg32 helper_gvec_neg32_riscv32 +#define helper_gvec_neg64 helper_gvec_neg64_riscv32 +#define helper_gvec_not helper_gvec_not_riscv32 +#define helper_gvec_or helper_gvec_or_riscv32 +#define helper_gvec_orc helper_gvec_orc_riscv32 +#define helper_gvec_ors helper_gvec_ors_riscv32 +#define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_riscv32 +#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_riscv32 +#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv32 +#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_riscv32 +#define helper_gvec_sar8i helper_gvec_sar8i_riscv32 +#define helper_gvec_sar16i helper_gvec_sar16i_riscv32 +#define helper_gvec_sar32i helper_gvec_sar32i_riscv32 +#define helper_gvec_sar64i helper_gvec_sar64i_riscv32 +#define helper_gvec_sdot_b helper_gvec_sdot_b_riscv32 +#define helper_gvec_sdot_h helper_gvec_sdot_h_riscv32 +#define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_riscv32 +#define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_riscv32 +#define helper_gvec_shl8i helper_gvec_shl8i_riscv32 +#define helper_gvec_shl16i helper_gvec_shl16i_riscv32 +#define helper_gvec_shl32i helper_gvec_shl32i_riscv32 +#define helper_gvec_shl64i helper_gvec_shl64i_riscv32 +#define helper_gvec_shr8i helper_gvec_shr8i_riscv32 +#define helper_gvec_shr16i helper_gvec_shr16i_riscv32 +#define helper_gvec_shr32i helper_gvec_shr32i_riscv32 +#define helper_gvec_shr64i helper_gvec_shr64i_riscv32 +#define helper_gvec_sub8 helper_gvec_sub8_riscv32 +#define helper_gvec_sub16 helper_gvec_sub16_riscv32 +#define helper_gvec_sub32 helper_gvec_sub32_riscv32 +#define helper_gvec_sub64 helper_gvec_sub64_riscv32 +#define helper_gvec_subs8 helper_gvec_subs8_riscv32 +#define helper_gvec_subs16 helper_gvec_subs16_riscv32 +#define helper_gvec_subs32 helper_gvec_subs32_riscv32 +#define helper_gvec_subs64 helper_gvec_subs64_riscv32 +#define helper_gvec_ssadd8 helper_gvec_ssadd8_riscv32 +#define helper_gvec_ssadd16 helper_gvec_ssadd16_riscv32 +#define helper_gvec_ssadd32 helper_gvec_ssadd32_riscv32 +#define helper_gvec_ssadd64 helper_gvec_ssadd64_riscv32 +#define helper_gvec_sssub8 helper_gvec_sssub8_riscv32 +#define helper_gvec_sssub16 helper_gvec_sssub16_riscv32 +#define helper_gvec_sssub32 helper_gvec_sssub32_riscv32 +#define helper_gvec_sssub64 helper_gvec_sssub64_riscv32 +#define helper_gvec_udot_b helper_gvec_udot_b_riscv32 +#define helper_gvec_udot_h helper_gvec_udot_h_riscv32 +#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_riscv32 +#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_riscv32 +#define helper_gvec_usadd8 helper_gvec_usadd8_riscv32 +#define helper_gvec_usadd16 helper_gvec_usadd16_riscv32 +#define helper_gvec_usadd32 helper_gvec_usadd32_riscv32 +#define helper_gvec_usadd64 helper_gvec_usadd64_riscv32 +#define helper_gvec_ussub8 helper_gvec_ussub8_riscv32 +#define helper_gvec_ussub16 helper_gvec_ussub16_riscv32 +#define helper_gvec_ussub32 helper_gvec_ussub32_riscv32 +#define helper_gvec_ussub64 helper_gvec_ussub64_riscv32 +#define helper_gvec_xor helper_gvec_xor_riscv32 +#define helper_gvec_xors helper_gvec_xors_riscv32 +#define helper_iwmmxt_addcb helper_iwmmxt_addcb_riscv32 +#define helper_iwmmxt_addcl helper_iwmmxt_addcl_riscv32 +#define helper_iwmmxt_addcw helper_iwmmxt_addcw_riscv32 +#define helper_iwmmxt_addnb helper_iwmmxt_addnb_riscv32 +#define helper_iwmmxt_addnl helper_iwmmxt_addnl_riscv32 +#define helper_iwmmxt_addnw helper_iwmmxt_addnw_riscv32 +#define helper_iwmmxt_addsb helper_iwmmxt_addsb_riscv32 +#define helper_iwmmxt_addsl helper_iwmmxt_addsl_riscv32 +#define helper_iwmmxt_addsw helper_iwmmxt_addsw_riscv32 +#define helper_iwmmxt_addub helper_iwmmxt_addub_riscv32 +#define helper_iwmmxt_addul helper_iwmmxt_addul_riscv32 +#define helper_iwmmxt_adduw helper_iwmmxt_adduw_riscv32 +#define helper_iwmmxt_align helper_iwmmxt_align_riscv32 +#define helper_iwmmxt_avgb0 helper_iwmmxt_avgb0_riscv32 +#define helper_iwmmxt_avgb1 helper_iwmmxt_avgb1_riscv32 +#define helper_iwmmxt_avgw0 helper_iwmmxt_avgw0_riscv32 +#define helper_iwmmxt_avgw1 helper_iwmmxt_avgw1_riscv32 +#define helper_iwmmxt_bcstb helper_iwmmxt_bcstb_riscv32 +#define helper_iwmmxt_bcstl helper_iwmmxt_bcstl_riscv32 +#define helper_iwmmxt_bcstw helper_iwmmxt_bcstw_riscv32 +#define helper_iwmmxt_cmpeqb helper_iwmmxt_cmpeqb_riscv32 +#define helper_iwmmxt_cmpeql helper_iwmmxt_cmpeql_riscv32 +#define helper_iwmmxt_cmpeqw helper_iwmmxt_cmpeqw_riscv32 +#define helper_iwmmxt_cmpgtsb helper_iwmmxt_cmpgtsb_riscv32 +#define helper_iwmmxt_cmpgtsl helper_iwmmxt_cmpgtsl_riscv32 +#define helper_iwmmxt_cmpgtsw helper_iwmmxt_cmpgtsw_riscv32 +#define helper_iwmmxt_cmpgtub helper_iwmmxt_cmpgtub_riscv32 +#define helper_iwmmxt_cmpgtul helper_iwmmxt_cmpgtul_riscv32 +#define helper_iwmmxt_cmpgtuw helper_iwmmxt_cmpgtuw_riscv32 +#define helper_iwmmxt_insr helper_iwmmxt_insr_riscv32 +#define helper_iwmmxt_macsw helper_iwmmxt_macsw_riscv32 +#define helper_iwmmxt_macuw helper_iwmmxt_macuw_riscv32 +#define helper_iwmmxt_maddsq helper_iwmmxt_maddsq_riscv32 +#define helper_iwmmxt_madduq helper_iwmmxt_madduq_riscv32 +#define helper_iwmmxt_maxsb helper_iwmmxt_maxsb_riscv32 +#define helper_iwmmxt_maxsl helper_iwmmxt_maxsl_riscv32 +#define helper_iwmmxt_maxsw helper_iwmmxt_maxsw_riscv32 +#define helper_iwmmxt_maxub helper_iwmmxt_maxub_riscv32 +#define helper_iwmmxt_maxul helper_iwmmxt_maxul_riscv32 +#define helper_iwmmxt_maxuw helper_iwmmxt_maxuw_riscv32 +#define helper_iwmmxt_minsb helper_iwmmxt_minsb_riscv32 +#define helper_iwmmxt_minsl helper_iwmmxt_minsl_riscv32 +#define helper_iwmmxt_minsw helper_iwmmxt_minsw_riscv32 +#define helper_iwmmxt_minub helper_iwmmxt_minub_riscv32 +#define helper_iwmmxt_minul helper_iwmmxt_minul_riscv32 +#define helper_iwmmxt_minuw helper_iwmmxt_minuw_riscv32 +#define helper_iwmmxt_msbb helper_iwmmxt_msbb_riscv32 +#define helper_iwmmxt_msbl helper_iwmmxt_msbl_riscv32 +#define helper_iwmmxt_msbw helper_iwmmxt_msbw_riscv32 +#define helper_iwmmxt_muladdsl helper_iwmmxt_muladdsl_riscv32 +#define helper_iwmmxt_muladdsw helper_iwmmxt_muladdsw_riscv32 +#define helper_iwmmxt_muladdswl helper_iwmmxt_muladdswl_riscv32 +#define helper_iwmmxt_mulshw helper_iwmmxt_mulshw_riscv32 +#define helper_iwmmxt_mulslw helper_iwmmxt_mulslw_riscv32 +#define helper_iwmmxt_muluhw helper_iwmmxt_muluhw_riscv32 +#define helper_iwmmxt_mululw helper_iwmmxt_mululw_riscv32 +#define helper_iwmmxt_packsl helper_iwmmxt_packsl_riscv32 +#define helper_iwmmxt_packsq helper_iwmmxt_packsq_riscv32 +#define helper_iwmmxt_packsw helper_iwmmxt_packsw_riscv32 +#define helper_iwmmxt_packul helper_iwmmxt_packul_riscv32 +#define helper_iwmmxt_packuq helper_iwmmxt_packuq_riscv32 +#define helper_iwmmxt_packuw helper_iwmmxt_packuw_riscv32 +#define helper_iwmmxt_rorl helper_iwmmxt_rorl_riscv32 +#define helper_iwmmxt_rorq helper_iwmmxt_rorq_riscv32 +#define helper_iwmmxt_rorw helper_iwmmxt_rorw_riscv32 +#define helper_iwmmxt_sadb helper_iwmmxt_sadb_riscv32 +#define helper_iwmmxt_sadw helper_iwmmxt_sadw_riscv32 +#define helper_iwmmxt_setpsr_nz helper_iwmmxt_setpsr_nz_riscv32 +#define helper_iwmmxt_shufh helper_iwmmxt_shufh_riscv32 +#define helper_iwmmxt_slll helper_iwmmxt_slll_riscv32 +#define helper_iwmmxt_sllq helper_iwmmxt_sllq_riscv32 +#define helper_iwmmxt_sllw helper_iwmmxt_sllw_riscv32 +#define helper_iwmmxt_sral helper_iwmmxt_sral_riscv32 +#define helper_iwmmxt_sraq helper_iwmmxt_sraq_riscv32 +#define helper_iwmmxt_sraw helper_iwmmxt_sraw_riscv32 +#define helper_iwmmxt_srll helper_iwmmxt_srll_riscv32 +#define helper_iwmmxt_srlq helper_iwmmxt_srlq_riscv32 +#define helper_iwmmxt_srlw helper_iwmmxt_srlw_riscv32 +#define helper_iwmmxt_subnb helper_iwmmxt_subnb_riscv32 +#define helper_iwmmxt_subnl helper_iwmmxt_subnl_riscv32 +#define helper_iwmmxt_subnw helper_iwmmxt_subnw_riscv32 +#define helper_iwmmxt_subsb helper_iwmmxt_subsb_riscv32 +#define helper_iwmmxt_subsl helper_iwmmxt_subsl_riscv32 +#define helper_iwmmxt_subsw helper_iwmmxt_subsw_riscv32 +#define helper_iwmmxt_subub helper_iwmmxt_subub_riscv32 +#define helper_iwmmxt_subul helper_iwmmxt_subul_riscv32 +#define helper_iwmmxt_subuw helper_iwmmxt_subuw_riscv32 +#define helper_iwmmxt_unpackhb helper_iwmmxt_unpackhb_riscv32 +#define helper_iwmmxt_unpackhl helper_iwmmxt_unpackhl_riscv32 +#define helper_iwmmxt_unpackhsb helper_iwmmxt_unpackhsb_riscv32 +#define helper_iwmmxt_unpackhsl helper_iwmmxt_unpackhsl_riscv32 +#define helper_iwmmxt_unpackhsw helper_iwmmxt_unpackhsw_riscv32 +#define helper_iwmmxt_unpackhub helper_iwmmxt_unpackhub_riscv32 +#define helper_iwmmxt_unpackhul helper_iwmmxt_unpackhul_riscv32 +#define helper_iwmmxt_unpackhuw helper_iwmmxt_unpackhuw_riscv32 +#define helper_iwmmxt_unpackhw helper_iwmmxt_unpackhw_riscv32 +#define helper_iwmmxt_unpacklb helper_iwmmxt_unpacklb_riscv32 +#define helper_iwmmxt_unpackll helper_iwmmxt_unpackll_riscv32 +#define helper_iwmmxt_unpacklsb helper_iwmmxt_unpacklsb_riscv32 +#define helper_iwmmxt_unpacklsl helper_iwmmxt_unpacklsl_riscv32 +#define helper_iwmmxt_unpacklsw helper_iwmmxt_unpacklsw_riscv32 +#define helper_iwmmxt_unpacklub helper_iwmmxt_unpacklub_riscv32 +#define helper_iwmmxt_unpacklul helper_iwmmxt_unpacklul_riscv32 +#define helper_iwmmxt_unpackluw helper_iwmmxt_unpackluw_riscv32 +#define helper_iwmmxt_unpacklw helper_iwmmxt_unpacklw_riscv32 +#define helper_ldb_cmmu helper_ldb_cmmu_riscv32 +#define helper_ldb_mmu helper_ldb_mmu_riscv32 +#define helper_ldl_cmmu helper_ldl_cmmu_riscv32 +#define helper_ldl_mmu helper_ldl_mmu_riscv32 +#define helper_ldq_cmmu helper_ldq_cmmu_riscv32 +#define helper_ldq_mmu helper_ldq_mmu_riscv32 +#define helper_ldw_cmmu helper_ldw_cmmu_riscv32 +#define helper_ldw_mmu helper_ldw_mmu_riscv32 +#define helper_le_ldl_cmmu helper_le_ldl_cmmu_riscv32 +#define helper_le_ldq_cmmu helper_le_ldq_cmmu_riscv32 +#define helper_le_ldq_mmu helper_le_ldq_mmu_riscv32 +#define helper_le_ldsl_mmu helper_le_ldsl_mmu_riscv32 +#define helper_le_ldsw_mmu helper_le_ldsw_mmu_riscv32 +#define helper_le_ldul_mmu helper_le_ldul_mmu_riscv32 +#define helper_le_lduw_mmu helper_le_lduw_mmu_riscv32 +#define helper_le_ldw_cmmu helper_le_ldw_cmmu_riscv32 +#define helper_le_stl_mmu helper_le_stl_mmu_riscv32 +#define helper_le_stq_mmu helper_le_stq_mmu_riscv32 +#define helper_le_stw_mmu helper_le_stw_mmu_riscv32 +#define helper_lookup_tb_ptr helper_lookup_tb_ptr_riscv32 +#define helper_mulsh_i32 helper_mulsh_i32_riscv32 +#define helper_mulsh_i64 helper_mulsh_i64_riscv32 +#define helper_muluh_i32 helper_muluh_i32_riscv32 +#define helper_muluh_i64 helper_muluh_i64_riscv32 +#define helper_mrs_banked helper_mrs_banked_riscv32 +#define helper_msa_ld_b helper_msa_ld_b_riscv32 +#define helper_msa_ld_d helper_msa_ld_d_riscv32 +#define helper_msa_ld_h helper_msa_ld_h_riscv32 +#define helper_msa_ld_w helper_msa_ld_w_riscv32 +#define helper_msa_st_b helper_msa_st_b_riscv32 +#define helper_msa_st_d helper_msa_st_d_riscv32 +#define helper_msa_st_h helper_msa_st_h_riscv32 +#define helper_msa_st_w helper_msa_st_w_riscv32 +#define helper_msr_banked helper_msr_banked_riscv32 +#define helper_msr_i_pstate helper_msr_i_pstate_riscv32 +#define helper_neon_abd_f32 helper_neon_abd_f32_riscv32 +#define helper_neon_abd_s16 helper_neon_abd_s16_riscv32 +#define helper_neon_abd_s32 helper_neon_abd_s32_riscv32 +#define helper_neon_abd_s8 helper_neon_abd_s8_riscv32 +#define helper_neon_abd_u16 helper_neon_abd_u16_riscv32 +#define helper_neon_abd_u32 helper_neon_abd_u32_riscv32 +#define helper_neon_abd_u8 helper_neon_abd_u8_riscv32 +#define helper_neon_abdl_s16 helper_neon_abdl_s16_riscv32 +#define helper_neon_abdl_s32 helper_neon_abdl_s32_riscv32 +#define helper_neon_abdl_s64 helper_neon_abdl_s64_riscv32 +#define helper_neon_abdl_u16 helper_neon_abdl_u16_riscv32 +#define helper_neon_abdl_u32 helper_neon_abdl_u32_riscv32 +#define helper_neon_abdl_u64 helper_neon_abdl_u64_riscv32 +#define helper_neon_abs_s16 helper_neon_abs_s16_riscv32 +#define helper_neon_abs_s8 helper_neon_abs_s8_riscv32 +#define helper_neon_acge_f32 helper_neon_acge_f32_riscv32 +#define helper_neon_acge_f64 helper_neon_acge_f64_riscv32 +#define helper_neon_acgt_f32 helper_neon_acgt_f32_riscv32 +#define helper_neon_acgt_f64 helper_neon_acgt_f64_riscv32 +#define helper_neon_add_u16 helper_neon_add_u16_riscv32 +#define helper_neon_add_u8 helper_neon_add_u8_riscv32 +#define helper_neon_addl_saturate_s32 helper_neon_addl_saturate_s32_riscv32 +#define helper_neon_addl_saturate_s64 helper_neon_addl_saturate_s64_riscv32 +#define helper_neon_addl_u16 helper_neon_addl_u16_riscv32 +#define helper_neon_addl_u32 helper_neon_addl_u32_riscv32 +#define helper_neon_ceq_f32 helper_neon_ceq_f32_riscv32 +#define helper_neon_ceq_u16 helper_neon_ceq_u16_riscv32 +#define helper_neon_ceq_u32 helper_neon_ceq_u32_riscv32 +#define helper_neon_ceq_u8 helper_neon_ceq_u8_riscv32 +#define helper_neon_cge_f32 helper_neon_cge_f32_riscv32 +#define helper_neon_cge_s16 helper_neon_cge_s16_riscv32 +#define helper_neon_cge_s32 helper_neon_cge_s32_riscv32 +#define helper_neon_cge_s8 helper_neon_cge_s8_riscv32 +#define helper_neon_cge_u16 helper_neon_cge_u16_riscv32 +#define helper_neon_cge_u32 helper_neon_cge_u32_riscv32 +#define helper_neon_cge_u8 helper_neon_cge_u8_riscv32 +#define helper_neon_cgt_f32 helper_neon_cgt_f32_riscv32 +#define helper_neon_cgt_s16 helper_neon_cgt_s16_riscv32 +#define helper_neon_cgt_s32 helper_neon_cgt_s32_riscv32 +#define helper_neon_cgt_s8 helper_neon_cgt_s8_riscv32 +#define helper_neon_cgt_u16 helper_neon_cgt_u16_riscv32 +#define helper_neon_cgt_u32 helper_neon_cgt_u32_riscv32 +#define helper_neon_cgt_u8 helper_neon_cgt_u8_riscv32 +#define helper_neon_cls_s16 helper_neon_cls_s16_riscv32 +#define helper_neon_cls_s32 helper_neon_cls_s32_riscv32 +#define helper_neon_cls_s8 helper_neon_cls_s8_riscv32 +#define helper_neon_clz_u16 helper_neon_clz_u16_riscv32 +#define helper_neon_clz_u8 helper_neon_clz_u8_riscv32 +#define helper_neon_cnt_u8 helper_neon_cnt_u8_riscv32 +#define helper_neon_fcvt_f16_to_f32 helper_neon_fcvt_f16_to_f32_riscv32 +#define helper_neon_fcvt_f32_to_f16 helper_neon_fcvt_f32_to_f16_riscv32 +#define helper_neon_hadd_s16 helper_neon_hadd_s16_riscv32 +#define helper_neon_hadd_s32 helper_neon_hadd_s32_riscv32 +#define helper_neon_hadd_s8 helper_neon_hadd_s8_riscv32 +#define helper_neon_hadd_u16 helper_neon_hadd_u16_riscv32 +#define helper_neon_hadd_u32 helper_neon_hadd_u32_riscv32 +#define helper_neon_hadd_u8 helper_neon_hadd_u8_riscv32 +#define helper_neon_hsub_s16 helper_neon_hsub_s16_riscv32 +#define helper_neon_hsub_s32 helper_neon_hsub_s32_riscv32 +#define helper_neon_hsub_s8 helper_neon_hsub_s8_riscv32 +#define helper_neon_hsub_u16 helper_neon_hsub_u16_riscv32 +#define helper_neon_hsub_u32 helper_neon_hsub_u32_riscv32 +#define helper_neon_hsub_u8 helper_neon_hsub_u8_riscv32 +#define helper_neon_max_s16 helper_neon_max_s16_riscv32 +#define helper_neon_max_s32 helper_neon_max_s32_riscv32 +#define helper_neon_max_s8 helper_neon_max_s8_riscv32 +#define helper_neon_max_u16 helper_neon_max_u16_riscv32 +#define helper_neon_max_u32 helper_neon_max_u32_riscv32 +#define helper_neon_max_u8 helper_neon_max_u8_riscv32 +#define helper_neon_min_s16 helper_neon_min_s16_riscv32 +#define helper_neon_min_s32 helper_neon_min_s32_riscv32 +#define helper_neon_min_s8 helper_neon_min_s8_riscv32 +#define helper_neon_min_u16 helper_neon_min_u16_riscv32 +#define helper_neon_min_u32 helper_neon_min_u32_riscv32 +#define helper_neon_min_u8 helper_neon_min_u8_riscv32 +#define helper_neon_mul_p8 helper_neon_mul_p8_riscv32 +#define helper_neon_mul_u16 helper_neon_mul_u16_riscv32 +#define helper_neon_mul_u8 helper_neon_mul_u8_riscv32 +#define helper_neon_mull_p8 helper_neon_mull_p8_riscv32 +#define helper_neon_mull_s16 helper_neon_mull_s16_riscv32 +#define helper_neon_mull_s8 helper_neon_mull_s8_riscv32 +#define helper_neon_mull_u16 helper_neon_mull_u16_riscv32 +#define helper_neon_mull_u8 helper_neon_mull_u8_riscv32 +#define helper_neon_narrow_high_u16 helper_neon_narrow_high_u16_riscv32 +#define helper_neon_narrow_high_u8 helper_neon_narrow_high_u8_riscv32 +#define helper_neon_narrow_round_high_u16 helper_neon_narrow_round_high_u16_riscv32 +#define helper_neon_narrow_round_high_u8 helper_neon_narrow_round_high_u8_riscv32 +#define helper_neon_narrow_sat_s16 helper_neon_narrow_sat_s16_riscv32 +#define helper_neon_narrow_sat_s32 helper_neon_narrow_sat_s32_riscv32 +#define helper_neon_narrow_sat_s8 helper_neon_narrow_sat_s8_riscv32 +#define helper_neon_narrow_sat_u16 helper_neon_narrow_sat_u16_riscv32 +#define helper_neon_narrow_sat_u32 helper_neon_narrow_sat_u32_riscv32 +#define helper_neon_narrow_sat_u8 helper_neon_narrow_sat_u8_riscv32 +#define helper_neon_narrow_u16 helper_neon_narrow_u16_riscv32 +#define helper_neon_narrow_u8 helper_neon_narrow_u8_riscv32 +#define helper_neon_negl_u16 helper_neon_negl_u16_riscv32 +#define helper_neon_negl_u32 helper_neon_negl_u32_riscv32 +#define helper_neon_padd_u16 helper_neon_padd_u16_riscv32 +#define helper_neon_padd_u8 helper_neon_padd_u8_riscv32 +#define helper_neon_paddl_u16 helper_neon_paddl_u16_riscv32 +#define helper_neon_paddl_u32 helper_neon_paddl_u32_riscv32 +#define helper_neon_pmax_s16 helper_neon_pmax_s16_riscv32 +#define helper_neon_pmax_s8 helper_neon_pmax_s8_riscv32 +#define helper_neon_pmax_u16 helper_neon_pmax_u16_riscv32 +#define helper_neon_pmax_u8 helper_neon_pmax_u8_riscv32 +#define helper_neon_pmin_s16 helper_neon_pmin_s16_riscv32 +#define helper_neon_pmin_s8 helper_neon_pmin_s8_riscv32 +#define helper_neon_pmin_u16 helper_neon_pmin_u16_riscv32 +#define helper_neon_pmin_u8 helper_neon_pmin_u8_riscv32 +#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_riscv32 +#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_riscv32 +#define helper_neon_qabs_s16 helper_neon_qabs_s16_riscv32 +#define helper_neon_qabs_s32 helper_neon_qabs_s32_riscv32 +#define helper_neon_qabs_s64 helper_neon_qabs_s64_riscv32 +#define helper_neon_qabs_s8 helper_neon_qabs_s8_riscv32 +#define helper_neon_qadd_s16 helper_neon_qadd_s16_riscv32 +#define helper_neon_qadd_s32 helper_neon_qadd_s32_riscv32 +#define helper_neon_qadd_s64 helper_neon_qadd_s64_riscv32 +#define helper_neon_qadd_s8 helper_neon_qadd_s8_riscv32 +#define helper_neon_qadd_u16 helper_neon_qadd_u16_riscv32 +#define helper_neon_qadd_u32 helper_neon_qadd_u32_riscv32 +#define helper_neon_qadd_u64 helper_neon_qadd_u64_riscv32 +#define helper_neon_qadd_u8 helper_neon_qadd_u8_riscv32 +#define helper_neon_qdmulh_s16 helper_neon_qdmulh_s16_riscv32 +#define helper_neon_qdmulh_s32 helper_neon_qdmulh_s32_riscv32 +#define helper_neon_qneg_s16 helper_neon_qneg_s16_riscv32 +#define helper_neon_qneg_s32 helper_neon_qneg_s32_riscv32 +#define helper_neon_qneg_s64 helper_neon_qneg_s64_riscv32 +#define helper_neon_qneg_s8 helper_neon_qneg_s8_riscv32 +#define helper_neon_qrdmlah_s16 helper_neon_qrdmlah_s16_riscv32 +#define helper_neon_qrdmlah_s32 helper_neon_qrdmlah_s32_riscv32 +#define helper_neon_qrdmlsh_s16 helper_neon_qrdmlsh_s16_riscv32 +#define helper_neon_qrdmlsh_s32 helper_neon_qrdmlsh_s32_riscv32 +#define helper_neon_qrdmulh_s16 helper_neon_qrdmulh_s16_riscv32 +#define helper_neon_qrdmulh_s32 helper_neon_qrdmulh_s32_riscv32 +#define helper_neon_qrshl_s16 helper_neon_qrshl_s16_riscv32 +#define helper_neon_qrshl_s32 helper_neon_qrshl_s32_riscv32 +#define helper_neon_qrshl_s64 helper_neon_qrshl_s64_riscv32 +#define helper_neon_qrshl_s8 helper_neon_qrshl_s8_riscv32 +#define helper_neon_qrshl_u16 helper_neon_qrshl_u16_riscv32 +#define helper_neon_qrshl_u32 helper_neon_qrshl_u32_riscv32 +#define helper_neon_qrshl_u64 helper_neon_qrshl_u64_riscv32 +#define helper_neon_qrshl_u8 helper_neon_qrshl_u8_riscv32 +#define helper_neon_qshl_s16 helper_neon_qshl_s16_riscv32 +#define helper_neon_qshl_s32 helper_neon_qshl_s32_riscv32 +#define helper_neon_qshl_s64 helper_neon_qshl_s64_riscv32 +#define helper_neon_qshl_s8 helper_neon_qshl_s8_riscv32 +#define helper_neon_qshl_u16 helper_neon_qshl_u16_riscv32 +#define helper_neon_qshl_u32 helper_neon_qshl_u32_riscv32 +#define helper_neon_qshl_u64 helper_neon_qshl_u64_riscv32 +#define helper_neon_qshl_u8 helper_neon_qshl_u8_riscv32 +#define helper_neon_qshlu_s16 helper_neon_qshlu_s16_riscv32 +#define helper_neon_qshlu_s32 helper_neon_qshlu_s32_riscv32 +#define helper_neon_qshlu_s64 helper_neon_qshlu_s64_riscv32 +#define helper_neon_qshlu_s8 helper_neon_qshlu_s8_riscv32 +#define helper_neon_qsub_s16 helper_neon_qsub_s16_riscv32 +#define helper_neon_qsub_s32 helper_neon_qsub_s32_riscv32 +#define helper_neon_qsub_s64 helper_neon_qsub_s64_riscv32 +#define helper_neon_qsub_s8 helper_neon_qsub_s8_riscv32 +#define helper_neon_qsub_u16 helper_neon_qsub_u16_riscv32 +#define helper_neon_qsub_u32 helper_neon_qsub_u32_riscv32 +#define helper_neon_qsub_u64 helper_neon_qsub_u64_riscv32 +#define helper_neon_qsub_u8 helper_neon_qsub_u8_riscv32 +#define helper_neon_qunzip16 helper_neon_qunzip16_riscv32 +#define helper_neon_qunzip32 helper_neon_qunzip32_riscv32 +#define helper_neon_qunzip8 helper_neon_qunzip8_riscv32 +#define helper_neon_qzip16 helper_neon_qzip16_riscv32 +#define helper_neon_qzip32 helper_neon_qzip32_riscv32 +#define helper_neon_qzip8 helper_neon_qzip8_riscv32 +#define helper_neon_rbit_u8 helper_neon_rbit_u8_riscv32 +#define helper_neon_rhadd_s16 helper_neon_rhadd_s16_riscv32 +#define helper_neon_rhadd_s32 helper_neon_rhadd_s32_riscv32 +#define helper_neon_rhadd_s8 helper_neon_rhadd_s8_riscv32 +#define helper_neon_rhadd_u16 helper_neon_rhadd_u16_riscv32 +#define helper_neon_rhadd_u32 helper_neon_rhadd_u32_riscv32 +#define helper_neon_rhadd_u8 helper_neon_rhadd_u8_riscv32 +#define helper_neon_rshl_s16 helper_neon_rshl_s16_riscv32 +#define helper_neon_rshl_s32 helper_neon_rshl_s32_riscv32 +#define helper_neon_rshl_s64 helper_neon_rshl_s64_riscv32 +#define helper_neon_rshl_s8 helper_neon_rshl_s8_riscv32 +#define helper_neon_rshl_u16 helper_neon_rshl_u16_riscv32 +#define helper_neon_rshl_u32 helper_neon_rshl_u32_riscv32 +#define helper_neon_rshl_u64 helper_neon_rshl_u64_riscv32 +#define helper_neon_rshl_u8 helper_neon_rshl_u8_riscv32 +#define helper_neon_shl_s16 helper_neon_shl_s16_riscv32 +#define helper_neon_shl_s32 helper_neon_shl_s32_riscv32 +#define helper_neon_shl_s64 helper_neon_shl_s64_riscv32 +#define helper_neon_shl_s8 helper_neon_shl_s8_riscv32 +#define helper_neon_shl_u16 helper_neon_shl_u16_riscv32 +#define helper_neon_shl_u32 helper_neon_shl_u32_riscv32 +#define helper_neon_shl_u64 helper_neon_shl_u64_riscv32 +#define helper_neon_shl_u8 helper_neon_shl_u8_riscv32 +#define helper_neon_sqadd_u16 helper_neon_sqadd_u16_riscv32 +#define helper_neon_sqadd_u32 helper_neon_sqadd_u32_riscv32 +#define helper_neon_sqadd_u64 helper_neon_sqadd_u64_riscv32 +#define helper_neon_sqadd_u8 helper_neon_sqadd_u8_riscv32 +#define helper_neon_sub_u16 helper_neon_sub_u16_riscv32 +#define helper_neon_sub_u8 helper_neon_sub_u8_riscv32 +#define helper_neon_subl_u16 helper_neon_subl_u16_riscv32 +#define helper_neon_subl_u32 helper_neon_subl_u32_riscv32 +#define helper_neon_tbl helper_neon_tbl_riscv32 +#define helper_neon_tst_u16 helper_neon_tst_u16_riscv32 +#define helper_neon_tst_u32 helper_neon_tst_u32_riscv32 +#define helper_neon_tst_u8 helper_neon_tst_u8_riscv32 +#define helper_neon_unarrow_sat16 helper_neon_unarrow_sat16_riscv32 +#define helper_neon_unarrow_sat32 helper_neon_unarrow_sat32_riscv32 +#define helper_neon_unarrow_sat8 helper_neon_unarrow_sat8_riscv32 +#define helper_neon_unzip16 helper_neon_unzip16_riscv32 +#define helper_neon_unzip8 helper_neon_unzip8_riscv32 +#define helper_neon_uqadd_s16 helper_neon_uqadd_s16_riscv32 +#define helper_neon_uqadd_s32 helper_neon_uqadd_s32_riscv32 +#define helper_neon_uqadd_s64 helper_neon_uqadd_s64_riscv32 +#define helper_neon_uqadd_s8 helper_neon_uqadd_s8_riscv32 +#define helper_neon_widen_s16 helper_neon_widen_s16_riscv32 +#define helper_neon_widen_s8 helper_neon_widen_s8_riscv32 +#define helper_neon_widen_u16 helper_neon_widen_u16_riscv32 +#define helper_neon_widen_u8 helper_neon_widen_u8_riscv32 +#define helper_neon_zip16 helper_neon_zip16_riscv32 +#define helper_neon_zip8 helper_neon_zip8_riscv32 +#define helper_power_down helper_power_down_riscv32 +#define helper_pre_hvc helper_pre_hvc_riscv32 +#define helper_pre_smc helper_pre_smc_riscv32 +#define helper_qadd16 helper_qadd16_riscv32 +#define helper_qadd8 helper_qadd8_riscv32 +#define helper_qaddsubx helper_qaddsubx_riscv32 +#define helper_qsub16 helper_qsub16_riscv32 +#define helper_qsub8 helper_qsub8_riscv32 +#define helper_qsubaddx helper_qsubaddx_riscv32 +#define helper_raise_exception helper_raise_exception_riscv32 +#define helper_rbit helper_rbit_riscv32 +#define helper_recpe_f16 helper_recpe_f16_riscv32 +#define helper_recpe_f32 helper_recpe_f32_riscv32 +#define helper_recpe_f64 helper_recpe_f64_riscv32 +#define helper_recpe_u32 helper_recpe_u32_riscv32 +#define helper_recps_f32 helper_recps_f32_riscv32 +#define helper_rem_i32 helper_rem_i32_riscv32 +#define helper_rem_i64 helper_rem_i64_riscv32 +#define helper_remu_i32 helper_remu_i32_riscv32 +#define helper_remu_i64 helper_remu_i64_riscv32 +#define helper_ret_ldb_cmmu helper_ret_ldb_cmmu_riscv32 +#define helper_ret_ldsb_mmu helper_ret_ldsb_mmu_riscv32 +#define helper_ret_ldub_mmu helper_ret_ldub_mmu_riscv32 +#define helper_ret_stb_mmu helper_ret_stb_mmu_riscv32 +#define helper_rintd helper_rintd_riscv32 +#define helper_rintd_exact helper_rintd_exact_riscv32 +#define helper_rints helper_rints_riscv32 +#define helper_rints_exact helper_rints_exact_riscv32 +#define helper_ror_cc helper_ror_cc_riscv32 +#define helper_rsqrte_f16 helper_rsqrte_f16_riscv32 +#define helper_rsqrte_f32 helper_rsqrte_f32_riscv32 +#define helper_rsqrte_f64 helper_rsqrte_f64_riscv32 +#define helper_rsqrte_u32 helper_rsqrte_u32_riscv32 +#define helper_rsqrts_f32 helper_rsqrts_f32_riscv32 +#define helper_sadd16 helper_sadd16_riscv32 +#define helper_sadd8 helper_sadd8_riscv32 +#define helper_saddsubx helper_saddsubx_riscv32 +#define helper_sar_cc helper_sar_cc_riscv32 +#define helper_sar_i32 helper_sar_i32_riscv32 +#define helper_sar_i64 helper_sar_i64_riscv32 +#define helper_sdiv helper_sdiv_riscv32 +#define helper_sel_flags helper_sel_flags_riscv32 +#define helper_set_cp_reg helper_set_cp_reg_riscv32 +#define helper_set_cp_reg64 helper_set_cp_reg64_riscv32 +#define helper_set_neon_rmode helper_set_neon_rmode_riscv32 +#define helper_set_r13_banked helper_set_r13_banked_riscv32 +#define helper_set_rmode helper_set_rmode_riscv32 +#define helper_set_user_reg helper_set_user_reg_riscv32 +#define helper_setend helper_setend_riscv32 +#define helper_shadd16 helper_shadd16_riscv32 +#define helper_shadd8 helper_shadd8_riscv32 +#define helper_shaddsubx helper_shaddsubx_riscv32 +#define helper_shl_cc helper_shl_cc_riscv32 +#define helper_shl_i64 helper_shl_i64_riscv32 +#define helper_shr_cc helper_shr_cc_riscv32 +#define helper_shr_i32 helper_shr_i32_riscv32 +#define helper_shr_i64 helper_shr_i64_riscv32 +#define helper_shsub16 helper_shsub16_riscv32 +#define helper_shsub8 helper_shsub8_riscv32 +#define helper_shsubaddx helper_shsubaddx_riscv32 +#define helper_ssat helper_ssat_riscv32 +#define helper_ssat16 helper_ssat16_riscv32 +#define helper_ssub16 helper_ssub16_riscv32 +#define helper_ssub8 helper_ssub8_riscv32 +#define helper_ssubaddx helper_ssubaddx_riscv32 +#define helper_stb_mmu helper_stb_mmu_riscv32 +#define helper_stl_mmu helper_stl_mmu_riscv32 +#define helper_stq_mmu helper_stq_mmu_riscv32 +#define helper_stw_mmu helper_stw_mmu_riscv32 +#define helper_sub_saturate helper_sub_saturate_riscv32 +#define helper_sub_usaturate helper_sub_usaturate_riscv32 +#define helper_sxtb16 helper_sxtb16_riscv32 +#define helper_uadd16 helper_uadd16_riscv32 +#define helper_uadd8 helper_uadd8_riscv32 +#define helper_uaddsubx helper_uaddsubx_riscv32 +#define helper_udiv helper_udiv_riscv32 +#define helper_uhadd16 helper_uhadd16_riscv32 +#define helper_uhadd8 helper_uhadd8_riscv32 +#define helper_uhaddsubx helper_uhaddsubx_riscv32 +#define helper_uhsub16 helper_uhsub16_riscv32 +#define helper_uhsub8 helper_uhsub8_riscv32 +#define helper_uhsubaddx helper_uhsubaddx_riscv32 +#define helper_uqadd16 helper_uqadd16_riscv32 +#define helper_uqadd8 helper_uqadd8_riscv32 +#define helper_uqaddsubx helper_uqaddsubx_riscv32 +#define helper_uqsub16 helper_uqsub16_riscv32 +#define helper_uqsub8 helper_uqsub8_riscv32 +#define helper_uqsubaddx helper_uqsubaddx_riscv32 +#define helper_usad8 helper_usad8_riscv32 +#define helper_usat helper_usat_riscv32 +#define helper_usat16 helper_usat16_riscv32 +#define helper_usub16 helper_usub16_riscv32 +#define helper_usub8 helper_usub8_riscv32 +#define helper_usubaddx helper_usubaddx_riscv32 +#define helper_uxtb16 helper_uxtb16_riscv32 +#define helper_v7m_blxns helper_v7m_blxns_riscv32 +#define helper_v7m_bxns helper_v7m_bxns_riscv32 +#define helper_v7m_mrs helper_v7m_mrs_riscv32 +#define helper_v7m_msr helper_v7m_msr_riscv32 +#define helper_v7m_tt helper_v7m_tt_riscv32 +#define helper_vfp_absd helper_vfp_absd_riscv32 +#define helper_vfp_abss helper_vfp_abss_riscv32 +#define helper_vfp_addd helper_vfp_addd_riscv32 +#define helper_vfp_adds helper_vfp_adds_riscv32 +#define helper_vfp_cmpd helper_vfp_cmpd_riscv32 +#define helper_vfp_cmph_a64 helper_vfp_cmph_a64_riscv32 +#define helper_vfp_cmped helper_vfp_cmped_riscv32 +#define helper_vfp_cmpeh_a64 helper_vfp_cmpeh_a64_riscv32 +#define helper_vfp_cmpes helper_vfp_cmpes_riscv32 +#define helper_vfp_cmps helper_vfp_cmps_riscv32 +#define helper_vfp_divd helper_vfp_divd_riscv32 +#define helper_vfp_divs helper_vfp_divs_riscv32 +#define helper_vfp_fcvt_f16_to_f32 helper_vfp_fcvt_f16_to_f32_riscv32 +#define helper_vfp_fcvt_f16_to_f64 helper_vfp_fcvt_f16_to_f64_riscv32 +#define helper_vfp_fcvt_f32_to_f16 helper_vfp_fcvt_f32_to_f16_riscv32 +#define helper_vfp_fcvt_f64_to_f16 helper_vfp_fcvt_f64_to_f16_riscv32 +#define helper_vfp_fcvtds helper_vfp_fcvtds_riscv32 +#define helper_vfp_fcvtsd helper_vfp_fcvtsd_riscv32 +#define helper_vfp_get_fpscr helper_vfp_get_fpscr_riscv32 +#define helper_vfp_maxd helper_vfp_maxd_riscv32 +#define helper_vfp_maxnumd helper_vfp_maxnumd_riscv32 +#define helper_vfp_maxnums helper_vfp_maxnums_riscv32 +#define helper_vfp_maxs helper_vfp_maxs_riscv32 +#define helper_vfp_mind helper_vfp_mind_riscv32 +#define helper_vfp_minnumd helper_vfp_minnumd_riscv32 +#define helper_vfp_minnums helper_vfp_minnums_riscv32 +#define helper_vfp_mins helper_vfp_mins_riscv32 +#define helper_vfp_muladdd helper_vfp_muladdd_riscv32 +#define helper_vfp_muladds helper_vfp_muladds_riscv32 +#define helper_vfp_muld helper_vfp_muld_riscv32 +#define helper_vfp_muls helper_vfp_muls_riscv32 +#define helper_vfp_negd helper_vfp_negd_riscv32 +#define helper_vfp_negs helper_vfp_negs_riscv32 +#define helper_vfp_set_fpscr helper_vfp_set_fpscr_riscv32 +#define helper_vfp_shtod helper_vfp_shtod_riscv32 +#define helper_vfp_shtos helper_vfp_shtos_riscv32 +#define helper_vfp_sitod helper_vfp_sitod_riscv32 +#define helper_vfp_sitoh helper_vfp_sitoh_riscv32 +#define helper_vfp_sitos helper_vfp_sitos_riscv32 +#define helper_vfp_sltod helper_vfp_sltod_riscv32 +#define helper_vfp_sltoh helper_vfp_sltoh_riscv32 +#define helper_vfp_sltos helper_vfp_sltos_riscv32 +#define helper_vfp_sqrtd helper_vfp_sqrtd_riscv32 +#define helper_vfp_sqrts helper_vfp_sqrts_riscv32 +#define helper_vfp_sqtod helper_vfp_sqtod_riscv32 +#define helper_vfp_sqtoh helper_vfp_sqtoh_riscv32 +#define helper_vfp_sqtos helper_vfp_sqtos_riscv32 +#define helper_vfp_subd helper_vfp_subd_riscv32 +#define helper_vfp_subs helper_vfp_subs_riscv32 +#define helper_vfp_toshd helper_vfp_toshd_riscv32 +#define helper_vfp_toshd_round_to_zero helper_vfp_toshd_round_to_zero_riscv32 +#define helper_vfp_toshh helper_vfp_toshh_riscv32 +#define helper_vfp_toshs helper_vfp_toshs_riscv32 +#define helper_vfp_toshs_round_to_zero helper_vfp_toshs_round_to_zero_riscv32 +#define helper_vfp_tosid helper_vfp_tosid_riscv32 +#define helper_vfp_tosih helper_vfp_tosih_riscv32 +#define helper_vfp_tosis helper_vfp_tosis_riscv32 +#define helper_vfp_tosizd helper_vfp_tosizd_riscv32 +#define helper_vfp_tosizh helper_vfp_tosizh_riscv32 +#define helper_vfp_tosizs helper_vfp_tosizs_riscv32 +#define helper_vfp_tosld helper_vfp_tosld_riscv32 +#define helper_vfp_tosld_round_to_zero helper_vfp_tosld_round_to_zero_riscv32 +#define helper_vfp_toslh helper_vfp_toslh_riscv32 +#define helper_vfp_tosls helper_vfp_tosls_riscv32 +#define helper_vfp_tosls_round_to_zero helper_vfp_tosls_round_to_zero_riscv32 +#define helper_vfp_tosqd helper_vfp_tosqd_riscv32 +#define helper_vfp_tosqh helper_vfp_tosqh_riscv32 +#define helper_vfp_tosqs helper_vfp_tosqs_riscv32 +#define helper_vfp_touhd helper_vfp_touhd_riscv32 +#define helper_vfp_touhd_round_to_zero helper_vfp_touhd_round_to_zero_riscv32 +#define helper_vfp_touhh helper_vfp_touhh_riscv32 +#define helper_vfp_touhs helper_vfp_touhs_riscv32 +#define helper_vfp_touhs_round_to_zero helper_vfp_touhs_round_to_zero_riscv32 +#define helper_vfp_touid helper_vfp_touid_riscv32 +#define helper_vfp_touih helper_vfp_touih_riscv32 +#define helper_vfp_touis helper_vfp_touis_riscv32 +#define helper_vfp_touizd helper_vfp_touizd_riscv32 +#define helper_vfp_touizh helper_vfp_touizh_riscv32 +#define helper_vfp_touizs helper_vfp_touizs_riscv32 +#define helper_vfp_tould helper_vfp_tould_riscv32 +#define helper_vfp_tould_round_to_zero helper_vfp_tould_round_to_zero_riscv32 +#define helper_vfp_toulh helper_vfp_toulh_riscv32 +#define helper_vfp_touls helper_vfp_touls_riscv32 +#define helper_vfp_touls_round_to_zero helper_vfp_touls_round_to_zero_riscv32 +#define helper_vfp_touqd helper_vfp_touqd_riscv32 +#define helper_vfp_touqh helper_vfp_touqh_riscv32 +#define helper_vfp_touqs helper_vfp_touqs_riscv32 +#define helper_vfp_uhtod helper_vfp_uhtod_riscv32 +#define helper_vfp_uhtos helper_vfp_uhtos_riscv32 +#define helper_vfp_uitod helper_vfp_uitod_riscv32 +#define helper_vfp_uitoh helper_vfp_uitoh_riscv32 +#define helper_vfp_uitos helper_vfp_uitos_riscv32 +#define helper_vfp_ultod helper_vfp_ultod_riscv32 +#define helper_vfp_ultoh helper_vfp_ultoh_riscv32 +#define helper_vfp_ultos helper_vfp_ultos_riscv32 +#define helper_vfp_uqtod helper_vfp_uqtod_riscv32 +#define helper_vfp_uqtoh helper_vfp_uqtoh_riscv32 +#define helper_vfp_uqtos helper_vfp_uqtos_riscv32 +#define helper_wfe helper_wfe_riscv32 +#define helper_wfi helper_wfi_riscv32 +#define helper_yield helper_yield_riscv32 +#define hex2decimal hex2decimal_riscv32 +#define hw_breakpoint_update hw_breakpoint_update_riscv32 +#define hw_breakpoint_update_all hw_breakpoint_update_all_riscv32 +#define hw_watchpoint_update hw_watchpoint_update_riscv32 +#define hw_watchpoint_update_all hw_watchpoint_update_all_riscv32 +#define init_cpreg_list init_cpreg_list_riscv32 +#define init_lists init_lists_riscv32 +#define input_type_enum input_type_enum_riscv32 +#define int128_2_64 int128_2_64_riscv32 +#define int128_add int128_add_riscv32 +#define int128_addto int128_addto_riscv32 +#define int128_and int128_and_riscv32 +#define int128_eq int128_eq_riscv32 +#define int128_ge int128_ge_riscv32 +#define int128_get64 int128_get64_riscv32 +#define int128_gt int128_gt_riscv32 +#define int128_le int128_le_riscv32 +#define int128_lt int128_lt_riscv32 +#define int128_make64 int128_make64_riscv32 +#define int128_max int128_max_riscv32 +#define int128_min int128_min_riscv32 +#define int128_ne int128_ne_riscv32 +#define int128_neg int128_neg_riscv32 +#define int128_nz int128_nz_riscv32 +#define int128_rshift int128_rshift_riscv32 +#define int128_sub int128_sub_riscv32 +#define int128_subfrom int128_subfrom_riscv32 +#define int128_zero int128_zero_riscv32 +#define int16_to_float16 int16_to_float16_riscv32 +#define int16_to_float16_scalbn int16_to_float16_scalbn_riscv32 +#define int16_to_float32 int16_to_float32_riscv32 +#define int16_to_float32_scalbn int16_to_float32_scalbn_riscv32 +#define int16_to_float64 int16_to_float64_riscv32 +#define int16_to_float64_scalbn int16_to_float64_scalbn_riscv32 +#define int32_to_float128 int32_to_float128_riscv32 +#define int32_to_float16 int32_to_float16_riscv32 +#define int32_to_float16_scalbn int32_to_float16_scalbn_riscv32 +#define int32_to_float32 int32_to_float32_riscv32 +#define int32_to_float32_scalbn int32_to_float32_scalbn_riscv32 +#define int32_to_float64 int32_to_float64_riscv32 +#define int32_to_float64_scalbn int32_to_float64_scalbn_riscv32 +#define int32_to_floatx80 int32_to_floatx80_riscv32 +#define int64_to_float128 int64_to_float128_riscv32 +#define int64_to_float16 int64_to_float16_riscv32 +#define int64_to_float16_scalbn int64_to_float16_scalbn_riscv32 +#define int64_to_float32 int64_to_float32_riscv32 +#define int64_to_float32_scalbn int64_to_float32_scalbn_riscv32 +#define int64_to_float64 int64_to_float64_riscv32 +#define int64_to_float64_scalbn int64_to_float64_scalbn_riscv32 +#define int64_to_floatx80 int64_to_floatx80_riscv32 +#define invalidate_and_set_dirty invalidate_and_set_dirty_riscv32 +#define invalidate_page_bitmap invalidate_page_bitmap_riscv32 +#define io_readb io_readb_riscv32 +#define io_readl io_readl_riscv32 +#define io_readq io_readq_riscv32 +#define io_readw io_readw_riscv32 +#define io_writeb io_writeb_riscv32 +#define io_writel io_writel_riscv32 +#define io_writeq io_writeq_riscv32 +#define io_writew io_writew_riscv32 +#define iotlb_to_section iotlb_to_section_riscv32 +#define is_a64 is_a64_riscv32 +#define is_help_option is_help_option_riscv32 +#define is_valid_option_list is_valid_option_list_riscv32 +#define isr_read isr_read_riscv32 +#define iwmmxt_load_creg iwmmxt_load_creg_riscv32 +#define iwmmxt_load_reg iwmmxt_load_reg_riscv32 +#define iwmmxt_store_creg iwmmxt_store_creg_riscv32 +#define iwmmxt_store_reg iwmmxt_store_reg_riscv32 +#define kvm_to_cpreg_id kvm_to_cpreg_id_riscv32 +#define last_ram_offset last_ram_offset_riscv32 +#define ldl_be_p ldl_be_p_riscv32 +#define ldl_be_phys ldl_be_phys_riscv32 +#define ldl_be_phys_cached ldl_be_phys_cached_riscv32 +#define ldl_he_p ldl_he_p_riscv32 +#define ldl_le_p ldl_le_p_riscv32 +#define ldl_le_phys ldl_le_phys_riscv32 +#define ldl_le_phys_cached ldl_le_phys_cached_riscv32 +#define ldl_phys ldl_phys_riscv32 +#define ldl_phys_cached ldl_phys_cached_riscv32 +#define ldl_phys_internal ldl_phys_internal_riscv32 +#define ldq_be_p ldq_be_p_riscv32 +#define ldq_be_phys ldq_be_phys_riscv32 +#define ldq_be_phys_cached ldq_be_phys_cached_riscv32 +#define ldq_he_p ldq_he_p_riscv32 +#define ldq_le_p ldq_le_p_riscv32 +#define ldq_le_phys ldq_le_phys_riscv32 +#define ldq_le_phys_cached ldq_le_phys_cached_riscv32 +#define ldq_phys ldq_phys_riscv32 +#define ldq_phys_cached ldq_phys_cached_riscv32 +#define ldq_phys_internal ldq_phys_internal_riscv32 +#define ldst_name ldst_name_riscv32 +#define ldub_p ldub_p_riscv32 +#define ldub_phys ldub_phys_riscv32 +#define ldub_phys_cached ldub_phys_cached_riscv32 +#define lduw_be_p lduw_be_p_riscv32 +#define lduw_be_phys lduw_be_phys_riscv32 +#define lduw_be_phys_cached lduw_be_phys_cached_riscv32 +#define lduw_he_p lduw_he_p_riscv32 +#define lduw_le_p lduw_le_p_riscv32 +#define lduw_le_phys lduw_le_phys_riscv32 +#define lduw_le_phys_cached lduw_le_phys_cached_riscv32 +#define lduw_phys lduw_phys_riscv32 +#define lduw_phys_cached lduw_phys_cached_riscv32 +#define lduw_phys_internal lduw_phys_internal_riscv32 +#define le128 le128_riscv32 +#define linked_bp_matches linked_bp_matches_riscv32 +#define listener_add_address_space listener_add_address_space_riscv32 +#define load_cpu_offset load_cpu_offset_riscv32 +#define load_reg load_reg_riscv32 +#define load_reg_var load_reg_var_riscv32 +#define log_cpu_state log_cpu_state_riscv32 +#define lpae_cp_reginfo lpae_cp_reginfo_riscv32 +#define lt128 lt128_riscv32 +#define machine_class_init machine_class_init_riscv32 +#define machine_finalize machine_finalize_riscv32 +#define machine_info machine_info_riscv32 +#define machine_initfn machine_initfn_riscv32 +#define machine_register_types machine_register_types_riscv32 +#define machvirt_init machvirt_init_riscv32 +#define machvirt_machine_init machvirt_machine_init_riscv32 +#define maj maj_riscv32 +#define mapping_conflict mapping_conflict_riscv32 +#define mapping_contiguous mapping_contiguous_riscv32 +#define mapping_have_same_region mapping_have_same_region_riscv32 +#define mapping_merge mapping_merge_riscv32 +#define memory_access_size memory_access_size_riscv32 +#define memory_free memory_free_riscv32 +#define memory_init memory_init_riscv32 +#define memory_listener_match memory_listener_match_riscv32 +#define memory_listener_register memory_listener_register_riscv32 +#define memory_listener_unregister memory_listener_unregister_riscv32 +#define memory_map memory_map_riscv32 +#define memory_map_init memory_map_init_riscv32 +#define memory_map_ptr memory_map_ptr_riscv32 +#define memory_mapping_filter memory_mapping_filter_riscv32 +#define memory_mapping_list_add_mapping_sorted memory_mapping_list_add_mapping_sorted_riscv32 +#define memory_mapping_list_add_merge_sorted memory_mapping_list_add_merge_sorted_riscv32 +#define memory_mapping_list_free memory_mapping_list_free_riscv32 +#define memory_mapping_list_init memory_mapping_list_init_riscv32 +#define memory_region_access_valid memory_region_access_valid_riscv32 +#define memory_region_add_subregion memory_region_add_subregion_riscv32 +#define memory_region_add_subregion_common memory_region_add_subregion_common_riscv32 +#define memory_region_add_subregion_overlap memory_region_add_subregion_overlap_riscv32 +#define memory_region_big_endian memory_region_big_endian_riscv32 +#define memory_region_clear_global_locking memory_region_clear_global_locking_riscv32 +#define memory_region_clear_pending memory_region_clear_pending_riscv32 +#define memory_region_del_subregion memory_region_del_subregion_riscv32 +#define memory_region_destructor_alias memory_region_destructor_alias_riscv32 +#define memory_region_destructor_none memory_region_destructor_none_riscv32 +#define memory_region_destructor_ram memory_region_destructor_ram_riscv32 +#define memory_region_destructor_ram_from_ptr memory_region_destructor_ram_from_ptr_riscv32 +#define memory_region_dispatch_read memory_region_dispatch_read_riscv32 +#define memory_region_dispatch_read1 memory_region_dispatch_read1_riscv32 +#define memory_region_dispatch_write memory_region_dispatch_write_riscv32 +#define memory_region_escape_name memory_region_escape_name_riscv32 +#define memory_region_finalize memory_region_finalize_riscv32 +#define memory_region_find memory_region_find_riscv32 +#define memory_region_from_host memory_region_from_host_riscv32 +#define memory_region_get_addr memory_region_get_addr_riscv32 +#define memory_region_get_alignment memory_region_get_alignment_riscv32 +#define memory_region_get_container memory_region_get_container_riscv32 +#define memory_region_get_dirty_log_mask memory_region_get_dirty_log_mask_riscv32 +#define memory_region_get_fd memory_region_get_fd_riscv32 +#define memory_region_get_may_overlap memory_region_get_may_overlap_riscv32 +#define memory_region_get_priority memory_region_get_priority_riscv32 +#define memory_region_get_ram_addr memory_region_get_ram_addr_riscv32 +#define memory_region_get_ram_ptr memory_region_get_ram_ptr_riscv32 +#define memory_region_get_size memory_region_get_size_riscv32 +#define memory_region_info memory_region_info_riscv32 +#define memory_region_init memory_region_init_riscv32 +#define memory_region_init_alias memory_region_init_alias_riscv32 +#define memory_region_init_io memory_region_init_io_riscv32 +#define memory_region_init_ram_device_ptr memory_region_init_ram_device_ptr_riscv32 +#define memory_region_init_ram_nomigrate memory_region_init_ram_nomigrate_riscv32 +#define memory_region_init_ram_ptr memory_region_init_ram_ptr_riscv32 +#define memory_region_init_reservation memory_region_init_reservation_riscv32 +#define memory_region_init_resizeable_ram memory_region_init_resizeable_ram_riscv32 +#define memory_region_init_rom_nomigrate memory_region_init_rom_nomigrate_riscv32 +#define memory_region_initfn memory_region_initfn_riscv32 +#define memory_region_is_logging memory_region_is_logging_riscv32 +#define memory_region_is_mapped memory_region_is_mapped_riscv32 +#define memory_region_is_ram_device memory_region_is_ram_device_riscv32 +#define memory_region_is_unassigned memory_region_is_unassigned_riscv32 +#define memory_region_name memory_region_name_riscv32 +#define memory_region_need_escape memory_region_need_escape_riscv32 +#define memory_region_oldmmio_read_accessor memory_region_oldmmio_read_accessor_riscv32 +#define memory_region_oldmmio_write_accessor memory_region_oldmmio_write_accessor_riscv32 +#define memory_region_present memory_region_present_riscv32 +#define memory_region_read_accessor memory_region_read_accessor_riscv32 +#define memory_region_readd_subregion memory_region_readd_subregion_riscv32 +#define memory_region_ref memory_region_ref_riscv32 +#define memory_region_resolve_container memory_region_resolve_container_riscv32 +#define memory_region_rom_device_set_romd memory_region_rom_device_set_romd_riscv32 +#define memory_region_section_get_iotlb memory_region_section_get_iotlb_riscv32 +#define memory_region_set_address memory_region_set_address_riscv32 +#define memory_region_set_alias_offset memory_region_set_alias_offset_riscv32 +#define memory_region_set_enabled memory_region_set_enabled_riscv32 +#define memory_region_set_readonly memory_region_set_readonly_riscv32 +#define memory_region_set_size memory_region_set_size_riscv32 +#define memory_region_size memory_region_size_riscv32 +#define memory_region_to_address_space memory_region_to_address_space_riscv32 +#define memory_region_transaction_begin memory_region_transaction_begin_riscv32 +#define memory_region_transaction_commit memory_region_transaction_commit_riscv32 +#define memory_region_unref memory_region_unref_riscv32 +#define memory_region_update_container_subregions memory_region_update_container_subregions_riscv32 +#define memory_region_write_accessor memory_region_write_accessor_riscv32 +#define memory_region_wrong_endianness memory_region_wrong_endianness_riscv32 +#define memory_register_types memory_register_types_riscv32 +#define memory_try_enable_merging memory_try_enable_merging_riscv32 +#define memory_unmap memory_unmap_riscv32 +#define module_call_init module_call_init_riscv32 +#define module_load module_load_riscv32 +#define mpidr_cp_reginfo mpidr_cp_reginfo_riscv32 +#define mpidr_read mpidr_read_riscv32 +#define msr_mask msr_mask_riscv32 +#define mul128By64To192 mul128By64To192_riscv32 +#define mul128To256 mul128To256_riscv32 +#define mul64To128 mul64To128_riscv32 +#define muldiv64 muldiv64_riscv32 +#define neon_2rm_is_float_op neon_2rm_is_float_op_riscv32 +#define neon_2rm_sizes neon_2rm_sizes_riscv32 +#define neon_3r_sizes neon_3r_sizes_riscv32 +#define neon_get_scalar neon_get_scalar_riscv32 +#define neon_load_reg neon_load_reg_riscv32 +#define neon_load_reg64 neon_load_reg64_riscv32 +#define neon_load_scratch neon_load_scratch_riscv32 +#define neon_ls_element_type neon_ls_element_type_riscv32 +#define neon_reg_offset neon_reg_offset_riscv32 +#define neon_store_reg neon_store_reg_riscv32 +#define neon_store_reg64 neon_store_reg64_riscv32 +#define neon_store_scratch neon_store_scratch_riscv32 +#define new_ldst_label new_ldst_label_riscv32 +#define next_list next_list_riscv32 +#define normalizeFloat128Subnormal normalizeFloat128Subnormal_riscv32 +#define normalizeFloat16Subnormal normalizeFloat16Subnormal_riscv32 +#define normalizeFloat32Subnormal normalizeFloat32Subnormal_riscv32 +#define normalizeFloat64Subnormal normalizeFloat64Subnormal_riscv32 +#define normalizeFloatx80Subnormal normalizeFloatx80Subnormal_riscv32 +#define normalizeRoundAndPackFloat128 normalizeRoundAndPackFloat128_riscv32 +#define normalizeRoundAndPackFloat32 normalizeRoundAndPackFloat32_riscv32 +#define normalizeRoundAndPackFloat64 normalizeRoundAndPackFloat64_riscv32 +#define normalizeRoundAndPackFloatx80 normalizeRoundAndPackFloatx80_riscv32 +#define not_v6_cp_reginfo not_v6_cp_reginfo_riscv32 +#define not_v7_cp_reginfo not_v7_cp_reginfo_riscv32 +#define not_v8_cp_reginfo not_v8_cp_reginfo_riscv32 +#define object_child_foreach object_child_foreach_riscv32 +#define object_child_foreach_recursive object_child_foreach_recursive_riscv32 +#define object_class_foreach object_class_foreach_riscv32 +#define object_class_foreach_tramp object_class_foreach_tramp_riscv32 +#define object_class_get_list object_class_get_list_riscv32 +#define object_class_get_list_sorted object_class_get_list_sorted_riscv32 +#define object_class_get_list_tramp object_class_get_list_tramp_riscv32 +#define object_class_get_parent object_class_get_parent_riscv32 +#define object_deinit object_deinit_riscv32 +#define object_dynamic_cast object_dynamic_cast_riscv32 +#define object_finalize object_finalize_riscv32 +#define object_finalize_child_property object_finalize_child_property_riscv32 +#define object_get_child_property object_get_child_property_riscv32 +#define object_get_internal_root object_get_internal_root_riscv32 +#define object_get_link_property object_get_link_property_riscv32 +#define object_get_root object_get_root_riscv32 +#define object_init_with_type object_init_with_type_riscv32 +#define object_initialize_with_type object_initialize_with_type_riscv32 +#define object_instance_init object_instance_init_riscv32 +#define object_new_with_type object_new_with_type_riscv32 +#define object_post_init_with_type object_post_init_with_type_riscv32 +#define object_property_add_alias object_property_add_alias_riscv32 +#define object_property_add_link object_property_add_link_riscv32 +#define object_property_add_uint16_ptr object_property_add_uint16_ptr_riscv32 +#define object_property_add_uint32_ptr object_property_add_uint32_ptr_riscv32 +#define object_property_add_uint64_ptr object_property_add_uint64_ptr_riscv32 +#define object_property_add_uint8_ptr object_property_add_uint8_ptr_riscv32 +#define object_property_allow_set_link object_property_allow_set_link_riscv32 +#define object_property_del object_property_del_riscv32 +#define object_property_del_all object_property_del_all_riscv32 +#define object_property_find object_property_find_riscv32 +#define object_property_get object_property_get_riscv32 +#define object_property_get_bool object_property_get_bool_riscv32 +#define object_property_get_int object_property_get_int_riscv32 +#define object_property_get_link object_property_get_link_riscv32 +#define object_property_get_qobject object_property_get_qobject_riscv32 +#define object_property_get_str object_property_get_str_riscv32 +#define object_property_get_type object_property_get_type_riscv32 +#define object_property_is_child object_property_is_child_riscv32 +#define object_property_set object_property_set_riscv32 +#define object_property_set_description object_property_set_description_riscv32 +#define object_property_set_link object_property_set_link_riscv32 +#define object_property_set_qobject object_property_set_qobject_riscv32 +#define object_release_link_property object_release_link_property_riscv32 +#define object_resolve_abs_path object_resolve_abs_path_riscv32 +#define object_resolve_child_property object_resolve_child_property_riscv32 +#define object_resolve_link object_resolve_link_riscv32 +#define object_resolve_link_property object_resolve_link_property_riscv32 +#define object_resolve_partial_path object_resolve_partial_path_riscv32 +#define object_resolve_path object_resolve_path_riscv32 +#define object_resolve_path_component object_resolve_path_component_riscv32 +#define object_resolve_path_type object_resolve_path_type_riscv32 +#define object_set_link_property object_set_link_property_riscv32 +#define object_type_get_instance_size object_type_get_instance_size_riscv32 +#define omap_cachemaint_write omap_cachemaint_write_riscv32 +#define omap_cp_reginfo omap_cp_reginfo_riscv32 +#define omap_threadid_write omap_threadid_write_riscv32 +#define omap_ticonfig_write omap_ticonfig_write_riscv32 +#define omap_wfi_write omap_wfi_write_riscv32 +#define op_bits op_bits_riscv32 +#define op_to_mov op_to_mov_riscv32 +#define op_to_movi op_to_movi_riscv32 +#define open_modeflags open_modeflags_riscv32 +#define output_type_enum output_type_enum_riscv32 +#define packFloat128 packFloat128_riscv32 +#define packFloat16 packFloat16_riscv32 +#define packFloat32 packFloat32_riscv32 +#define packFloat64 packFloat64_riscv32 +#define packFloatx80 packFloatx80_riscv32 +#define page_find page_find_riscv32 +#define page_find_alloc page_find_alloc_riscv32 +#define page_flush_tb page_flush_tb_riscv32 +#define page_flush_tb_1 page_flush_tb_1_riscv32 +#define page_init page_init_riscv32 +#define page_size_init page_size_init_riscv32 +#define par_write par_write_riscv32 +#define parse_array parse_array_riscv32 +#define parse_cpu_model parse_cpu_model_riscv32 +#define parse_error parse_error_riscv32 +#define parse_escape parse_escape_riscv32 +#define parse_keyword parse_keyword_riscv32 +#define parse_literal parse_literal_riscv32 +#define parse_object parse_object_riscv32 +#define parse_option_bool parse_option_bool_riscv32 +#define parse_option_number parse_option_number_riscv32 +#define parse_option_size parse_option_size_riscv32 +#define parse_optional parse_optional_riscv32 +#define parse_pair parse_pair_riscv32 +#define parse_str parse_str_riscv32 +#define parse_type_bool parse_type_bool_riscv32 +#define parse_type_int parse_type_int_riscv32 +#define parse_type_number parse_type_number_riscv32 +#define parse_type_size parse_type_size_riscv32 +#define parse_type_str parse_type_str_riscv32 +#define parse_value parse_value_riscv32 +#define parser_context_free parser_context_free_riscv32 +#define parser_context_new parser_context_new_riscv32 +#define parser_context_peek_token parser_context_peek_token_riscv32 +#define parser_context_pop_token parser_context_pop_token_riscv32 +#define parser_context_restore parser_context_restore_riscv32 +#define parser_context_save parser_context_save_riscv32 +#define patch_reloc patch_reloc_riscv32 +#define phys_map_node_alloc phys_map_node_alloc_riscv32 +#define phys_map_node_reserve phys_map_node_reserve_riscv32 +#define phys_mem_alloc phys_mem_alloc_riscv32 +#define phys_mem_set_alloc phys_mem_set_alloc_riscv32 +#define phys_page_compact phys_page_compact_riscv32 +#define phys_page_compact_all phys_page_compact_all_riscv32 +#define phys_page_find phys_page_find_riscv32 +#define phys_page_set phys_page_set_riscv32 +#define phys_page_set_level phys_page_set_level_riscv32 +#define phys_section_add phys_section_add_riscv32 +#define phys_section_destroy phys_section_destroy_riscv32 +#define phys_sections_free phys_sections_free_riscv32 +#define pickNaN pickNaN_riscv32 +#define pickNaNMulAdd pickNaNMulAdd_riscv32 +#define pmccfiltr_write pmccfiltr_write_riscv32 +#define pmccntr_read pmccntr_read_riscv32 +#define pmccntr_sync pmccntr_sync_riscv32 +#define pmccntr_write pmccntr_write_riscv32 +#define pmccntr_write32 pmccntr_write32_riscv32 +#define pmcntenclr_write pmcntenclr_write_riscv32 +#define pmcntenset_write pmcntenset_write_riscv32 +#define pmcr_write pmcr_write_riscv32 +#define pmintenclr_write pmintenclr_write_riscv32 +#define pmintenset_write pmintenset_write_riscv32 +#define pmovsr_write pmovsr_write_riscv32 +#define pmreg_access pmreg_access_riscv32 +#define pmsav5_cp_reginfo pmsav5_cp_reginfo_riscv32 +#define pmsav5_data_ap_read pmsav5_data_ap_read_riscv32 +#define pmsav5_data_ap_write pmsav5_data_ap_write_riscv32 +#define pmsav5_insn_ap_read pmsav5_insn_ap_read_riscv32 +#define pmsav5_insn_ap_write pmsav5_insn_ap_write_riscv32 +#define pmuserenr_write pmuserenr_write_riscv32 +#define pmxevtyper_write pmxevtyper_write_riscv32 +#define ppc_tb_set_jmp_target ppc_tb_set_jmp_target_riscv32 +#define print_type_bool print_type_bool_riscv32 +#define print_type_int print_type_int_riscv32 +#define print_type_number print_type_number_riscv32 +#define print_type_size print_type_size_riscv32 +#define print_type_str print_type_str_riscv32 +#define probe_write probe_write_riscv32 +#define propagateFloat128NaN propagateFloat128NaN_riscv32 +#define propagateFloat32MulAddNaN propagateFloat32MulAddNaN_riscv32 +#define propagateFloat32NaN propagateFloat32NaN_riscv32 +#define propagateFloat64MulAddNaN propagateFloat64MulAddNaN_riscv32 +#define propagateFloat64NaN propagateFloat64NaN_riscv32 +#define propagateFloatx80NaN propagateFloatx80NaN_riscv32 +#define property_get_alias property_get_alias_riscv32 +#define property_get_bool property_get_bool_riscv32 +#define property_get_str property_get_str_riscv32 +#define property_get_uint16_ptr property_get_uint16_ptr_riscv32 +#define property_get_uint32_ptr property_get_uint32_ptr_riscv32 +#define property_get_uint64_ptr property_get_uint64_ptr_riscv32 +#define property_get_uint8_ptr property_get_uint8_ptr_riscv32 +#define property_release_alias property_release_alias_riscv32 +#define property_release_bool property_release_bool_riscv32 +#define property_release_str property_release_str_riscv32 +#define property_resolve_alias property_resolve_alias_riscv32 +#define property_set_alias property_set_alias_riscv32 +#define property_set_bool property_set_bool_riscv32 +#define property_set_str property_set_str_riscv32 +#define pstate_read pstate_read_riscv32 +#define pstate_write pstate_write_riscv32 +#define pxa250_initfn pxa250_initfn_riscv32 +#define pxa255_initfn pxa255_initfn_riscv32 +#define pxa260_initfn pxa260_initfn_riscv32 +#define pxa261_initfn pxa261_initfn_riscv32 +#define pxa262_initfn pxa262_initfn_riscv32 +#define pxa270a0_initfn pxa270a0_initfn_riscv32 +#define pxa270a1_initfn pxa270a1_initfn_riscv32 +#define pxa270b0_initfn pxa270b0_initfn_riscv32 +#define pxa270b1_initfn pxa270b1_initfn_riscv32 +#define pxa270c0_initfn pxa270c0_initfn_riscv32 +#define pxa270c5_initfn pxa270c5_initfn_riscv32 +#define qapi_dealloc_end_implicit_struct qapi_dealloc_end_implicit_struct_riscv32 +#define qapi_dealloc_end_list qapi_dealloc_end_list_riscv32 +#define qapi_dealloc_end_struct qapi_dealloc_end_struct_riscv32 +#define qapi_dealloc_get_visitor qapi_dealloc_get_visitor_riscv32 +#define qapi_dealloc_next_list qapi_dealloc_next_list_riscv32 +#define qapi_dealloc_pop qapi_dealloc_pop_riscv32 +#define qapi_dealloc_push qapi_dealloc_push_riscv32 +#define qapi_dealloc_start_implicit_struct qapi_dealloc_start_implicit_struct_riscv32 +#define qapi_dealloc_start_list qapi_dealloc_start_list_riscv32 +#define qapi_dealloc_start_struct qapi_dealloc_start_struct_riscv32 +#define qapi_dealloc_start_union qapi_dealloc_start_union_riscv32 +#define qapi_dealloc_type_bool qapi_dealloc_type_bool_riscv32 +#define qapi_dealloc_type_enum qapi_dealloc_type_enum_riscv32 +#define qapi_dealloc_type_int qapi_dealloc_type_int_riscv32 +#define qapi_dealloc_type_number qapi_dealloc_type_number_riscv32 +#define qapi_dealloc_type_size qapi_dealloc_type_size_riscv32 +#define qapi_dealloc_type_str qapi_dealloc_type_str_riscv32 +#define qapi_dealloc_visitor_cleanup qapi_dealloc_visitor_cleanup_riscv32 +#define qapi_dealloc_visitor_new qapi_dealloc_visitor_new_riscv32 +#define qapi_free_ErrorClassList qapi_free_ErrorClassList_riscv32 +#define qapi_free_X86CPUFeatureWordInfo qapi_free_X86CPUFeatureWordInfo_riscv32 +#define qapi_free_X86CPUFeatureWordInfoList qapi_free_X86CPUFeatureWordInfoList_riscv32 +#define qapi_free_X86CPURegister32List qapi_free_X86CPURegister32List_riscv32 +#define qapi_free_boolList qapi_free_boolList_riscv32 +#define qapi_free_int16List qapi_free_int16List_riscv32 +#define qapi_free_int32List qapi_free_int32List_riscv32 +#define qapi_free_int64List qapi_free_int64List_riscv32 +#define qapi_free_int8List qapi_free_int8List_riscv32 +#define qapi_free_intList qapi_free_intList_riscv32 +#define qapi_free_numberList qapi_free_numberList_riscv32 +#define qapi_free_strList qapi_free_strList_riscv32 +#define qapi_free_uint16List qapi_free_uint16List_riscv32 +#define qapi_free_uint32List qapi_free_uint32List_riscv32 +#define qapi_free_uint64List qapi_free_uint64List_riscv32 +#define qapi_free_uint8List qapi_free_uint8List_riscv32 +#define qbool_destroy_obj qbool_destroy_obj_riscv32 +#define qbool_from_int qbool_from_int_riscv32 +#define qbool_get_int qbool_get_int_riscv32 +#define qbool_type qbool_type_riscv32 +#define qbus_create qbus_create_riscv32 +#define qbus_create_inplace qbus_create_inplace_riscv32 +#define qbus_finalize qbus_finalize_riscv32 +#define qbus_initfn qbus_initfn_riscv32 +#define qbus_realize qbus_realize_riscv32 +#define qdev_create qdev_create_riscv32 +#define qdev_get_type qdev_get_type_riscv32 +#define qdev_register_types qdev_register_types_riscv32 +#define qdev_set_parent_bus qdev_set_parent_bus_riscv32 +#define qdev_try_create qdev_try_create_riscv32 +#define qdict_add_key qdict_add_key_riscv32 +#define qdict_array_split qdict_array_split_riscv32 +#define qdict_clone_shallow qdict_clone_shallow_riscv32 +#define qdict_del qdict_del_riscv32 +#define qdict_destroy_obj qdict_destroy_obj_riscv32 +#define qdict_entry_key qdict_entry_key_riscv32 +#define qdict_entry_value qdict_entry_value_riscv32 +#define qdict_extract_subqdict qdict_extract_subqdict_riscv32 +#define qdict_find qdict_find_riscv32 +#define qdict_first qdict_first_riscv32 +#define qdict_flatten qdict_flatten_riscv32 +#define qdict_flatten_qdict qdict_flatten_qdict_riscv32 +#define qdict_flatten_qlist qdict_flatten_qlist_riscv32 +#define qdict_get qdict_get_riscv32 +#define qdict_get_bool qdict_get_bool_riscv32 +#define qdict_get_double qdict_get_double_riscv32 +#define qdict_get_int qdict_get_int_riscv32 +#define qdict_get_obj qdict_get_obj_riscv32 +#define qdict_get_qdict qdict_get_qdict_riscv32 +#define qdict_get_qlist qdict_get_qlist_riscv32 +#define qdict_get_str qdict_get_str_riscv32 +#define qdict_get_try_bool qdict_get_try_bool_riscv32 +#define qdict_get_try_int qdict_get_try_int_riscv32 +#define qdict_get_try_str qdict_get_try_str_riscv32 +#define qdict_has_prefixed_entries qdict_has_prefixed_entries_riscv32 +#define qdict_haskey qdict_haskey_riscv32 +#define qdict_iter qdict_iter_riscv32 +#define qdict_join qdict_join_riscv32 +#define qdict_new qdict_new_riscv32 +#define qdict_next qdict_next_riscv32 +#define qdict_next_entry qdict_next_entry_riscv32 +#define qdict_put_bool qdict_put_bool_riscv32 +#define qdict_put_int qdict_put_int_riscv32 +#define qdict_put_null qdict_put_null_riscv32 +#define qdict_put_obj qdict_put_obj_riscv32 +#define qdict_put_str qdict_put_str_riscv32 +#define qdict_rename_keys qdict_rename_keys_riscv32 +#define qdict_size qdict_size_riscv32 +#define qdict_type qdict_type_riscv32 +#define qemu_clock_get_us qemu_clock_get_us_riscv32 +#define qemu_clock_ptr qemu_clock_ptr_riscv32 +#define qemu_clocks qemu_clocks_riscv32 +#define qemu_get_cpu qemu_get_cpu_riscv32 +#define qemu_get_guest_memory_mapping qemu_get_guest_memory_mapping_riscv32 +#define qemu_get_guest_simple_memory_mapping qemu_get_guest_simple_memory_mapping_riscv32 +#define qemu_get_ram_block qemu_get_ram_block_riscv32 +#define qemu_host_page_mask qemu_host_page_mask_riscv32 +#define qemu_host_page_size qemu_host_page_size_riscv32 +#define qemu_init_vcpu qemu_init_vcpu_riscv32 +#define qemu_ld_helpers qemu_ld_helpers_riscv32 +#define qemu_log_enabled qemu_log_enabled_riscv32 +#define qemu_log_vprintf qemu_log_vprintf_riscv32 +#define qemu_loglevel_mask qemu_loglevel_mask_riscv32 +#define qemu_map_ram_ptr qemu_map_ram_ptr_riscv32 +#define qemu_oom_check qemu_oom_check_riscv32 +#define qemu_parse_fd qemu_parse_fd_riscv32 +#define qemu_ram_addr_from_host qemu_ram_addr_from_host_riscv32 +#define qemu_ram_addr_from_host_nofail qemu_ram_addr_from_host_nofail_riscv32 +#define qemu_ram_alloc qemu_ram_alloc_riscv32 +#define qemu_ram_alloc_from_ptr qemu_ram_alloc_from_ptr_riscv32 +#define qemu_ram_alloc_resizeable qemu_ram_alloc_resizeable_riscv32 +#define qemu_ram_block_by_name qemu_ram_block_by_name_riscv32 +#define qemu_ram_block_from_host qemu_ram_block_from_host_riscv32 +#define qemu_ram_foreach_block qemu_ram_foreach_block_riscv32 +#define qemu_ram_free qemu_ram_free_riscv32 +#define qemu_ram_get_idstr qemu_ram_get_idstr_riscv32 +#define qemu_ram_is_shared qemu_ram_is_shared_riscv32 +#define qemu_ram_ptr_length qemu_ram_ptr_length_riscv32 +#define qemu_ram_remap qemu_ram_remap_riscv32 +#define qemu_ram_resize qemu_ram_resize_riscv32 +#define qemu_ram_setup_dump qemu_ram_setup_dump_riscv32 +#define qemu_ram_unset_idstr qemu_ram_unset_idstr_riscv32 +#define qemu_st_helpers qemu_st_helpers_riscv32 +#define qemu_strnlen qemu_strnlen_riscv32 +#define qemu_strsep qemu_strsep_riscv32 +#define qemu_tcg_configure qemu_tcg_configure_riscv32 +#define qemu_tcg_init_vcpu qemu_tcg_init_vcpu_riscv32 +#define qemu_try_memalign qemu_try_memalign_riscv32 +#define qentry_destroy qentry_destroy_riscv32 +#define qerror_human qerror_human_riscv32 +#define qerror_report qerror_report_riscv32 +#define qerror_report_err qerror_report_err_riscv32 +#define qfloat_destroy_obj qfloat_destroy_obj_riscv32 +#define qfloat_from_double qfloat_from_double_riscv32 +#define qfloat_get_double qfloat_get_double_riscv32 +#define qfloat_type qfloat_type_riscv32 +#define qint_destroy_obj qint_destroy_obj_riscv32 +#define qint_from_int qint_from_int_riscv32 +#define qint_get_int qint_get_int_riscv32 +#define qint_type qint_type_riscv32 +#define qlist_append_bool qlist_append_bool_riscv32 +#define qlist_append_int qlist_append_int_riscv32 +#define qlist_append_null qlist_append_null_riscv32 +#define qlist_append_obj qlist_append_obj_riscv32 +#define qlist_append_str qlist_append_str_riscv32 +#define qlist_copy qlist_copy_riscv32 +#define qlist_copy_elem qlist_copy_elem_riscv32 +#define qlist_destroy_obj qlist_destroy_obj_riscv32 +#define qlist_empty qlist_empty_riscv32 +#define qlist_entry_obj qlist_entry_obj_riscv32 +#define qlist_first qlist_first_riscv32 +#define qlist_iter qlist_iter_riscv32 +#define qlist_new qlist_new_riscv32 +#define qlist_next qlist_next_riscv32 +#define qlist_peek qlist_peek_riscv32 +#define qlist_pop qlist_pop_riscv32 +#define qlist_size qlist_size_riscv32 +#define qlist_size_iter qlist_size_iter_riscv32 +#define qlist_type qlist_type_riscv32 +#define qlit_equal_qobject qlit_equal_qobject_riscv32 +#define qobject_from_qlit qobject_from_qlit_riscv32 +#define qobject_get_try_str qobject_get_try_str_riscv32 +#define qobject_input_end_implicit_struct qobject_input_end_implicit_struct_riscv32 +#define qobject_input_end_list qobject_input_end_list_riscv32 +#define qobject_input_end_struct qobject_input_end_struct_riscv32 +#define qobject_input_get_next_type qobject_input_get_next_type_riscv32 +#define qobject_input_get_object qobject_input_get_object_riscv32 +#define qobject_input_get_visitor qobject_input_get_visitor_riscv32 +#define qobject_input_next_list qobject_input_next_list_riscv32 +#define qobject_input_optional qobject_input_optional_riscv32 +#define qobject_input_pop qobject_input_pop_riscv32 +#define qobject_input_push qobject_input_push_riscv32 +#define qobject_input_start_implicit_struct qobject_input_start_implicit_struct_riscv32 +#define qobject_input_start_list qobject_input_start_list_riscv32 +#define qobject_input_start_struct qobject_input_start_struct_riscv32 +#define qobject_input_type_bool qobject_input_type_bool_riscv32 +#define qobject_input_type_int qobject_input_type_int_riscv32 +#define qobject_input_type_number qobject_input_type_number_riscv32 +#define qobject_input_type_str qobject_input_type_str_riscv32 +#define qobject_input_visitor_cleanup qobject_input_visitor_cleanup_riscv32 +#define qobject_input_visitor_new qobject_input_visitor_new_riscv32 +#define qobject_input_visitor_new_strict qobject_input_visitor_new_strict_riscv32 +#define qobject_output_add_obj qobject_output_add_obj_riscv32 +#define qobject_output_end_list qobject_output_end_list_riscv32 +#define qobject_output_end_struct qobject_output_end_struct_riscv32 +#define qobject_output_first qobject_output_first_riscv32 +#define qobject_output_get_qobject qobject_output_get_qobject_riscv32 +#define qobject_output_get_visitor qobject_output_get_visitor_riscv32 +#define qobject_output_last qobject_output_last_riscv32 +#define qobject_output_next_list qobject_output_next_list_riscv32 +#define qobject_output_pop qobject_output_pop_riscv32 +#define qobject_output_push_obj qobject_output_push_obj_riscv32 +#define qobject_output_start_list qobject_output_start_list_riscv32 +#define qobject_output_start_struct qobject_output_start_struct_riscv32 +#define qobject_output_type_bool qobject_output_type_bool_riscv32 +#define qobject_output_type_int qobject_output_type_int_riscv32 +#define qobject_output_type_number qobject_output_type_number_riscv32 +#define qobject_output_type_str qobject_output_type_str_riscv32 +#define qobject_output_visitor_cleanup qobject_output_visitor_cleanup_riscv32 +#define qobject_output_visitor_new qobject_output_visitor_new_riscv32 +#define qobject_decref qobject_decref_riscv32 +#define qobject_type qobject_type_riscv32 +#define qstring_append qstring_append_riscv32 +#define qstring_append_chr qstring_append_chr_riscv32 +#define qstring_append_int qstring_append_int_riscv32 +#define qstring_destroy_obj qstring_destroy_obj_riscv32 +#define qstring_from_escaped_str qstring_from_escaped_str_riscv32 +#define qstring_from_str qstring_from_str_riscv32 +#define qstring_from_substr qstring_from_substr_riscv32 +#define qstring_get_length qstring_get_length_riscv32 +#define qstring_get_str qstring_get_str_riscv32 +#define qstring_get_try_str qstring_get_try_str_riscv32 +#define qstring_new qstring_new_riscv32 +#define qstring_type qstring_type_riscv32 +#define ram_block_add ram_block_add_riscv32 +#define ram_size ram_size_riscv32 +#define range_compare range_compare_riscv32 +#define range_covers_byte range_covers_byte_riscv32 +#define range_get_last range_get_last_riscv32 +#define range_merge range_merge_riscv32 +#define ranges_can_merge ranges_can_merge_riscv32 +#define raw_read raw_read_riscv32 +#define raw_write raw_write_riscv32 +#define rcon rcon_riscv32 +#define read_raw_cp_reg read_raw_cp_reg_riscv32 +#define recip_estimate recip_estimate_riscv32 +#define recip_sqrt_estimate recip_sqrt_estimate_riscv32 +#define register_cp_regs_for_features register_cp_regs_for_features_riscv32 +#define register_multipage register_multipage_riscv32 +#define register_subpage register_subpage_riscv32 +#define register_tm_clones register_tm_clones_riscv32 +#define register_types_object register_types_object_riscv32 +#define regnames regnames_riscv32 +#define render_memory_region render_memory_region_riscv32 +#define reset_all_temps reset_all_temps_riscv32 +#define reset_temp reset_temp_riscv32 +#define restore_state_to_opc restore_state_to_opc_riscv32 +#define resume_all_vcpus resume_all_vcpus_riscv32 +#define rol32 rol32_riscv32 +#define rol64 rol64_riscv32 +#define ror32 ror32_riscv32 +#define ror64 ror64_riscv32 +#define roundAndPackFloat128 roundAndPackFloat128_riscv32 +#define roundAndPackFloat16 roundAndPackFloat16_riscv32 +#define roundAndPackFloat32 roundAndPackFloat32_riscv32 +#define roundAndPackFloat64 roundAndPackFloat64_riscv32 +#define roundAndPackFloatx80 roundAndPackFloatx80_riscv32 +#define roundAndPackInt32 roundAndPackInt32_riscv32 +#define roundAndPackInt64 roundAndPackInt64_riscv32 +#define roundAndPackUint64 roundAndPackUint64_riscv32 +#define round_to_inf round_to_inf_riscv32 +#define run_on_cpu run_on_cpu_riscv32 +#define s0 s0_riscv32 +#define s1 s1_riscv32 +#define sa1100_initfn sa1100_initfn_riscv32 +#define sa1110_initfn sa1110_initfn_riscv32 +#define save_globals save_globals_riscv32 +#define scr_write scr_write_riscv32 +#define sctlr_write sctlr_write_riscv32 +#define set_bit set_bit_riscv32 +#define set_bits set_bits_riscv32 +#define set_default_nan_mode set_default_nan_mode_riscv32 +#define set_feature set_feature_riscv32 +#define set_float_detect_tininess set_float_detect_tininess_riscv32 +#define set_float_exception_flags set_float_exception_flags_riscv32 +#define set_float_rounding_mode set_float_rounding_mode_riscv32 +#define set_flush_inputs_to_zero set_flush_inputs_to_zero_riscv32 +#define set_flush_to_zero set_flush_to_zero_riscv32 +#define set_preferred_target_page_bits set_preferred_target_page_bits_riscv32 +#define set_swi_errno set_swi_errno_riscv32 +#define sextract32 sextract32_riscv32 +#define sextract64 sextract64_riscv32 +#define shift128ExtraRightJamming shift128ExtraRightJamming_riscv32 +#define shift128Right shift128Right_riscv32 +#define shift128RightJamming shift128RightJamming_riscv32 +#define shift32RightJamming shift32RightJamming_riscv32 +#define shift64ExtraRightJamming shift64ExtraRightJamming_riscv32 +#define shift64RightJamming shift64RightJamming_riscv32 +#define shifter_out_im shifter_out_im_riscv32 +#define shortShift128Left shortShift128Left_riscv32 +#define shortShift192Left shortShift192Left_riscv32 +#define simd_desc simd_desc_riscv32 +#define simple_mpu_ap_bits simple_mpu_ap_bits_riscv32 +#define size_code_gen_buffer size_code_gen_buffer_riscv32 +#define softmmu_lock_user softmmu_lock_user_riscv32 +#define softmmu_lock_user_string softmmu_lock_user_string_riscv32 +#define softmmu_tget32 softmmu_tget32_riscv32 +#define softmmu_tget8 softmmu_tget8_riscv32 +#define softmmu_tput32 softmmu_tput32_riscv32 +#define softmmu_unlock_user softmmu_unlock_user_riscv32 +#define sort_constraints sort_constraints_riscv32 +#define sp_el0_access sp_el0_access_riscv32 +#define spsel_read spsel_read_riscv32 +#define spsel_write spsel_write_riscv32 +#define start_list start_list_riscv32 +#define stb_p stb_p_riscv32 +#define stb_phys stb_phys_riscv32 +#define stb_phys_cached stb_phys_cached_riscv32 +#define stl_be_p stl_be_p_riscv32 +#define stl_be_phys stl_be_phys_riscv32 +#define stl_be_phys_cached stl_be_phys_cached_riscv32 +#define stl_he_p stl_he_p_riscv32 +#define stl_le_p stl_le_p_riscv32 +#define stl_le_phys stl_le_phys_riscv32 +#define stl_le_phys_cached stl_le_phys_cached_riscv32 +#define stl_phys stl_phys_riscv32 +#define stl_phys_cached stl_phys_cached_riscv32 +#define stl_phys_internal stl_phys_internal_riscv32 +#define stl_phys_notdirty stl_phys_notdirty_riscv32 +#define stl_phys_notdirty_cached stl_phys_notdirty_cached_riscv32 +#define store_cpu_offset store_cpu_offset_riscv32 +#define store_reg store_reg_riscv32 +#define store_reg_bx store_reg_bx_riscv32 +#define store_reg_from_load store_reg_from_load_riscv32 +#define stq_be_p stq_be_p_riscv32 +#define stq_be_phys stq_be_phys_riscv32 +#define stq_be_phys_cached stq_be_phys_cached_riscv32 +#define stq_he_p stq_he_p_riscv32 +#define stq_le_p stq_le_p_riscv32 +#define stq_le_phys stq_le_phys_riscv32 +#define stq_le_phys_cached stq_le_phys_cached_riscv32 +#define stq_phys stq_phys_riscv32 +#define stq_phys_cached stq_phys_cached_riscv32 +#define string_input_get_visitor string_input_get_visitor_riscv32 +#define string_input_visitor_cleanup string_input_visitor_cleanup_riscv32 +#define string_input_visitor_new string_input_visitor_new_riscv32 +#define stristart stristart_riscv32 +#define strongarm_cp_reginfo strongarm_cp_reginfo_riscv32 +#define strpadcpy strpadcpy_riscv32 +#define strstart strstart_riscv32 +#define stw_be_p stw_be_p_riscv32 +#define stw_be_phys stw_be_phys_riscv32 +#define stw_be_phys_cached stw_be_phys_cached_riscv32 +#define stw_he_p stw_he_p_riscv32 +#define stw_le_p stw_le_p_riscv32 +#define stw_le_phys stw_le_phys_riscv32 +#define stw_le_phys_cached stw_le_phys_cached_riscv32 +#define stw_phys stw_phys_riscv32 +#define stw_phys_cached stw_phys_cached_riscv32 +#define stw_phys_internal stw_phys_internal_riscv32 +#define sub128 sub128_riscv32 +#define sub16_sat sub16_sat_riscv32 +#define sub16_usat sub16_usat_riscv32 +#define sub192 sub192_riscv32 +#define sub8_sat sub8_sat_riscv32 +#define sub8_usat sub8_usat_riscv32 +#define subFloat128Sigs subFloat128Sigs_riscv32 +#define subFloat32Sigs subFloat32Sigs_riscv32 +#define subFloat64Sigs subFloat64Sigs_riscv32 +#define subFloatx80Sigs subFloatx80Sigs_riscv32 +#define subpage_accepts subpage_accepts_riscv32 +#define subpage_init subpage_init_riscv32 +#define subpage_ops subpage_ops_riscv32 +#define subpage_read subpage_read_riscv32 +#define subpage_register subpage_register_riscv32 +#define subpage_write subpage_write_riscv32 +#define suffix_mul suffix_mul_riscv32 +#define swap_commutative swap_commutative_riscv32 +#define swap_commutative2 swap_commutative2_riscv32 +#define switch_mode switch_mode_riscv32 +#define syn_aa32_bkpt syn_aa32_bkpt_riscv32 +#define syn_aa32_hvc syn_aa32_hvc_riscv32 +#define syn_aa32_smc syn_aa32_smc_riscv32 +#define syn_aa32_svc syn_aa32_svc_riscv32 +#define syn_breakpoint syn_breakpoint_riscv32 +#define syn_cp14_rrt_trap syn_cp14_rrt_trap_riscv32 +#define syn_cp14_rt_trap syn_cp14_rt_trap_riscv32 +#define syn_cp15_rrt_trap syn_cp15_rrt_trap_riscv32 +#define syn_cp15_rt_trap syn_cp15_rt_trap_riscv32 +#define syn_data_abort syn_data_abort_riscv32 +#define syn_fp_access_trap syn_fp_access_trap_riscv32 +#define syn_insn_abort syn_insn_abort_riscv32 +#define syn_swstep syn_swstep_riscv32 +#define syn_uncategorized syn_uncategorized_riscv32 +#define syn_watchpoint syn_watchpoint_riscv32 +#define sync_globals sync_globals_riscv32 +#define syscall_err syscall_err_riscv32 +#define system_bus_class_init system_bus_class_init_riscv32 +#define system_bus_info system_bus_info_riscv32 +#define t2ee_cp_reginfo t2ee_cp_reginfo_riscv32 +#define table_logic_cc table_logic_cc_riscv32 +#define target_el_table target_el_table_riscv32 +#define target_parse_constraint target_parse_constraint_riscv32 +#define target_words_bigendian target_words_bigendian_riscv32 +#define tb_alloc tb_alloc_riscv32 +#define tb_alloc_page tb_alloc_page_riscv32 +#define tb_check_watchpoint tb_check_watchpoint_riscv32 +#define tb_cleanup tb_cleanup_riscv32 +#define tb_find_fast tb_find_fast_riscv32 +#define tb_find_pc tb_find_pc_riscv32 +#define tb_find_slow tb_find_slow_riscv32 +#define tb_flush tb_flush_riscv32 +#define tb_flush_jmp_cache tb_flush_jmp_cache_riscv32 +#define tb_free tb_free_riscv32 +#define tb_gen_code tb_gen_code_riscv32 +#define tb_hash_remove tb_hash_remove_riscv32 +#define tb_htable_lookup tb_htable_lookup_riscv32 +#define tb_invalidate_phys_addr tb_invalidate_phys_addr_riscv32 +#define tb_invalidate_phys_page_fast tb_invalidate_phys_page_fast_riscv32 +#define tb_invalidate_phys_page_range tb_invalidate_phys_page_range_riscv32 +#define tb_invalidate_phys_range tb_invalidate_phys_range_riscv32 +#define tb_jmp_cache_hash_func tb_jmp_cache_hash_func_riscv32 +#define tb_jmp_cache_hash_page tb_jmp_cache_hash_page_riscv32 +#define tb_jmp_remove tb_jmp_remove_riscv32 +#define tb_link_page tb_link_page_riscv32 +#define tb_page_remove tb_page_remove_riscv32 +#define tb_phys_hash_func tb_phys_hash_func_riscv32 +#define tb_phys_invalidate tb_phys_invalidate_riscv32 +#define tb_reset_jump tb_reset_jump_riscv32 +#define tb_set_jmp_target tb_set_jmp_target_riscv32 +#define tcg_accel_class_init tcg_accel_class_init_riscv32 +#define tcg_accel_type tcg_accel_type_riscv32 +#define tcg_add_param_i32 tcg_add_param_i32_riscv32 +#define tcg_add_param_i64 tcg_add_param_i64_riscv32 +#define tcg_add_target_add_op_defs tcg_add_target_add_op_defs_riscv32 +#define tcg_allowed tcg_allowed_riscv32 +#define tcg_can_emit_vec_op tcg_can_emit_vec_op_riscv32 +#define tcg_canonicalize_memop tcg_canonicalize_memop_riscv32 +#define tcg_commit tcg_commit_riscv32 +#define tcg_cond_to_jcc tcg_cond_to_jcc_riscv32 +#define tcg_const_i32 tcg_const_i32_riscv32 +#define tcg_const_i64 tcg_const_i64_riscv32 +#define tcg_const_local_i32 tcg_const_local_i32_riscv32 +#define tcg_const_local_i64 tcg_const_local_i64_riscv32 +#define tcg_const_ones_vec tcg_const_ones_vec_riscv32 +#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_riscv32 +#define tcg_const_zeros_vec tcg_const_zeros_vec_riscv32 +#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_riscv32 +#define tcg_constant_folding tcg_constant_folding_riscv32 +#define tcg_context_init tcg_context_init_riscv32 +#define tcg_cpu_exec tcg_cpu_exec_riscv32 +#define tcg_current_code_size tcg_current_code_size_riscv32 +#define tcg_dump_info tcg_dump_info_riscv32 +#define tcg_dump_ops tcg_dump_ops_riscv32 +#define tcg_emit_op tcg_emit_op_riscv32 +#define tcg_enabled tcg_enabled_riscv32 +#define tcg_exec_all tcg_exec_all_riscv32 +#define tcg_exec_init tcg_exec_init_riscv32 +#define tcg_expand_vec_op tcg_expand_vec_op_riscv32 +#define tcg_find_helper tcg_find_helper_riscv32 +#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_riscv32 +#define tcg_func_start tcg_func_start_riscv32 +#define tcg_gen_abs_i32 tcg_gen_abs_i32_riscv32 +#define tcg_gen_add2_i32 tcg_gen_add2_i32_riscv32 +#define tcg_gen_add2_i64 tcg_gen_add2_i64_riscv32 +#define tcg_gen_add_i32 tcg_gen_add_i32_riscv32 +#define tcg_gen_add_i64 tcg_gen_add_i64_riscv32 +#define tcg_gen_add_vec tcg_gen_add_vec_riscv32 +#define tcg_gen_addi_i32 tcg_gen_addi_i32_riscv32 +#define tcg_gen_addi_i64 tcg_gen_addi_i64_riscv32 +#define tcg_gen_and_i32 tcg_gen_and_i32_riscv32 +#define tcg_gen_and_i64 tcg_gen_and_i64_riscv32 +#define tcg_gen_and_vec tcg_gen_and_vec_riscv32 +#define tcg_gen_andc_i32 tcg_gen_andc_i32_riscv32 +#define tcg_gen_andc_i64 tcg_gen_andc_i64_riscv32 +#define tcg_gen_andc_vec tcg_gen_andc_vec_riscv32 +#define tcg_gen_andi_i32 tcg_gen_andi_i32_riscv32 +#define tcg_gen_andi_i64 tcg_gen_andi_i64_riscv32 +#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_riscv32 +#define tcg_gen_atomic_add_fetch_i64 tcg_gen_atomic_add_fetch_i64_riscv32 +#define tcg_gen_atomic_and_fetch_i32 tcg_gen_atomic_and_fetch_i32_riscv32 +#define tcg_gen_atomic_and_fetch_i64 tcg_gen_atomic_and_fetch_i64_riscv32 +#define tcg_gen_atomic_cmpxchg_i32 tcg_gen_atomic_cmpxchg_i32_riscv32 +#define tcg_gen_atomic_cmpxchg_i64 tcg_gen_atomic_cmpxchg_i64_riscv32 +#define tcg_gen_atomic_fetch_add_i32 tcg_gen_atomic_fetch_add_i32_riscv32 +#define tcg_gen_atomic_fetch_add_i64 tcg_gen_atomic_fetch_add_i64_riscv32 +#define tcg_gen_atomic_fetch_and_i32 tcg_gen_atomic_fetch_and_i32_riscv32 +#define tcg_gen_atomic_fetch_and_i64 tcg_gen_atomic_fetch_and_i64_riscv32 +#define tcg_gen_atomic_fetch_or_i32 tcg_gen_atomic_fetch_or_i32_riscv32 +#define tcg_gen_atomic_fetch_or_i64 tcg_gen_atomic_fetch_or_i64_riscv32 +#define tcg_gen_atomic_fetch_smax_i32 tcg_gen_atomic_fetch_smax_i32_riscv32 +#define tcg_gen_atomic_fetch_smax_i64 tcg_gen_atomic_fetch_smax_i64_riscv32 +#define tcg_gen_atomic_fetch_smin_i32 tcg_gen_atomic_fetch_smin_i32_riscv32 +#define tcg_gen_atomic_fetch_smin_i64 tcg_gen_atomic_fetch_smin_i64_riscv32 +#define tcg_gen_atomic_fetch_umax_i32 tcg_gen_atomic_fetch_umax_i32_riscv32 +#define tcg_gen_atomic_fetch_umax_i64 tcg_gen_atomic_fetch_umax_i64_riscv32 +#define tcg_gen_atomic_fetch_umin_i32 tcg_gen_atomic_fetch_umin_i32_riscv32 +#define tcg_gen_atomic_fetch_umin_i64 tcg_gen_atomic_fetch_umin_i64_riscv32 +#define tcg_gen_atomic_fetch_xor_i32 tcg_gen_atomic_fetch_xor_i32_riscv32 +#define tcg_gen_atomic_fetch_xor_i64 tcg_gen_atomic_fetch_xor_i64_riscv32 +#define tcg_gen_atomic_or_fetch_i32 tcg_gen_atomic_or_fetch_i32_riscv32 +#define tcg_gen_atomic_or_fetch_i64 tcg_gen_atomic_or_fetch_i64_riscv32 +#define tcg_gen_atomic_smax_fetch_i32 tcg_gen_atomic_smax_fetch_i32_riscv32 +#define tcg_gen_atomic_smax_fetch_i64 tcg_gen_atomic_smax_fetch_i64_riscv32 +#define tcg_gen_atomic_smin_fetch_i32 tcg_gen_atomic_smin_fetch_i32_riscv32 +#define tcg_gen_atomic_smin_fetch_i64 tcg_gen_atomic_smin_fetch_i64_riscv32 +#define tcg_gen_atomic_umax_fetch_i32 tcg_gen_atomic_umax_fetch_i32_riscv32 +#define tcg_gen_atomic_umax_fetch_i64 tcg_gen_atomic_umax_fetch_i64_riscv32 +#define tcg_gen_atomic_umin_fetch_i32 tcg_gen_atomic_umin_fetch_i32_riscv32 +#define tcg_gen_atomic_umin_fetch_i64 tcg_gen_atomic_umin_fetch_i64_riscv32 +#define tcg_gen_atomic_xchg_i32 tcg_gen_atomic_xchg_i32_riscv32 +#define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_riscv32 +#define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_riscv32 +#define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_riscv32 +#define tcg_gen_br tcg_gen_br_riscv32 +#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_riscv32 +#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_riscv32 +#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_riscv32 +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_riscv32 +#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_riscv32 +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_riscv32 +#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_riscv32 +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_riscv32 +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_riscv32 +#define tcg_gen_callN tcg_gen_callN_riscv32 +#define tcg_gen_clrsb_i32 tcg_gen_clrsb_i32_riscv32 +#define tcg_gen_clrsb_i64 tcg_gen_clrsb_i64_riscv32 +#define tcg_gen_clz_i32 tcg_gen_clz_i32_riscv32 +#define tcg_gen_clz_i64 tcg_gen_clz_i64_riscv32 +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_riscv32 +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_riscv32 +#define tcg_gen_cmp_vec tcg_gen_cmp_vec_riscv32 +#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_riscv32 +#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_riscv32 +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_riscv32 +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_riscv32 +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_riscv32 +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_riscv32 +#define tcg_gen_code tcg_gen_code_riscv32 +#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_riscv32 +#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_riscv32 +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_riscv32 +#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_riscv32 +#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_riscv32 +#define tcg_gen_discard_i64 tcg_gen_discard_i64_riscv32 +#define tcg_gen_div_i32 tcg_gen_div_i32_riscv32 +#define tcg_gen_div_i64 tcg_gen_div_i64_riscv32 +#define tcg_gen_divu_i32 tcg_gen_divu_i32_riscv32 +#define tcg_gen_divu_i64 tcg_gen_divu_i64_riscv32 +#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_riscv32 +#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_riscv32 +#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_riscv32 +#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_riscv32 +#define tcg_gen_dupi_vec tcg_gen_dupi_vec_riscv32 +#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_riscv32 +#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_riscv32 +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_riscv32 +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_riscv32 +#define tcg_gen_exit_tb tcg_gen_exit_tb_riscv32 +#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_riscv32 +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_riscv32 +#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_riscv32 +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_riscv32 +#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_riscv32 +#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_riscv32 +#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_riscv32 +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_riscv32 +#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_riscv32 +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_riscv32 +#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_riscv32 +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_riscv32 +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_riscv32 +#define tcg_gen_extract_i32 tcg_gen_extract_i32_riscv32 +#define tcg_gen_extract_i64 tcg_gen_extract_i64_riscv32 +#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_riscv32 +#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_riscv32 +#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_riscv32 +#define tcg_gen_goto_tb tcg_gen_goto_tb_riscv32 +#define tcg_gen_gvec_2 tcg_gen_gvec_2_riscv32 +#define tcg_gen_gvec_2i tcg_gen_gvec_2i_riscv32 +#define tcg_gen_gvec_2i_ool tcg_gen_gvec_2i_ool_riscv32 +#define tcg_gen_gvec_2s tcg_gen_gvec_2s_riscv32 +#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_riscv32 +#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_riscv32 +#define tcg_gen_gvec_3 tcg_gen_gvec_3_riscv32 +#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_riscv32 +#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_riscv32 +#define tcg_gen_gvec_4 tcg_gen_gvec_4_riscv32 +#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv32 +#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv32 +#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv32 +#define tcg_gen_gvec_add tcg_gen_gvec_add_riscv32 +#define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv32 +#define tcg_gen_gvec_adds tcg_gen_gvec_adds_riscv32 +#define tcg_gen_gvec_adds8 tcg_gen_gvec_adds8_riscv32 +#define tcg_gen_gvec_adds16 tcg_gen_gvec_adds16_riscv32 +#define tcg_gen_gvec_adds32 tcg_gen_gvec_adds32_riscv32 +#define tcg_gen_gvec_adds64 tcg_gen_gvec_adds64_riscv32 +#define tcg_gen_gvec_and tcg_gen_gvec_and_riscv32 +#define tcg_gen_gvec_andc tcg_gen_gvec_andc_riscv32 +#define tcg_gen_gvec_andi tcg_gen_gvec_andi_riscv32 +#define tcg_gen_gvec_ands tcg_gen_gvec_ands_riscv32 +#define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_riscv32 +#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_riscv32 +#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_riscv32 +#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_riscv32 +#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_riscv32 +#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_riscv32 +#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_riscv32 +#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_riscv32 +#define tcg_gen_gvec_mov tcg_gen_gvec_mov_riscv32 +#define tcg_gen_gvec_mul tcg_gen_gvec_mul_riscv32 +#define tcg_gen_gvec_muli tcg_gen_gvec_muli_riscv32 +#define tcg_gen_gvec_muls tcg_gen_gvec_muls_riscv32 +#define tcg_gen_gvec_muls8 tcg_gen_gvec_muls8_riscv32 +#define tcg_gen_gvec_muls16 tcg_gen_gvec_muls16_riscv32 +#define tcg_gen_gvec_muls32 tcg_gen_gvec_muls32_riscv32 +#define tcg_gen_gvec_muls64 tcg_gen_gvec_muls64_riscv32 +#define tcg_gen_gvec_neg tcg_gen_gvec_neg_riscv32 +#define tcg_gen_gvec_not tcg_gen_gvec_not_riscv32 +#define tcg_gen_gvec_or tcg_gen_gvec_or_riscv32 +#define tcg_gen_gvec_orc tcg_gen_gvec_orc_riscv32 +#define tcg_gen_gvec_ori tcg_gen_gvec_ori_riscv32 +#define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv32 +#define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv32 +#define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv32 +#define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv32 +#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_riscv32 +#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_riscv32 +#define tcg_gen_gvec_sub tcg_gen_gvec_sub_riscv32 +#define tcg_gen_gvec_subs tcg_gen_gvec_subs_riscv32 +#define tcg_gen_gvec_subs8 tcg_gen_gvec_subs8_riscv32 +#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_riscv32 +#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_riscv32 +#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_riscv32 +#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_riscv32 +#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_riscv32 +#define tcg_gen_gvec_xor tcg_gen_gvec_xor_riscv32 +#define tcg_gen_gvec_xori tcg_gen_gvec_xori_riscv32 +#define tcg_gen_gvec_xors tcg_gen_gvec_xors_riscv32 +#define tcg_gen_insn_start tcg_gen_insn_start_riscv32 +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_riscv32 +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_riscv32 +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_riscv32 +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_riscv32 +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_riscv32 +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_riscv32 +#define tcg_gen_ld_i32 tcg_gen_ld_i32_riscv32 +#define tcg_gen_ld_i64 tcg_gen_ld_i64_riscv32 +#define tcg_gen_ld_vec tcg_gen_ld_vec_riscv32 +#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_riscv32 +#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_riscv32 +#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_riscv32 +#define tcg_gen_mb tcg_gen_mb_riscv32 +#define tcg_gen_mov_i32 tcg_gen_mov_i32_riscv32 +#define tcg_gen_mov_i64 tcg_gen_mov_i64_riscv32 +#define tcg_gen_mov_vec tcg_gen_mov_vec_riscv32 +#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_riscv32 +#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_riscv32 +#define tcg_gen_movi_i32 tcg_gen_movi_i32_riscv32 +#define tcg_gen_movi_i64 tcg_gen_movi_i64_riscv32 +#define tcg_gen_mul_i32 tcg_gen_mul_i32_riscv32 +#define tcg_gen_mul_i64 tcg_gen_mul_i64_riscv32 +#define tcg_gen_mul_vec tcg_gen_mul_vec_riscv32 +#define tcg_gen_muli_i32 tcg_gen_muli_i32_riscv32 +#define tcg_gen_muli_i64 tcg_gen_muli_i64_riscv32 +#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_riscv32 +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_riscv32 +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_riscv32 +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_riscv32 +#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_riscv32 +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_riscv32 +#define tcg_gen_nand_i32 tcg_gen_nand_i32_riscv32 +#define tcg_gen_nand_i64 tcg_gen_nand_i64_riscv32 +#define tcg_gen_neg_i32 tcg_gen_neg_i32_riscv32 +#define tcg_gen_neg_i64 tcg_gen_neg_i64_riscv32 +#define tcg_gen_neg_vec tcg_gen_neg_vec_riscv32 +#define tcg_gen_nor_i32 tcg_gen_nor_i32_riscv32 +#define tcg_gen_nor_i64 tcg_gen_nor_i64_riscv32 +#define tcg_gen_nor_vec tcg_gen_nor_vec_riscv32 +#define tcg_gen_not_i32 tcg_gen_not_i32_riscv32 +#define tcg_gen_not_i64 tcg_gen_not_i64_riscv32 +#define tcg_gen_not_vec tcg_gen_not_vec_riscv32 +#define tcg_gen_op1 tcg_gen_op1_riscv32 +#define tcg_gen_op1i tcg_gen_op1i_riscv32 +#define tcg_gen_op2 tcg_gen_op2_riscv32 +#define tcg_gen_op2_i32 tcg_gen_op2_i32_riscv32 +#define tcg_gen_op2_i64 tcg_gen_op2_i64_riscv32 +#define tcg_gen_op2i_i32 tcg_gen_op2i_i32_riscv32 +#define tcg_gen_op2i_i64 tcg_gen_op2i_i64_riscv32 +#define tcg_gen_op3 tcg_gen_op3_riscv32 +#define tcg_gen_op3_i32 tcg_gen_op3_i32_riscv32 +#define tcg_gen_op3_i64 tcg_gen_op3_i64_riscv32 +#define tcg_gen_op4 tcg_gen_op4_riscv32 +#define tcg_gen_op4_i32 tcg_gen_op4_i32_riscv32 +#define tcg_gen_op4i_i32 tcg_gen_op4i_i32_riscv32 +#define tcg_gen_op4ii_i32 tcg_gen_op4ii_i32_riscv32 +#define tcg_gen_op4ii_i64 tcg_gen_op4ii_i64_riscv32 +#define tcg_gen_op5 tcg_gen_op5_riscv32 +#define tcg_gen_op5ii_i32 tcg_gen_op5ii_i32_riscv32 +#define tcg_gen_op6 tcg_gen_op6_riscv32 +#define tcg_gen_op6_i32 tcg_gen_op6_i32_riscv32 +#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_riscv32 +#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_riscv32 +#define tcg_gen_or_i32 tcg_gen_or_i32_riscv32 +#define tcg_gen_or_i64 tcg_gen_or_i64_riscv32 +#define tcg_gen_or_vec tcg_gen_or_vec_riscv32 +#define tcg_gen_orc_i32 tcg_gen_orc_i32_riscv32 +#define tcg_gen_orc_i64 tcg_gen_orc_i64_riscv32 +#define tcg_gen_orc_vec tcg_gen_orc_vec_riscv32 +#define tcg_gen_ori_i32 tcg_gen_ori_i32_riscv32 +#define tcg_gen_ori_i64 tcg_gen_ori_i64_riscv32 +#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_riscv32 +#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_riscv32 +#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_riscv32 +#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_riscv32 +#define tcg_gen_rem_i32 tcg_gen_rem_i32_riscv32 +#define tcg_gen_rem_i64 tcg_gen_rem_i64_riscv32 +#define tcg_gen_remu_i32 tcg_gen_remu_i32_riscv32 +#define tcg_gen_remu_i64 tcg_gen_remu_i64_riscv32 +#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_riscv32 +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_riscv32 +#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_riscv32 +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_riscv32 +#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_riscv32 +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_riscv32 +#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_riscv32 +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_riscv32 +#define tcg_gen_sar_i32 tcg_gen_sar_i32_riscv32 +#define tcg_gen_sar_i64 tcg_gen_sar_i64_riscv32 +#define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv32 +#define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv32 +#define tcg_gen_sari_vec tcg_gen_sari_vec_riscv32 +#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv32 +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv32 +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_riscv32 +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_riscv32 +#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_riscv32 +#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_riscv32 +#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_riscv32 +#define tcg_gen_shl_i32 tcg_gen_shl_i32_riscv32 +#define tcg_gen_shl_i64 tcg_gen_shl_i64_riscv32 +#define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv32 +#define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv32 +#define tcg_gen_shli_vec tcg_gen_shli_vec_riscv32 +#define tcg_gen_shr_i32 tcg_gen_shr_i32_riscv32 +#define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv32 +#define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv32 +#define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv32 +#define tcg_gen_shri_vec tcg_gen_shri_vec_riscv32 +#define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv32 +#define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv32 +#define tcg_gen_smin_i32 tcg_gen_smin_i32_riscv32 +#define tcg_gen_smin_i64 tcg_gen_smin_i64_riscv32 +#define tcg_gen_st_i32 tcg_gen_st_i32_riscv32 +#define tcg_gen_st_i64 tcg_gen_st_i64_riscv32 +#define tcg_gen_st_vec tcg_gen_st_vec_riscv32 +#define tcg_gen_stl_vec tcg_gen_stl_vec_riscv32 +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_riscv32 +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_riscv32 +#define tcg_gen_sub_i32 tcg_gen_sub_i32_riscv32 +#define tcg_gen_sub_i64 tcg_gen_sub_i64_riscv32 +#define tcg_gen_sub_vec tcg_gen_sub_vec_riscv32 +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_riscv32 +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_riscv32 +#define tcg_gen_subi_i32 tcg_gen_subi_i32_riscv32 +#define tcg_gen_subi_i64 tcg_gen_subi_i64_riscv32 +#define tcg_gen_umax_i32 tcg_gen_umax_i32_riscv32 +#define tcg_gen_umax_i64 tcg_gen_umax_i64_riscv32 +#define tcg_gen_umin_i32 tcg_gen_umin_i32_riscv32 +#define tcg_gen_umin_i64 tcg_gen_umin_i64_riscv32 +#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_riscv32 +#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_riscv32 +#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_riscv32 +#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_riscv32 +#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_riscv32 +#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_riscv32 +#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_riscv32 +#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_riscv32 +#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_riscv32 +#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_riscv32 +#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_riscv32 +#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_riscv32 +#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_riscv32 +#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_riscv32 +#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_riscv32 +#define tcg_gen_xor_i32 tcg_gen_xor_i32_riscv32 +#define tcg_gen_xor_i64 tcg_gen_xor_i64_riscv32 +#define tcg_gen_xor_vec tcg_gen_xor_vec_riscv32 +#define tcg_gen_xori_i32 tcg_gen_xori_i32_riscv32 +#define tcg_gen_xori_i64 tcg_gen_xori_i64_riscv32 +#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_riscv32 +#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_riscv32 +#define tcg_get_arg_str_idx tcg_get_arg_str_idx_riscv32 +#define tcg_global_mem_new_i32 tcg_global_mem_new_i32_riscv32 +#define tcg_global_mem_new_i64 tcg_global_mem_new_i64_riscv32 +#define tcg_global_mem_new_internal tcg_global_mem_new_internal_riscv32 +#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_riscv32 +#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_riscv32 +#define tcg_global_reg_new_internal tcg_global_reg_new_internal_riscv32 +#define tcg_handle_interrupt tcg_handle_interrupt_riscv32 +#define tcg_init tcg_init_riscv32 +#define tcg_invert_cond tcg_invert_cond_riscv32 +#define tcg_la_bb_end tcg_la_bb_end_riscv32 +#define tcg_la_br_end tcg_la_br_end_riscv32 +#define tcg_la_func_end tcg_la_func_end_riscv32 +#define tcg_liveness_analysis tcg_liveness_analysis_riscv32 +#define tcg_malloc tcg_malloc_riscv32 +#define tcg_malloc_internal tcg_malloc_internal_riscv32 +#define tcg_op_defs_org tcg_op_defs_org_riscv32 +#define tcg_op_insert_after tcg_op_insert_after_riscv32 +#define tcg_op_insert_before tcg_op_insert_before_riscv32 +#define tcg_op_remove tcg_op_remove_riscv32 +#define tcg_op_supported tcg_op_supported_riscv32 +#define tcg_opt_gen_mov tcg_opt_gen_mov_riscv32 +#define tcg_opt_gen_movi tcg_opt_gen_movi_riscv32 +#define tcg_optimize tcg_optimize_riscv32 +#define tcg_out16 tcg_out16_riscv32 +#define tcg_out32 tcg_out32_riscv32 +#define tcg_out64 tcg_out64_riscv32 +#define tcg_out8 tcg_out8_riscv32 +#define tcg_out_addi tcg_out_addi_riscv32 +#define tcg_out_branch tcg_out_branch_riscv32 +#define tcg_out_brcond32 tcg_out_brcond32_riscv32 +#define tcg_out_brcond64 tcg_out_brcond64_riscv32 +#define tcg_out_bswap32 tcg_out_bswap32_riscv32 +#define tcg_out_bswap64 tcg_out_bswap64_riscv32 +#define tcg_out_call tcg_out_call_riscv32 +#define tcg_out_cmp tcg_out_cmp_riscv32 +#define tcg_out_ext16s tcg_out_ext16s_riscv32 +#define tcg_out_ext16u tcg_out_ext16u_riscv32 +#define tcg_out_ext32s tcg_out_ext32s_riscv32 +#define tcg_out_ext32u tcg_out_ext32u_riscv32 +#define tcg_out_ext8s tcg_out_ext8s_riscv32 +#define tcg_out_ext8u tcg_out_ext8u_riscv32 +#define tcg_out_jmp tcg_out_jmp_riscv32 +#define tcg_out_jxx tcg_out_jxx_riscv32 +#define tcg_out_label tcg_out_label_riscv32 +#define tcg_out_ld tcg_out_ld_riscv32 +#define tcg_out_modrm tcg_out_modrm_riscv32 +#define tcg_out_modrm_offset tcg_out_modrm_offset_riscv32 +#define tcg_out_modrm_sib_offset tcg_out_modrm_sib_offset_riscv32 +#define tcg_out_mov tcg_out_mov_riscv32 +#define tcg_out_movcond32 tcg_out_movcond32_riscv32 +#define tcg_out_movcond64 tcg_out_movcond64_riscv32 +#define tcg_out_movi tcg_out_movi_riscv32 +#define tcg_out_op tcg_out_op_riscv32 +#define tcg_out_pop tcg_out_pop_riscv32 +#define tcg_out_push tcg_out_push_riscv32 +#define tcg_out_qemu_ld tcg_out_qemu_ld_riscv32 +#define tcg_out_qemu_ld_direct tcg_out_qemu_ld_direct_riscv32 +#define tcg_out_qemu_ld_slow_path tcg_out_qemu_ld_slow_path_riscv32 +#define tcg_out_qemu_st tcg_out_qemu_st_riscv32 +#define tcg_out_qemu_st_direct tcg_out_qemu_st_direct_riscv32 +#define tcg_out_qemu_st_slow_path tcg_out_qemu_st_slow_path_riscv32 +#define tcg_out_reloc tcg_out_reloc_riscv32 +#define tcg_out_rolw_8 tcg_out_rolw_8_riscv32 +#define tcg_out_setcond32 tcg_out_setcond32_riscv32 +#define tcg_out_setcond64 tcg_out_setcond64_riscv32 +#define tcg_out_shifti tcg_out_shifti_riscv32 +#define tcg_out_st tcg_out_st_riscv32 +#define tcg_out_tb_finalize tcg_out_tb_finalize_riscv32 +#define tcg_out_tb_init tcg_out_tb_init_riscv32 +#define tcg_out_tlb_load tcg_out_tlb_load_riscv32 +#define tcg_out_vex_modrm tcg_out_vex_modrm_riscv32 +#define tcg_patch32 tcg_patch32_riscv32 +#define tcg_patch8 tcg_patch8_riscv32 +#define tcg_pcrel_diff tcg_pcrel_diff_riscv32 +#define tcg_pool_reset tcg_pool_reset_riscv32 +#define tcg_prologue_init tcg_prologue_init_riscv32 +#define tcg_ptr_byte_diff tcg_ptr_byte_diff_riscv32 +#define tcg_reg_alloc tcg_reg_alloc_riscv32 +#define tcg_reg_alloc_bb_end tcg_reg_alloc_bb_end_riscv32 +#define tcg_reg_alloc_call tcg_reg_alloc_call_riscv32 +#define tcg_reg_alloc_mov tcg_reg_alloc_mov_riscv32 +#define tcg_reg_alloc_movi tcg_reg_alloc_movi_riscv32 +#define tcg_reg_alloc_op tcg_reg_alloc_op_riscv32 +#define tcg_reg_alloc_start tcg_reg_alloc_start_riscv32 +#define tcg_reg_free tcg_reg_free_riscv32 +#define tcg_reg_sync tcg_reg_sync_riscv32 +#define tcg_set_frame tcg_set_frame_riscv32 +#define tcg_set_nop tcg_set_nop_riscv32 +#define tcg_swap_cond tcg_swap_cond_riscv32 +#define tcg_target_call_iarg_regs tcg_target_call_iarg_regs_riscv32 +#define tcg_target_call_oarg_regs tcg_target_call_oarg_regs_riscv32 +#define tcg_target_callee_save_regs tcg_target_callee_save_regs_riscv32 +#define tcg_target_const_match tcg_target_const_match_riscv32 +#define tcg_target_deposit_valid tcg_target_deposit_valid_riscv32 +#define tcg_target_init tcg_target_init_riscv32 +#define tcg_target_qemu_prologue tcg_target_qemu_prologue_riscv32 +#define tcg_target_reg_alloc_order tcg_target_reg_alloc_order_riscv32 +#define tcg_tb_alloc tcg_tb_alloc_riscv32 +#define tcg_temp_alloc tcg_temp_alloc_riscv32 +#define tcg_temp_free_internal tcg_temp_free_internal_riscv32 +#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_riscv32 +#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_riscv32 +#define tcg_temp_new_i32 tcg_temp_new_i32_riscv32 +#define tcg_temp_new_i64 tcg_temp_new_i64_riscv32 +#define tcg_temp_new_internal tcg_temp_new_internal_riscv32 +#define tcg_temp_new_vec tcg_temp_new_vec_riscv32 +#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_riscv32 +#define tdb_hash tdb_hash_riscv32 +#define teecr_write teecr_write_riscv32 +#define teehbr_access teehbr_access_riscv32 +#define temp_allocate_frame temp_allocate_frame_riscv32 +#define temp_dead temp_dead_riscv32 +#define temp_save temp_save_riscv32 +#define temp_sync temp_sync_riscv32 +#define temps_are_copies temps_are_copies_riscv32 +#define tgen_arithi tgen_arithi_riscv32 +#define tgen_arithr tgen_arithr_riscv32 +#define thumb2_logic_op thumb2_logic_op_riscv32 +#define ti925t_initfn ti925t_initfn_riscv32 +#define tlb_add_large_page tlb_add_large_page_riscv32 +#define tlb_fill tlb_fill_riscv32 +#define tlb_flush tlb_flush_riscv32 +#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv32 +#define tlb_flush_entry tlb_flush_entry_riscv32 +#define tlb_flush_page tlb_flush_page_riscv32 +#define tlb_flush_page_by_mmuidx tlb_flush_page_by_mmuidx_riscv32 +#define tlb_is_dirty_ram tlb_is_dirty_ram_riscv32 +#define tlb_reset_dirty tlb_reset_dirty_riscv32 +#define tlb_reset_dirty_range tlb_reset_dirty_range_riscv32 +#define tlb_set_dirty tlb_set_dirty_riscv32 +#define tlb_set_page tlb_set_page_riscv32 +#define tlb_set_page_with_attrs tlb_set_page_with_attrs_riscv32 +#define tlb_vaddr_to_host tlb_vaddr_to_host_riscv32 +#define tlbi_aa64_asid_is_write tlbi_aa64_asid_is_write_riscv32 +#define tlbi_aa64_asid_write tlbi_aa64_asid_write_riscv32 +#define tlbi_aa64_va_is_write tlbi_aa64_va_is_write_riscv32 +#define tlbi_aa64_va_write tlbi_aa64_va_write_riscv32 +#define tlbi_aa64_vaa_is_write tlbi_aa64_vaa_is_write_riscv32 +#define tlbi_aa64_vaa_write tlbi_aa64_vaa_write_riscv32 +#define tlbiall_is_write tlbiall_is_write_riscv32 +#define tlbiall_write tlbiall_write_riscv32 +#define tlbiasid_is_write tlbiasid_is_write_riscv32 +#define tlbiasid_write tlbiasid_write_riscv32 +#define tlbimva_is_write tlbimva_is_write_riscv32 +#define tlbimva_write tlbimva_write_riscv32 +#define tlbimvaa_is_write tlbimvaa_is_write_riscv32 +#define tlbimvaa_write tlbimvaa_write_riscv32 +#define to_qiv to_qiv_riscv32 +#define to_qov to_qov_riscv32 +#define token_get_type token_get_type_riscv32 +#define token_get_value token_get_value_riscv32 +#define token_is_escape token_is_escape_riscv32 +#define token_is_keyword token_is_keyword_riscv32 +#define token_is_operator token_is_operator_riscv32 +#define tokens_append_from_iter tokens_append_from_iter_riscv32 +#define tosa_init tosa_init_riscv32 +#define tosa_machine_init_register_types tosa_machine_init_register_types_riscv32 +#define translator_loop translator_loop_riscv32 +#define translator_loop_temp_check translator_loop_temp_check_riscv32 +#define tswap32 tswap32_riscv32 +#define tswap64 tswap64_riscv32 +#define type_class_get_size type_class_get_size_riscv32 +#define type_get_by_name type_get_by_name_riscv32 +#define type_get_parent type_get_parent_riscv32 +#define type_has_parent type_has_parent_riscv32 +#define type_initialize type_initialize_riscv32 +#define type_initialize_interface type_initialize_interface_riscv32 +#define type_is_ancestor type_is_ancestor_riscv32 +#define type_new type_new_riscv32 +#define type_object_get_size type_object_get_size_riscv32 +#define type_register_internal type_register_internal_riscv32 +#define type_table_add type_table_add_riscv32 +#define type_table_get type_table_get_riscv32 +#define type_table_lookup type_table_lookup_riscv32 +#define uint16_to_float16 uint16_to_float16_riscv32 +#define uint16_to_float16_scalbn uint16_to_float16_scalbn_riscv32 +#define uint16_to_float32 uint16_to_float32_riscv32 +#define uint16_to_float32_scalbn uint16_to_float32_scalbn_riscv32 +#define uint16_to_float64 uint16_to_float64_riscv32 +#define uint16_to_float64_scalbn uint16_to_float64_scalbn_riscv32 +#define uint32_to_float16 uint32_to_float16_riscv32 +#define uint32_to_float16_scalbn uint32_to_float16_scalbn_riscv32 +#define uint32_to_float32 uint32_to_float32_riscv32 +#define uint32_to_float32_scalbn uint32_to_float32_scalbn_riscv32 +#define uint32_to_float64 uint32_to_float64_riscv32 +#define uint32_to_float64_scalbn uint32_to_float64_scalbn_riscv32 +#define uint64_to_float128 uint64_to_float128_riscv32 +#define uint64_to_float16 uint64_to_float16_riscv32 +#define uint64_to_float16_scalbn uint64_to_float16_scalbn_riscv32 +#define uint64_to_float32 uint64_to_float32_riscv32 +#define uint64_to_float32_scalbn uint64_to_float32_scalbn_riscv32 +#define uint64_to_float64 uint64_to_float64_riscv32 +#define uint64_to_float64_scalbn uint64_to_float64_scalbn_riscv32 +#define unassigned_io_ops unassigned_io_ops_riscv32 +#define unassigned_io_read unassigned_io_read_riscv32 +#define unassigned_io_write unassigned_io_write_riscv32 +#define unassigned_mem_accepts unassigned_mem_accepts_riscv32 +#define unassigned_mem_ops unassigned_mem_ops_riscv32 +#define unassigned_mem_read unassigned_mem_read_riscv32 +#define unassigned_mem_write unassigned_mem_write_riscv32 +#define unicorn_free_empty_flat_view unicorn_free_empty_flat_view_riscv32 +#define update_spsel update_spsel_riscv32 +#define use_idiv_instructions_rt use_idiv_instructions_rt_riscv32 +#define v6_cp_reginfo v6_cp_reginfo_riscv32 +#define v6k_cp_reginfo v6k_cp_reginfo_riscv32 +#define v7_cp_reginfo v7_cp_reginfo_riscv32 +#define v7m_pop v7m_pop_riscv32 +#define v7m_push v7m_push_riscv32 +#define v7mp_cp_reginfo v7mp_cp_reginfo_riscv32 +#define v8_cp_reginfo v8_cp_reginfo_riscv32 +#define v8_el2_cp_reginfo v8_el2_cp_reginfo_riscv32 +#define v8_el3_cp_reginfo v8_el3_cp_reginfo_riscv32 +#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_riscv32 +#define vapa_cp_reginfo vapa_cp_reginfo_riscv32 +#define vbar_write vbar_write_riscv32 +#define vec_gen_2 vec_gen_2_riscv32 +#define vec_gen_3 vec_gen_3_riscv32 +#define vec_gen_4 vec_gen_4_riscv32 +#define vfp_exceptbits_from_host vfp_exceptbits_from_host_riscv32 +#define vfp_exceptbits_to_host vfp_exceptbits_to_host_riscv32 +#define vfp_get_fpcr vfp_get_fpcr_riscv32 +#define vfp_get_fpscr vfp_get_fpscr_riscv32 +#define vfp_get_fpsr vfp_get_fpsr_riscv32 +#define vfp_reg_offset vfp_reg_offset_riscv32 +#define vfp_set_fpcr vfp_set_fpcr_riscv32 +#define vfp_set_fpscr vfp_set_fpscr_riscv32 +#define vfp_set_fpsr vfp_set_fpsr_riscv32 +#define visit_end_implicit_struct visit_end_implicit_struct_riscv32 +#define visit_end_list visit_end_list_riscv32 +#define visit_end_struct visit_end_struct_riscv32 +#define visit_end_union visit_end_union_riscv32 +#define visit_get_next_type visit_get_next_type_riscv32 +#define visit_next_list visit_next_list_riscv32 +#define visit_optional visit_optional_riscv32 +#define visit_start_implicit_struct visit_start_implicit_struct_riscv32 +#define visit_start_list visit_start_list_riscv32 +#define visit_start_struct visit_start_struct_riscv32 +#define visit_start_union visit_start_union_riscv32 +#define vm_start vm_start_riscv32 +#define vmsa_cp_reginfo vmsa_cp_reginfo_riscv32 +#define vmsa_tcr_el1_write vmsa_tcr_el1_write_riscv32 +#define vmsa_ttbcr_raw_write vmsa_ttbcr_raw_write_riscv32 +#define vmsa_ttbcr_reset vmsa_ttbcr_reset_riscv32 +#define vmsa_ttbcr_write vmsa_ttbcr_write_riscv32 +#define vmsa_ttbr_write vmsa_ttbr_write_riscv32 +#define write_cpustate_to_list write_cpustate_to_list_riscv32 +#define write_list_to_cpustate write_list_to_cpustate_riscv32 +#define write_raw_cp_reg write_raw_cp_reg_riscv32 +#define write_v7m_exception write_v7m_exception_riscv32 +#define x86_ldl_phys x86_ldl_phys_riscv32 +#define x86_ldq_phys x86_ldq_phys_riscv32 +#define x86_ldub_phys x86_ldub_phys_riscv32 +#define x86_lduw_phys x86_lduw_phys_riscv32 +#define x86_op_defs x86_op_defs_riscv32 +#define x86_stb_phys x86_stb_phys_riscv32 +#define x86_stl_phys x86_stl_phys_riscv32 +#define x86_stl_phys_notdirty x86_stl_phys_notdirty_riscv32 +#define x86_stq_phys x86_stq_phys_riscv32 +#define x86_stw_phys x86_stw_phys_riscv32 +#define xpsr_read xpsr_read_riscv32 +#define xpsr_write xpsr_write_riscv32 +#define xscale_cp_reginfo xscale_cp_reginfo_riscv32 +#define xscale_cpar_write xscale_cpar_write_riscv32 +#define RISCV32_REGS_STORAGE_SIZE RISCV32_REGS_STORAGE_SIZE_riscv32 +#define RISCV64_REGS_STORAGE_SIZE RISCV64_REGS_STORAGE_SIZE_riscv32 +#define cpu_riscv_get_fflags cpu_riscv_get_fflags_riscv32 +#define cpu_riscv_set_fflags cpu_riscv_set_fflags_riscv32 +#define csr_read_helper csr_read_helper_riscv32 +#define csr_write_helper csr_write_helper_riscv32 +#define do_raise_exception_err do_raise_exception_err_riscv32 +#define helper_csrrc helper_csrrc_riscv32 +#define helper_csrrs helper_csrrs_riscv32 +#define helper_csrrw helper_csrrw_riscv32 +#define helper_fadd_d helper_fadd_d_riscv32 +#define helper_fadd_s helper_fadd_s_riscv32 +#define helper_fclass_d helper_fclass_d_riscv32 +#define helper_fclass_s helper_fclass_s_riscv32 +#define helper_fcvt_d_s helper_fcvt_d_s_riscv32 +#define helper_fcvt_d_w helper_fcvt_d_w_riscv32 +#define helper_fcvt_d_wu helper_fcvt_d_wu_riscv32 +#define helper_fcvt_s_d helper_fcvt_s_d_riscv32 +#define helper_fcvt_s_w helper_fcvt_s_w_riscv32 +#define helper_fcvt_s_wu helper_fcvt_s_wu_riscv32 +#define helper_fcvt_w_d helper_fcvt_w_d_riscv32 +#define helper_fcvt_w_s helper_fcvt_w_s_riscv32 +#define helper_fcvt_wu_d helper_fcvt_wu_d_riscv32 +#define helper_fcvt_wu_s helper_fcvt_wu_s_riscv32 +#define helper_fdiv_d helper_fdiv_d_riscv32 +#define helper_fdiv_s helper_fdiv_s_riscv32 +#define helper_feq_d helper_feq_d_riscv32 +#define helper_feq_s helper_feq_s_riscv32 +#define helper_fle_d helper_fle_d_riscv32 +#define helper_fle_s helper_fle_s_riscv32 +#define helper_flt_d helper_flt_d_riscv32 +#define helper_flt_s helper_flt_s_riscv32 +#define helper_fmadd_d helper_fmadd_d_riscv32 +#define helper_fmadd_s helper_fmadd_s_riscv32 +#define helper_fmsub_d helper_fmsub_d_riscv32 +#define helper_fmsub_s helper_fmsub_s_riscv32 +#define helper_fmax_d helper_fmax_d_riscv32 +#define helper_fmax_s helper_fmax_s_riscv32 +#define helper_fmin_d helper_fmin_d_riscv32 +#define helper_fmin_s helper_fmin_s_riscv32 +#define helper_fmul_d helper_fmul_d_riscv32 +#define helper_fmul_s helper_fmul_s_riscv32 +#define helper_fnmadd_d helper_fnmadd_d_riscv32 +#define helper_fnmadd_s helper_fnmadd_s_riscv32 +#define helper_fnmsub_d helper_fnmsub_d_riscv32 +#define helper_fnmsub_s helper_fnmsub_s_riscv32 +#define helper_fsqrt_d helper_fsqrt_d_riscv32 +#define helper_fsqrt_s helper_fsqrt_s_riscv32 +#define helper_fsub_d helper_fsub_d_riscv32 +#define helper_fsub_s helper_fsub_s_riscv32 +#define helper_mret helper_mret_riscv32 +#define helper_riscv_tlb_flush helper_riscv_tlb_flush_riscv32 +#define helper_set_rounding_mode helper_set_rounding_mode_riscv32 +#define helper_sret helper_sret_riscv32 +#define pmp_hart_has_privs pmp_hart_has_privs_riscv32 +#define pmpaddr_csr_read pmpaddr_csr_read_riscv32 +#define pmpaddr_csr_write pmpaddr_csr_write_riscv32 +#define pmpcfg_csr_read pmpcfg_csr_read_riscv32 +#define pmpcfg_csr_write pmpcfg_csr_write_riscv32 +#define riscv_cpu_do_interrupt riscv_cpu_do_interrupt_riscv32 +#define riscv_cpu_do_unaligned_access riscv_cpu_do_unaligned_access_riscv32 +#define riscv_cpu_exec_interrupt riscv_cpu_exec_interrupt_riscv32 +#define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv32 +#define riscv_cpu_handle_mmu_fault riscv_cpu_handle_mmu_fault_riscv32 +#define riscv_cpu_list riscv_cpu_list_riscv32 +#define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv32 +#define riscv_cpu_register_types riscv_cpu_register_types_riscv32 +#define riscv_excp_names riscv_excp_names_riscv32 +#define riscv_fpr_regnames riscv_fpr_regnames_riscv32 +#define riscv_int_regnames riscv_int_regnames_riscv32 +#define riscv_intr_names riscv_intr_names_riscv32 +#define riscv_isa_string riscv_isa_string_riscv32 +#define riscv_set_local_interrupt riscv_set_local_interrupt_riscv32 +#define riscv_set_mode riscv_set_mode_riscv32 +#define riscv_translate_init riscv_translate_init_riscv32 +#define spike_v1_10_0_machine_init_register_types spike_v1_10_0_machine_init_register_types_riscv32 +#endif diff --git a/qemu/riscv64.h b/qemu/riscv64.h new file mode 100644 index 00000000..c3a07b66 --- /dev/null +++ b/qemu/riscv64.h @@ -0,0 +1,3343 @@ +/* Autogen header for Unicorn Engine - DONOT MODIFY */ +#ifndef UNICORN_AUTOGEN_RISCV64_H +#define UNICORN_AUTOGEN_RISCV64_H +#define ErrorClass_lookup ErrorClass_lookup_riscv64 +#define S0 S0_riscv64 +#define S1 S1_riscv64 +#define X86CPURegister32_lookup X86CPURegister32_lookup_riscv64 +#define _DYNAMIC _DYNAMIC_riscv64 +#define _GLOBAL_OFFSET_TABLE_ _GLOBAL_OFFSET_TABLE__riscv64 +#define __jit_debug_descriptor __jit_debug_descriptor_riscv64 +#define __jit_debug_register_code __jit_debug_register_code_riscv64 +#define _edata _edata_riscv64 +#define _end _end_riscv64 +#define _fini _fini_riscv64 +#define _init _init_riscv64 +#define a15_l2ctlr_read a15_l2ctlr_read_riscv64 +#define a64_translate_init a64_translate_init_riscv64 +#define aa32_generate_debug_exceptions aa32_generate_debug_exceptions_riscv64 +#define aa64_cacheop_access aa64_cacheop_access_riscv64 +#define aa64_daif_access aa64_daif_access_riscv64 +#define aa64_daif_write aa64_daif_write_riscv64 +#define aa64_dczid_read aa64_dczid_read_riscv64 +#define aa64_fpcr_read aa64_fpcr_read_riscv64 +#define aa64_fpcr_write aa64_fpcr_write_riscv64 +#define aa64_fpsr_read aa64_fpsr_read_riscv64 +#define aa64_fpsr_write aa64_fpsr_write_riscv64 +#define aa64_generate_debug_exceptions aa64_generate_debug_exceptions_riscv64 +#define aa64_zva_access aa64_zva_access_riscv64 +#define aarch64_banked_spsr_index aarch64_banked_spsr_index_riscv64 +#define aarch64_restore_sp aarch64_restore_sp_riscv64 +#define aarch64_save_sp aarch64_save_sp_riscv64 +#define aarch64_sync_32_to_64 aarch64_sync_32_to_64_riscv64 +#define aarch64_sync_64_to_32 aarch64_sync_64_to_32_riscv64 +#define aarch64_tb_set_jmp_target aarch64_tb_set_jmp_target_riscv64 +#define accel_find accel_find_riscv64 +#define accel_init_machine accel_init_machine_riscv64 +#define accel_type accel_type_riscv64 +#define access_with_adjusted_size access_with_adjusted_size_riscv64 +#define add128 add128_riscv64 +#define add16_sat add16_sat_riscv64 +#define add16_usat add16_usat_riscv64 +#define add192 add192_riscv64 +#define add8_sat add8_sat_riscv64 +#define add8_usat add8_usat_riscv64 +#define addFloat128Sigs addFloat128Sigs_riscv64 +#define addFloat32Sigs addFloat32Sigs_riscv64 +#define addFloat64Sigs addFloat64Sigs_riscv64 +#define addFloatx80Sigs addFloatx80Sigs_riscv64 +#define add_cpreg_to_hashtable add_cpreg_to_hashtable_riscv64 +#define add_cpreg_to_list add_cpreg_to_list_riscv64 +#define add_qemu_ldst_label add_qemu_ldst_label_riscv64 +#define address_space_access_valid address_space_access_valid_riscv64 +#define address_space_cache_destroy address_space_cache_destroy_riscv64 +#define address_space_cache_init address_space_cache_init_riscv64 +#define address_space_cache_invalidate address_space_cache_invalidate_riscv64 +#define address_space_destroy address_space_destroy_riscv64 +#define address_space_dispatch_compact address_space_dispatch_compact_riscv64 +#define address_space_dispatch_free address_space_dispatch_free_riscv64 +#define address_space_dispatch_new address_space_dispatch_new_riscv64 +#define address_space_get_flatview address_space_get_flatview_riscv64 +#define address_space_init address_space_init_riscv64 +#define address_space_init_dispatch address_space_init_dispatch_riscv64 +#define address_space_get_iotlb_entry address_space_get_iotlb_entry_riscv64 +#define address_space_ldl address_space_ldl_riscv64 +#define address_space_ldl_be address_space_ldl_be_riscv64 +#define address_space_ldl_be_cached address_space_ldl_be_cached_riscv64 +#define address_space_ldl_cached address_space_ldl_cached_riscv64 +#define address_space_ldl_le address_space_ldl_le_riscv64 +#define address_space_ldl_le_cached address_space_ldl_le_cached_riscv64 +#define address_space_ldq address_space_ldq_riscv64 +#define address_space_ldq_be address_space_ldq_be_riscv64 +#define address_space_ldq_be_cached address_space_ldq_be_cached_riscv64 +#define address_space_ldq_cached address_space_ldq_cached_riscv64 +#define address_space_ldq_le address_space_ldq_le_riscv64 +#define address_space_ldq_le_cached address_space_ldq_le_cached_riscv64 +#define address_space_ldub address_space_ldub_riscv64 +#define address_space_ldub_cached address_space_ldub_cached_riscv64 +#define address_space_lduw address_space_lduw_riscv64 +#define address_space_lduw_be address_space_lduw_be_riscv64 +#define address_space_lduw_be_cached address_space_lduw_be_cached_riscv64 +#define address_space_lduw_cached address_space_lduw_cached_riscv64 +#define address_space_lduw_le address_space_lduw_le_riscv64 +#define address_space_lduw_le_cached address_space_lduw_le_cached_riscv64 +#define address_space_lookup_region address_space_lookup_region_riscv64 +#define address_space_map address_space_map_riscv64 +#define address_space_rw address_space_rw_riscv64 +#define address_space_stb address_space_stb_riscv64 +#define address_space_stb_cached address_space_stb_cached_riscv64 +#define address_space_stl address_space_stl_riscv64 +#define address_space_stl_be address_space_stl_be_riscv64 +#define address_space_stl_be_cached address_space_stl_be_cached_riscv64 +#define address_space_stl_cached address_space_stl_cached_riscv64 +#define address_space_stl_le address_space_stl_le_riscv64 +#define address_space_stl_le_cached address_space_stl_le_cached_riscv64 +#define address_space_stl_notdirty address_space_stl_notdirty_riscv64 +#define address_space_stl_notdirty_cached address_space_stl_notdirty_cached_riscv64 +#define address_space_stq address_space_stq_riscv64 +#define address_space_stq_be address_space_stq_be_riscv64 +#define address_space_stq_be_cached address_space_stq_be_cached_riscv64 +#define address_space_stq_cached address_space_stq_cached_riscv64 +#define address_space_stq_le address_space_stq_le_riscv64 +#define address_space_stq_le_cached address_space_stq_le_cached_riscv64 +#define address_space_stw address_space_stw_riscv64 +#define address_space_stw_be address_space_stw_be_riscv64 +#define address_space_stw_be_cached address_space_stw_be_cached_riscv64 +#define address_space_stw_cached address_space_stw_cached_riscv64 +#define address_space_stw_le address_space_stw_le_riscv64 +#define address_space_stw_le_cached address_space_stw_le_cached_riscv64 +#define address_space_to_dispatch address_space_to_dispatch_riscv64 +#define address_space_to_flatview address_space_to_flatview_riscv64 +#define address_space_translate_for_iotlb address_space_translate_for_iotlb_riscv64 +#define address_space_translate_internal address_space_translate_internal_riscv64 +#define address_space_unmap address_space_unmap_riscv64 +#define address_space_unregister address_space_unregister_riscv64 +#define address_space_update_topology address_space_update_topology_riscv64 +#define address_space_update_topology_pass address_space_update_topology_pass_riscv64 +#define address_space_write address_space_write_riscv64 +#define addrrange_contains addrrange_contains_riscv64 +#define addrrange_end addrrange_end_riscv64 +#define addrrange_equal addrrange_equal_riscv64 +#define addrrange_intersection addrrange_intersection_riscv64 +#define addrrange_intersects addrrange_intersects_riscv64 +#define addrrange_make addrrange_make_riscv64 +#define adjust_endianness adjust_endianness_riscv64 +#define all_helpers all_helpers_riscv64 +#define alloc_code_gen_buffer alloc_code_gen_buffer_riscv64 +#define alloc_entry alloc_entry_riscv64 +#define always_true always_true_riscv64 +#define arm1026_initfn arm1026_initfn_riscv64 +#define arm1136_initfn arm1136_initfn_riscv64 +#define arm1136_r2_initfn arm1136_r2_initfn_riscv64 +#define arm1176_initfn arm1176_initfn_riscv64 +#define arm11mpcore_initfn arm11mpcore_initfn_riscv64 +#define arm926_initfn arm926_initfn_riscv64 +#define arm946_initfn arm946_initfn_riscv64 +#define arm_adjust_watchpoint_address arm_adjust_watchpoint_address_riscv64 +#define arm_ccnt_enabled arm_ccnt_enabled_riscv64 +#define arm_cp_read_zero arm_cp_read_zero_riscv64 +#define arm_cp_reset_ignore arm_cp_reset_ignore_riscv64 +#define arm_cp_write_ignore arm_cp_write_ignore_riscv64 +#define arm_cpu_do_interrupt arm_cpu_do_interrupt_riscv64 +#define arm_cpu_do_transaction_failed arm_cpu_do_transaction_failed_riscv64 +#define arm_cpu_do_unaligned_access arm_cpu_do_unaligned_access_riscv64 +#define arm_cpu_exec_interrupt arm_cpu_exec_interrupt_riscv64 +#define arm_cpu_finalizefn arm_cpu_finalizefn_riscv64 +#define arm_cpu_get_phys_page_attrs_debug arm_cpu_get_phys_page_attrs_debug_riscv64 +#define arm_cpu_initfn arm_cpu_initfn_riscv64 +#define arm_cpu_list arm_cpu_list_riscv64 +#define arm_cpu_post_init arm_cpu_post_init_riscv64 +#define arm_cpu_realizefn arm_cpu_realizefn_riscv64 +#define arm_cpu_register_gdb_regs_for_features arm_cpu_register_gdb_regs_for_features_riscv64 +#define arm_cpu_register_types arm_cpu_register_types_riscv64 +#define arm_cpu_set_pc arm_cpu_set_pc_riscv64 +#define arm_cpus arm_cpus_riscv64 +#define arm_current_el arm_current_el_riscv64 +#define arm_dc_feature arm_dc_feature_riscv64 +#define arm_debug_check_watchpoint arm_debug_check_watchpoint_riscv64 +#define arm_debug_excp_handler arm_debug_excp_handler_riscv64 +#define arm_debug_target_el arm_debug_target_el_riscv64 +#define arm_el_is_aa64 arm_el_is_aa64_riscv64 +#define arm_env_get_cpu arm_env_get_cpu_riscv64 +#define arm_excp_unmasked arm_excp_unmasked_riscv64 +#define arm_feature arm_feature_riscv64 +#define arm_free_cc arm_free_cc_riscv64 +#define arm_gen_test_cc arm_gen_test_cc_riscv64 +#define arm_generate_debug_exceptions arm_generate_debug_exceptions_riscv64 +#define arm_gt_htimer_cb arm_gt_htimer_cb_riscv64 +#define arm_gt_ptimer_cb arm_gt_ptimer_cb_riscv64 +#define arm_gt_stimer_cb arm_gt_stimer_cb_riscv64 +#define arm_gt_vtimer_cb arm_gt_vtimer_cb_riscv64 +#define arm_handle_psci_call arm_handle_psci_call_riscv64 +#define arm_is_psci_call arm_is_psci_call_riscv64 +#define arm_is_secure arm_is_secure_riscv64 +#define arm_is_secure_below_el3 arm_is_secure_below_el3_riscv64 +#define arm_jump_cc arm_jump_cc_riscv64 +#define arm_ldl_code arm_ldl_code_riscv64 +#define arm_lduw_code arm_lduw_code_riscv64 +#define arm_log_exception arm_log_exception_riscv64 +#define arm_phys_excp_target_el arm_phys_excp_target_el_riscv64 +#define arm_reg_read arm_reg_read_riscv64 +#define arm_reg_reset arm_reg_reset_riscv64 +#define arm_reg_write arm_reg_write_riscv64 +#define arm_release arm_release_riscv64 +#define arm_rmode_to_sf arm_rmode_to_sf_riscv64 +#define arm_s1_regime_using_lpae_format arm_s1_regime_using_lpae_format_riscv64 +#define arm_singlestep_active arm_singlestep_active_riscv64 +#define arm_test_cc arm_test_cc_riscv64 +#define arm_tlb_fill arm_tlb_fill_riscv64 +#define arm_translate_init arm_translate_init_riscv64 +#define arm_v7m_class_init arm_v7m_class_init_riscv64 +#define arm_v7m_cpu_do_interrupt arm_v7m_cpu_do_interrupt_riscv64 +#define ats_access ats_access_riscv64 +#define ats_write ats_write_riscv64 +#define bad_mode_switch bad_mode_switch_riscv64 +#define bank_number bank_number_riscv64 +#define bitmap_zero_extend bitmap_zero_extend_riscv64 +#define bp_wp_matches bp_wp_matches_riscv64 +#define breakpoint_invalidate breakpoint_invalidate_riscv64 +#define build_page_bitmap build_page_bitmap_riscv64 +#define bus_add_child bus_add_child_riscv64 +#define bus_class_init bus_class_init_riscv64 +#define bus_info bus_info_riscv64 +#define bus_unparent bus_unparent_riscv64 +#define cache_block_ops_cp_reginfo cache_block_ops_cp_reginfo_riscv64 +#define cache_dirty_status_cp_reginfo cache_dirty_status_cp_reginfo_riscv64 +#define cache_test_clean_cp_reginfo cache_test_clean_cp_reginfo_riscv64 +#define call_recip_estimate call_recip_estimate_riscv64 +#define can_merge can_merge_riscv64 +#define capacity_increase capacity_increase_riscv64 +#define ccsidr_read ccsidr_read_riscv64 +#define check_ap check_ap_riscv64 +#define check_breakpoints check_breakpoints_riscv64 +#define check_exit_request check_exit_request_riscv64 +#define check_watchpoints check_watchpoints_riscv64 +#define cho cho_riscv64 +#define clear_bit clear_bit_riscv64 +#define clz32 clz32_riscv64 +#define clz64 clz64_riscv64 +#define cmp_flatrange_addr cmp_flatrange_addr_riscv64 +#define commonNaNToFloat128 commonNaNToFloat128_riscv64 +#define commonNaNToFloat16 commonNaNToFloat16_riscv64 +#define commonNaNToFloat32 commonNaNToFloat32_riscv64 +#define commonNaNToFloat64 commonNaNToFloat64_riscv64 +#define commonNaNToFloatx80 commonNaNToFloatx80_riscv64 +#define compute_abs_deadline compute_abs_deadline_riscv64 +#define cond_name cond_name_riscv64 +#define configure_accelerator configure_accelerator_riscv64 +#define container_get container_get_riscv64 +#define container_info container_info_riscv64 +#define container_register_types container_register_types_riscv64 +#define contextidr_write contextidr_write_riscv64 +#define core_log_global_start core_log_global_start_riscv64 +#define core_log_global_stop core_log_global_stop_riscv64 +#define core_memory_listener core_memory_listener_riscv64 +#define cortex_a15_initfn cortex_a15_initfn_riscv64 +#define cortex_a8_initfn cortex_a8_initfn_riscv64 +#define cortex_a9_initfn cortex_a9_initfn_riscv64 +#define cortex_m3_initfn cortex_m3_initfn_riscv64 +#define cortexa15_cp_reginfo cortexa15_cp_reginfo_riscv64 +#define cortexa8_cp_reginfo cortexa8_cp_reginfo_riscv64 +#define cortexa9_cp_reginfo cortexa9_cp_reginfo_riscv64 +#define countLeadingZeros32 countLeadingZeros32_riscv64 +#define countLeadingZeros64 countLeadingZeros64_riscv64 +#define count_cpreg count_cpreg_riscv64 +#define cp_access_ok cp_access_ok_riscv64 +#define cp_reg_reset cp_reg_reset_riscv64 +#define cp_reginfo cp_reginfo_riscv64 +#define cpacr_write cpacr_write_riscv64 +#define cpreg_field_is_64bit cpreg_field_is_64bit_riscv64 +#define cpreg_key_compare cpreg_key_compare_riscv64 +#define cpreg_make_keylist cpreg_make_keylist_riscv64 +#define cpreg_to_kvm_id cpreg_to_kvm_id_riscv64 +#define cpsr_read cpsr_read_riscv64 +#define cpsr_write cpsr_write_riscv64 +#define cptype_valid cptype_valid_riscv64 +#define cpu_abort cpu_abort_riscv64 +#define cpu_address_space_init cpu_address_space_init_riscv64 +#define cpu_breakpoint_insert cpu_breakpoint_insert_riscv64 +#define cpu_breakpoint_remove cpu_breakpoint_remove_riscv64 +#define cpu_breakpoint_remove_all cpu_breakpoint_remove_all_riscv64 +#define cpu_breakpoint_remove_by_ref cpu_breakpoint_remove_by_ref_riscv64 +#define cpu_can_do_io cpu_can_do_io_riscv64 +#define cpu_can_run cpu_can_run_riscv64 +#define cpu_class_init cpu_class_init_riscv64 +#define cpu_common_class_by_name cpu_common_class_by_name_riscv64 +#define cpu_common_exec_interrupt cpu_common_exec_interrupt_riscv64 +#define cpu_common_get_arch_id cpu_common_get_arch_id_riscv64 +#define cpu_common_get_memory_mapping cpu_common_get_memory_mapping_riscv64 +#define cpu_common_get_paging_enabled cpu_common_get_paging_enabled_riscv64 +#define cpu_common_has_work cpu_common_has_work_riscv64 +#define cpu_common_initfn cpu_common_initfn_riscv64 +#define cpu_common_noop cpu_common_noop_riscv64 +#define cpu_common_parse_features cpu_common_parse_features_riscv64 +#define cpu_common_realizefn cpu_common_realizefn_riscv64 +#define cpu_common_reset cpu_common_reset_riscv64 +#define cpu_dump_statistics cpu_dump_statistics_riscv64 +#define cpu_exec cpu_exec_riscv64 +#define cpu_exec_exit cpu_exec_exit_riscv64 +#define cpu_exec_init cpu_exec_init_riscv64 +#define cpu_exec_init_all cpu_exec_init_all_riscv64 +#define cpu_exec_step_atomic cpu_exec_step_atomic_riscv64 +#define cpu_flush_icache_range cpu_flush_icache_range_riscv64 +#define cpu_get_address_space cpu_get_address_space_riscv64 +#define cpu_get_clock cpu_get_clock_riscv64 +#define cpu_get_real_ticks cpu_get_real_ticks_riscv64 +#define cpu_get_tb_cpu_state cpu_get_tb_cpu_state_riscv64 +#define cpu_handle_debug_exception cpu_handle_debug_exception_riscv64 +#define cpu_handle_guest_debug cpu_handle_guest_debug_riscv64 +#define cpu_inb cpu_inb_riscv64 +#define cpu_inl cpu_inl_riscv64 +#define cpu_interrupt cpu_interrupt_riscv64 +#define cpu_interrupt_handler cpu_interrupt_handler_riscv64 +#define cpu_inw cpu_inw_riscv64 +#define cpu_io_recompile cpu_io_recompile_riscv64 +#define cpu_is_stopped cpu_is_stopped_riscv64 +#define cpu_ldl_code cpu_ldl_code_riscv64 +#define cpu_ldub_code cpu_ldub_code_riscv64 +#define cpu_lduw_code cpu_lduw_code_riscv64 +#define cpu_loop_exit cpu_loop_exit_riscv64 +#define cpu_loop_exit_atomic cpu_loop_exit_atomic_riscv64 +#define cpu_loop_exit_noexc cpu_loop_exit_noexc_riscv64 +#define cpu_loop_exit_restore cpu_loop_exit_restore_riscv64 +#define cpu_memory_rw_debug cpu_memory_rw_debug_riscv64 +#define cpu_mmu_index cpu_mmu_index_riscv64 +#define cpu_outb cpu_outb_riscv64 +#define cpu_outl cpu_outl_riscv64 +#define cpu_outw cpu_outw_riscv64 +#define cpu_physical_memory_all_dirty cpu_physical_memory_all_dirty_riscv64 +#define cpu_physical_memory_clear_dirty_range cpu_physical_memory_clear_dirty_range_riscv64 +#define cpu_physical_memory_is_clean cpu_physical_memory_is_clean_riscv64 +#define cpu_physical_memory_is_io cpu_physical_memory_is_io_riscv64 +#define cpu_physical_memory_map cpu_physical_memory_map_riscv64 +#define cpu_physical_memory_range_includes_clean cpu_physical_memory_range_includes_clean_riscv64 +#define cpu_physical_memory_reset_dirty cpu_physical_memory_reset_dirty_riscv64 +#define cpu_physical_memory_rw cpu_physical_memory_rw_riscv64 +#define cpu_physical_memory_unmap cpu_physical_memory_unmap_riscv64 +#define cpu_physical_memory_write_rom cpu_physical_memory_write_rom_riscv64 +#define cpu_physical_memory_write_rom_internal cpu_physical_memory_write_rom_internal_riscv64 +#define cpu_register cpu_register_riscv64 +#define cpu_register_types cpu_register_types_riscv64 +#define cpu_restore_state cpu_restore_state_riscv64 +#define cpu_restore_state_from_tb cpu_restore_state_from_tb_riscv64 +#define cpu_single_step cpu_single_step_riscv64 +#define cpu_tb_exec cpu_tb_exec_riscv64 +#define cpu_to_be64 cpu_to_be64_riscv64 +#define cpu_to_le32 cpu_to_le32_riscv64 +#define cpu_to_le64 cpu_to_le64_riscv64 +#define cpu_type_info cpu_type_info_riscv64 +#define cpu_unassigned_access cpu_unassigned_access_riscv64 +#define cpu_watchpoint_address_matches cpu_watchpoint_address_matches_riscv64 +#define cpu_watchpoint_insert cpu_watchpoint_insert_riscv64 +#define cpu_watchpoint_remove cpu_watchpoint_remove_riscv64 +#define cpu_watchpoint_remove_all cpu_watchpoint_remove_all_riscv64 +#define cpu_watchpoint_remove_by_ref cpu_watchpoint_remove_by_ref_riscv64 +#define crc32c_table crc32c_table_riscv64 +#define create_new_memory_mapping create_new_memory_mapping_riscv64 +#define csselr_write csselr_write_riscv64 +#define cto32 cto32_riscv64 +#define ctr_el0_access ctr_el0_access_riscv64 +#define ctz32 ctz32_riscv64 +#define ctz64 ctz64_riscv64 +#define dacr_write dacr_write_riscv64 +#define dbgbcr_write dbgbcr_write_riscv64 +#define dbgbvr_write dbgbvr_write_riscv64 +#define dbgwcr_write dbgwcr_write_riscv64 +#define dbgwvr_write dbgwvr_write_riscv64 +#define debug_cp_reginfo debug_cp_reginfo_riscv64 +#define debug_frame debug_frame_riscv64 +#define debug_lpae_cp_reginfo debug_lpae_cp_reginfo_riscv64 +#define define_arm_cp_regs define_arm_cp_regs_riscv64 +#define define_arm_cp_regs_with_opaque define_arm_cp_regs_with_opaque_riscv64 +#define define_debug_regs define_debug_regs_riscv64 +#define define_one_arm_cp_reg define_one_arm_cp_reg_riscv64 +#define define_one_arm_cp_reg_with_opaque define_one_arm_cp_reg_with_opaque_riscv64 +#define deposit32 deposit32_riscv64 +#define deposit64 deposit64_riscv64 +#define deregister_tm_clones deregister_tm_clones_riscv64 +#define device_class_base_init device_class_base_init_riscv64 +#define device_class_init device_class_init_riscv64 +#define device_finalize device_finalize_riscv64 +#define device_get_realized device_get_realized_riscv64 +#define device_initfn device_initfn_riscv64 +#define device_post_init device_post_init_riscv64 +#define device_reset device_reset_riscv64 +#define device_set_realized device_set_realized_riscv64 +#define device_type_info device_type_info_riscv64 +#define disas_arm_insn disas_arm_insn_riscv64 +#define disas_coproc_insn disas_coproc_insn_riscv64 +#define disas_dsp_insn disas_dsp_insn_riscv64 +#define disas_iwmmxt_insn disas_iwmmxt_insn_riscv64 +#define disas_neon_data_insn disas_neon_data_insn_riscv64 +#define disas_neon_ls_insn disas_neon_ls_insn_riscv64 +#define disas_thumb2_insn disas_thumb2_insn_riscv64 +#define disas_thumb_insn disas_thumb_insn_riscv64 +#define disas_vfp_insn disas_vfp_insn_riscv64 +#define disas_vfp_v8_insn disas_vfp_v8_insn_riscv64 +#define do_arm_semihosting do_arm_semihosting_riscv64 +#define do_clz16 do_clz16_riscv64 +#define do_clz8 do_clz8_riscv64 +#define do_constant_folding do_constant_folding_riscv64 +#define do_constant_folding_2 do_constant_folding_2_riscv64 +#define do_constant_folding_cond do_constant_folding_cond_riscv64 +#define do_constant_folding_cond2 do_constant_folding_cond2_riscv64 +#define do_constant_folding_cond_32 do_constant_folding_cond_32_riscv64 +#define do_constant_folding_cond_64 do_constant_folding_cond_64_riscv64 +#define do_constant_folding_cond_eq do_constant_folding_cond_eq_riscv64 +#define do_fcvt_f16_to_f32 do_fcvt_f16_to_f32_riscv64 +#define do_fcvt_f32_to_f16 do_fcvt_f32_to_f16_riscv64 +#define do_ssat do_ssat_riscv64 +#define do_usad do_usad_riscv64 +#define do_usat do_usat_riscv64 +#define do_v7m_exception_exit do_v7m_exception_exit_riscv64 +#define dummy_c15_cp_reginfo dummy_c15_cp_reginfo_riscv64 +#define dummy_func dummy_func_riscv64 +#define dummy_section dummy_section_riscv64 +#define dup_const_impl dup_const_impl_riscv64 +#define end_list end_list_riscv64 +#define ensure_writable_pages ensure_writable_pages_riscv64 +#define eq128 eq128_riscv64 +#define error_copy error_copy_riscv64 +#define error_exit error_exit_riscv64 +#define error_get_class error_get_class_riscv64 +#define error_get_pretty error_get_pretty_riscv64 +#define error_setg_file_open_internal error_setg_file_open_internal_riscv64 +#define estimateDiv128To64 estimateDiv128To64_riscv64 +#define estimateSqrt32 estimateSqrt32_riscv64 +#define excnames excnames_riscv64 +#define excp_is_internal excp_is_internal_riscv64 +#define extended_addresses_enabled extended_addresses_enabled_riscv64 +#define extended_mpu_ap_bits extended_mpu_ap_bits_riscv64 +#define extract32 extract32_riscv64 +#define extract64 extract64_riscv64 +#define extractFloat128Exp extractFloat128Exp_riscv64 +#define extractFloat128Frac0 extractFloat128Frac0_riscv64 +#define extractFloat128Frac1 extractFloat128Frac1_riscv64 +#define extractFloat128Sign extractFloat128Sign_riscv64 +#define extractFloat16Exp extractFloat16Exp_riscv64 +#define extractFloat16Frac extractFloat16Frac_riscv64 +#define extractFloat16Sign extractFloat16Sign_riscv64 +#define extractFloat32Exp extractFloat32Exp_riscv64 +#define extractFloat32Frac extractFloat32Frac_riscv64 +#define extractFloat32Sign extractFloat32Sign_riscv64 +#define extractFloat64Exp extractFloat64Exp_riscv64 +#define extractFloat64Frac extractFloat64Frac_riscv64 +#define extractFloat64Sign extractFloat64Sign_riscv64 +#define extractFloatx80Exp extractFloatx80Exp_riscv64 +#define extractFloatx80Frac extractFloatx80Frac_riscv64 +#define extractFloatx80Sign extractFloatx80Sign_riscv64 +#define fcse_write fcse_write_riscv64 +#define find_better_copy find_better_copy_riscv64 +#define find_default_machine find_default_machine_riscv64 +#define find_desc_by_name find_desc_by_name_riscv64 +#define find_first_bit find_first_bit_riscv64 +#define find_paging_enabled_cpu find_paging_enabled_cpu_riscv64 +#define find_ram_block find_ram_block_riscv64 +#define find_ram_offset find_ram_offset_riscv64 +#define find_string find_string_riscv64 +#define find_type find_type_riscv64 +#define flatrange_equal flatrange_equal_riscv64 +#define flatview_add_to_dispatch flatview_add_to_dispatch_riscv64 +#define flatview_destroy flatview_destroy_riscv64 +#define flatview_init flatview_init_riscv64 +#define flatview_insert flatview_insert_riscv64 +#define flatview_lookup flatview_lookup_riscv64 +#define flatview_read flatview_read_riscv64 +#define flatview_read_continue flatview_read_continue_riscv64 +#define flatview_read_full flatview_read_full_riscv64 +#define flatview_ref flatview_ref_riscv64 +#define flatview_simplify flatview_simplify_riscv64 +#define flatview_to_dispatch flatview_to_dispatch_riscv64 +#define flatview_translate flatview_translate_riscv64 +#define flatview_unref flatview_unref_riscv64 +#define float128ToCommonNaN float128ToCommonNaN_riscv64 +#define float128_add float128_add_riscv64 +#define float128_compare float128_compare_riscv64 +#define float128_compare_internal float128_compare_internal_riscv64 +#define float128_compare_quiet float128_compare_quiet_riscv64 +#define float128_default_nan float128_default_nan_riscv64 +#define float128_div float128_div_riscv64 +#define float128_eq float128_eq_riscv64 +#define float128_eq_quiet float128_eq_quiet_riscv64 +#define float128_is_quiet_nan float128_is_quiet_nan_riscv64 +#define float128_is_signaling_nan float128_is_signaling_nan_riscv64 +#define float128_le float128_le_riscv64 +#define float128_le_quiet float128_le_quiet_riscv64 +#define float128_lt float128_lt_riscv64 +#define float128_lt_quiet float128_lt_quiet_riscv64 +#define float128_maybe_silence_nan float128_maybe_silence_nan_riscv64 +#define float128_mul float128_mul_riscv64 +#define float128_rem float128_rem_riscv64 +#define float128_round_to_int float128_round_to_int_riscv64 +#define float128_scalbn float128_scalbn_riscv64 +#define float128_silence_nan float128_silence_nan_riscv64 +#define float128_sqrt float128_sqrt_riscv64 +#define float128_sub float128_sub_riscv64 +#define float128_to_float32 float128_to_float32_riscv64 +#define float128_to_float64 float128_to_float64_riscv64 +#define float128_to_floatx80 float128_to_floatx80_riscv64 +#define float128_to_int32 float128_to_int32_riscv64 +#define float128_to_int32_round_to_zero float128_to_int32_round_to_zero_riscv64 +#define float128_to_int64 float128_to_int64_riscv64 +#define float128_to_int64_round_to_zero float128_to_int64_round_to_zero_riscv64 +#define float128_to_uint32_round_to_zero float128_to_uint32_round_to_zero_riscv64 +#define float128_to_uint64 float128_to_uint64_riscv64 +#define float128_to_uint64_round_to_zero float128_to_uint64_round_to_zero_riscv64 +#define float128_unordered float128_unordered_riscv64 +#define float128_unordered_quiet float128_unordered_quiet_riscv64 +#define float16ToCommonNaN float16ToCommonNaN_riscv64 +#define float16_add float16_add_riscv64 +#define float16_compare float16_compare_riscv64 +#define float16_compare_quiet float16_compare_quiet_riscv64 +#define float16_default_nan float16_default_nan_riscv64 +#define float16_div float16_div_riscv64 +#define float16_is_quiet_nan float16_is_quiet_nan_riscv64 +#define float16_is_signaling_nan float16_is_signaling_nan_riscv64 +#define float16_max float16_max_riscv64 +#define float16_maxnum float16_maxnum_riscv64 +#define float16_maxnummag float16_maxnummag_riscv64 +#define float16_maybe_silence_nan float16_maybe_silence_nan_riscv64 +#define float16_min float16_min_riscv64 +#define float16_minnum float16_minnum_riscv64 +#define float16_minnummag float16_minnummag_riscv64 +#define float16_mul float16_mul_riscv64 +#define float16_muladd float16_muladd_riscv64 +#define float16_round_to_int float16_round_to_int_riscv64 +#define float16_scalbn float16_scalbn_riscv64 +#define float16_silence_nan float16_silence_nan_riscv64 +#define float16_sqrt float16_sqrt_riscv64 +#define float16_squash_input_denormal float16_squash_input_denormal_riscv64 +#define float16_sub float16_sub_riscv64 +#define float16_to_int16 float16_to_int16_riscv64 +#define float16_to_int16_round_to_zero float16_to_int16_round_to_zero_riscv64 +#define float16_to_int16_scalbn float16_to_int16_scalbn_riscv64 +#define float16_to_int32 float16_to_int32_riscv64 +#define float16_to_int32_round_to_zero float16_to_int32_round_to_zero_riscv64 +#define float16_to_int32_scalbn float16_to_int32_scalbn_riscv64 +#define float16_to_int64 float16_to_int64_riscv64 +#define float16_to_int64_round_to_zero float16_to_int64_round_to_zero_riscv64 +#define float16_to_int64_scalbn float16_to_int64_scalbn_riscv64 +#define float16_to_float32 float16_to_float32_riscv64 +#define float16_to_float64 float16_to_float64_riscv64 +#define float16_to_uint16 float16_to_uint16_riscv64 +#define float16_to_uint16_round_to_zero float16_to_uint16_round_to_zero_riscv64 +#define float16_to_uint16_scalbn float16_to_uint16_scalbn_riscv64 +#define float16_to_uint32 float16_to_uint32_riscv64 +#define float16_to_uint32_round_to_zero float16_to_uint32_round_to_zero_riscv64 +#define float16_to_uint32_scalbn float16_to_uint32_scalbn_riscv64 +#define float16_to_uint64 float16_to_uint64_riscv64 +#define float16_to_uint64_round_to_zero float16_to_uint64_round_to_zero_riscv64 +#define float16_to_uint64_scalbn float16_to_uint64_scalbn_riscv64 +#define float32ToCommonNaN float32ToCommonNaN_riscv64 +#define float32_abs float32_abs_riscv64 +#define float32_add float32_add_riscv64 +#define float32_chs float32_chs_riscv64 +#define float32_compare float32_compare_riscv64 +#define float32_compare_internal float32_compare_internal_riscv64 +#define float32_compare_quiet float32_compare_quiet_riscv64 +#define float32_default_nan float32_default_nan_riscv64 +#define float32_div float32_div_riscv64 +#define float32_eq float32_eq_riscv64 +#define float32_eq_quiet float32_eq_quiet_riscv64 +#define float32_exp2 float32_exp2_riscv64 +#define float32_exp2_coefficients float32_exp2_coefficients_riscv64 +#define float32_is_any_nan float32_is_any_nan_riscv64 +#define float32_is_infinity float32_is_infinity_riscv64 +#define float32_is_neg float32_is_neg_riscv64 +#define float32_is_quiet_nan float32_is_quiet_nan_riscv64 +#define float32_is_signaling_nan float32_is_signaling_nan_riscv64 +#define float32_is_zero float32_is_zero_riscv64 +#define float32_is_zero_or_denormal float32_is_zero_or_denormal_riscv64 +#define float32_le float32_le_riscv64 +#define float32_le_quiet float32_le_quiet_riscv64 +#define float32_log2 float32_log2_riscv64 +#define float32_lt float32_lt_riscv64 +#define float32_lt_quiet float32_lt_quiet_riscv64 +#define float32_max float32_max_riscv64 +#define float32_maxnum float32_maxnum_riscv64 +#define float32_maxnummag float32_maxnummag_riscv64 +#define float32_maybe_silence_nan float32_maybe_silence_nan_riscv64 +#define float32_min float32_min_riscv64 +#define float32_minmax float32_minmax_riscv64 +#define float32_minnum float32_minnum_riscv64 +#define float32_minnummag float32_minnummag_riscv64 +#define float32_mul float32_mul_riscv64 +#define float32_muladd float32_muladd_riscv64 +#define float32_rem float32_rem_riscv64 +#define float32_round_to_int float32_round_to_int_riscv64 +#define float32_scalbn float32_scalbn_riscv64 +#define float32_set_sign float32_set_sign_riscv64 +#define float32_silence_nan float32_silence_nan_riscv64 +#define float32_sqrt float32_sqrt_riscv64 +#define float32_squash_input_denormal float32_squash_input_denormal_riscv64 +#define float32_sub float32_sub_riscv64 +#define float32_to_float128 float32_to_float128_riscv64 +#define float32_to_float16 float32_to_float16_riscv64 +#define float32_to_float64 float32_to_float64_riscv64 +#define float32_to_floatx80 float32_to_floatx80_riscv64 +#define float32_to_int16 float32_to_int16_riscv64 +#define float32_to_int16_round_to_zero float32_to_int16_round_to_zero_riscv64 +#define float32_to_int16_scalbn float32_to_int16_scalbn_riscv64 +#define float32_to_int32 float32_to_int32_riscv64 +#define float32_to_int32_round_to_zero float32_to_int32_round_to_zero_riscv64 +#define float32_to_int32_scalbn float32_to_int32_scalbn_riscv64 +#define float32_to_int64 float32_to_int64_riscv64 +#define float32_to_int64_round_to_zero float32_to_int64_round_to_zero_riscv64 +#define float32_to_int64_scalbn float32_to_int64_scalbn_riscv64 +#define float32_to_uint16 float32_to_uint16_riscv64 +#define float32_to_uint16_round_to_zero float32_to_uint16_round_to_zero_riscv64 +#define float32_to_uint16_scalbn float32_to_uint16_scalbn_riscv64 +#define float32_to_uint32 float32_to_uint32_riscv64 +#define float32_to_uint32_round_to_zero float32_to_uint32_round_to_zero_riscv64 +#define float32_to_uint32_scalbn float32_to_uint32_scalbn_riscv64 +#define float32_to_uint64 float32_to_uint64_riscv64 +#define float32_to_uint64_round_to_zero float32_to_uint64_round_to_zero_riscv64 +#define float32_to_uint64_scalbn float32_to_uint64_scalbn_riscv64 +#define float32_unordered float32_unordered_riscv64 +#define float32_unordered_quiet float32_unordered_quiet_riscv64 +#define float64ToCommonNaN float64ToCommonNaN_riscv64 +#define float64_abs float64_abs_riscv64 +#define float64_add float64_add_riscv64 +#define float64_chs float64_chs_riscv64 +#define float64_compare float64_compare_riscv64 +#define float64_compare_internal float64_compare_internal_riscv64 +#define float64_compare_quiet float64_compare_quiet_riscv64 +#define float64_default_nan float64_default_nan_riscv64 +#define float64_div float64_div_riscv64 +#define float64_eq float64_eq_riscv64 +#define float64_eq_quiet float64_eq_quiet_riscv64 +#define float64_is_any_nan float64_is_any_nan_riscv64 +#define float64_is_infinity float64_is_infinity_riscv64 +#define float64_is_neg float64_is_neg_riscv64 +#define float64_is_quiet_nan float64_is_quiet_nan_riscv64 +#define float64_is_signaling_nan float64_is_signaling_nan_riscv64 +#define float64_is_zero float64_is_zero_riscv64 +#define float64_le float64_le_riscv64 +#define float64_le_quiet float64_le_quiet_riscv64 +#define float64_log2 float64_log2_riscv64 +#define float64_lt float64_lt_riscv64 +#define float64_lt_quiet float64_lt_quiet_riscv64 +#define float64_max float64_max_riscv64 +#define float64_maxnum float64_maxnum_riscv64 +#define float64_maxnummag float64_maxnummag_riscv64 +#define float64_maybe_silence_nan float64_maybe_silence_nan_riscv64 +#define float64_min float64_min_riscv64 +#define float64_minmax float64_minmax_riscv64 +#define float64_minnum float64_minnum_riscv64 +#define float64_minnummag float64_minnummag_riscv64 +#define float64_mul float64_mul_riscv64 +#define float64_muladd float64_muladd_riscv64 +#define float64_rem float64_rem_riscv64 +#define float64_round_to_int float64_round_to_int_riscv64 +#define float64_scalbn float64_scalbn_riscv64 +#define float64_set_sign float64_set_sign_riscv64 +#define float64_silence_nan float64_silence_nan_riscv64 +#define float64_sqrt float64_sqrt_riscv64 +#define float64_squash_input_denormal float64_squash_input_denormal_riscv64 +#define float64_sub float64_sub_riscv64 +#define float64_to_float128 float64_to_float128_riscv64 +#define float64_to_float16 float64_to_float16_riscv64 +#define float64_to_float32 float64_to_float32_riscv64 +#define float64_to_floatx80 float64_to_floatx80_riscv64 +#define float64_to_int16 float64_to_int16_riscv64 +#define float64_to_int16_round_to_zero float64_to_int16_round_to_zero_riscv64 +#define float64_to_int16_scalbn float64_to_int16_scalbn_riscv64 +#define float64_to_int32 float64_to_int32_riscv64 +#define float64_to_int32_round_to_zero float64_to_int32_round_to_zero_riscv64 +#define float64_to_int32_scalbn float64_to_int32_scalbn_riscv64 +#define float64_to_int64 float64_to_int64_riscv64 +#define float64_to_int64_round_to_zero float64_to_int64_round_to_zero_riscv64 +#define float64_to_int64_scalbn float64_to_int64_scalbn_riscv64 +#define float64_to_uint16 float64_to_uint16_riscv64 +#define float64_to_uint16_round_to_zero float64_to_uint16_round_to_zero_riscv64 +#define float64_to_uint16_scalbn float64_to_uint16_scalbn_riscv64 +#define float64_to_uint32 float64_to_uint32_riscv64 +#define float64_to_uint32_round_to_zero float64_to_uint32_round_to_zero_riscv64 +#define float64_to_uint32_scalbn float64_to_uint32_scalbn_riscv64 +#define float64_to_uint64 float64_to_uint64_riscv64 +#define float64_to_uint64_round_to_zero float64_to_uint64_round_to_zero_riscv64 +#define float64_to_uint64_scalbn float64_to_uint64_scalbn_riscv64 +#define float64_trunc_to_int float64_trunc_to_int_riscv64 +#define float64_unordered float64_unordered_riscv64 +#define float64_unordered_quiet float64_unordered_quiet_riscv64 +#define float_raise float_raise_riscv64 +#define floatx80ToCommonNaN floatx80ToCommonNaN_riscv64 +#define floatx80_add floatx80_add_riscv64 +#define floatx80_compare floatx80_compare_riscv64 +#define floatx80_compare_internal floatx80_compare_internal_riscv64 +#define floatx80_compare_quiet floatx80_compare_quiet_riscv64 +#define floatx80_default_nan floatx80_default_nan_riscv64 +#define floatx80_div floatx80_div_riscv64 +#define floatx80_eq floatx80_eq_riscv64 +#define floatx80_eq_quiet floatx80_eq_quiet_riscv64 +#define floatx80_infinity floatx80_infinity_riscv64 +#define floatx80_is_quiet_nan floatx80_is_quiet_nan_riscv64 +#define floatx80_is_signaling_nan floatx80_is_signaling_nan_riscv64 +#define floatx80_le floatx80_le_riscv64 +#define floatx80_le_quiet floatx80_le_quiet_riscv64 +#define floatx80_lt floatx80_lt_riscv64 +#define floatx80_lt_quiet floatx80_lt_quiet_riscv64 +#define floatx80_maybe_silence_nan floatx80_maybe_silence_nan_riscv64 +#define floatx80_mul floatx80_mul_riscv64 +#define floatx80_rem floatx80_rem_riscv64 +#define floatx80_round floatx80_round_riscv64 +#define floatx80_round_to_int floatx80_round_to_int_riscv64 +#define floatx80_scalbn floatx80_scalbn_riscv64 +#define floatx80_silence_nan floatx80_silence_nan_riscv64 +#define floatx80_sqrt floatx80_sqrt_riscv64 +#define floatx80_sub floatx80_sub_riscv64 +#define floatx80_to_float128 floatx80_to_float128_riscv64 +#define floatx80_to_float32 floatx80_to_float32_riscv64 +#define floatx80_to_float64 floatx80_to_float64_riscv64 +#define floatx80_to_int32 floatx80_to_int32_riscv64 +#define floatx80_to_int32_round_to_zero floatx80_to_int32_round_to_zero_riscv64 +#define floatx80_to_int64 floatx80_to_int64_riscv64 +#define floatx80_to_int64_round_to_zero floatx80_to_int64_round_to_zero_riscv64 +#define floatx80_unordered floatx80_unordered_riscv64 +#define floatx80_unordered_quiet floatx80_unordered_quiet_riscv64 +#define flush_icache_range flush_icache_range_riscv64 +#define format_string format_string_riscv64 +#define fp_decode_rm fp_decode_rm_riscv64 +#define frame_dummy frame_dummy_riscv64 +#define free_code_gen_buffer free_code_gen_buffer_riscv64 +#define free_range free_range_riscv64 +#define fstat64 fstat64_riscv64 +#define futex_wait futex_wait_riscv64 +#define futex_wake futex_wake_riscv64 +#define g_list_insert_sorted_merged g_list_insert_sorted_merged_riscv64 +#define gen_goto_tb gen_goto_tb_riscv64 +#define gen_helper_access_check_cp_reg gen_helper_access_check_cp_reg_riscv64 +#define gen_helper_check_breakpoints gen_helper_check_breakpoints_riscv64 +#define gen_helper_clear_pstate_ss gen_helper_clear_pstate_ss_riscv64 +#define gen_helper_cpsr_read gen_helper_cpsr_read_riscv64 +#define gen_helper_cpsr_write gen_helper_cpsr_write_riscv64 +#define gen_helper_cpsr_write_eret gen_helper_cpsr_write_eret_riscv64 +#define gen_helper_get_cp_reg gen_helper_get_cp_reg_riscv64 +#define gen_helper_get_cp_reg64 gen_helper_get_cp_reg64_riscv64 +#define gen_helper_get_r13_banked gen_helper_get_r13_banked_riscv64 +#define gen_helper_get_user_reg gen_helper_get_user_reg_riscv64 +#define gen_helper_sel_flags gen_helper_sel_flags_riscv64 +#define gen_helper_set_cp_reg gen_helper_set_cp_reg_riscv64 +#define gen_helper_set_cp_reg64 gen_helper_set_cp_reg64_riscv64 +#define gen_helper_set_neon_rmode gen_helper_set_neon_rmode_riscv64 +#define gen_helper_set_r13_banked gen_helper_set_r13_banked_riscv64 +#define gen_helper_set_rmode gen_helper_set_rmode_riscv64 +#define gen_helper_set_user_reg gen_helper_set_user_reg_riscv64 +#define gen_helper_vfp_get_fpscr gen_helper_vfp_get_fpscr_riscv64 +#define gen_helper_vfp_set_fpscr gen_helper_vfp_set_fpscr_riscv64 +#define gen_intermediate_code gen_intermediate_code_riscv64 +#define gen_lookup_tb gen_lookup_tb_riscv64 +#define gen_new_label gen_new_label_riscv64 +#define gen_set_label gen_set_label_riscv64 +#define gen_step_complete_exception gen_step_complete_exception_riscv64 +#define generate_memory_topology generate_memory_topology_riscv64 +#define generic_timer_cp_reginfo generic_timer_cp_reginfo_riscv64 +#define get_arm_cp_reginfo get_arm_cp_reginfo_riscv64 +#define get_clock get_clock_riscv64 +#define get_clock_realtime get_clock_realtime_riscv64 +#define get_constraint_priority get_constraint_priority_riscv64 +#define get_float_exception_flags get_float_exception_flags_riscv64 +#define get_float_rounding_mode get_float_rounding_mode_riscv64 +#define get_fpstatus_ptr get_fpstatus_ptr_riscv64 +#define get_level1_table_address get_level1_table_address_riscv64 +#define get_mem_index get_mem_index_riscv64 +#define get_next_param_value get_next_param_value_riscv64 +#define get_opt_name get_opt_name_riscv64 +#define get_opt_value get_opt_value_riscv64 +#define get_page_addr_code get_page_addr_code_riscv64 +#define get_param_value get_param_value_riscv64 +#define get_phys_addr get_phys_addr_riscv64 +#define get_phys_addr_lpae get_phys_addr_lpae_riscv64 +#define get_phys_addr_mpu get_phys_addr_mpu_riscv64 +#define get_phys_addr_v5 get_phys_addr_v5_riscv64 +#define get_phys_addr_v6 get_phys_addr_v6_riscv64 +#define get_system_memory get_system_memory_riscv64 +#define gt_cnt_read gt_cnt_read_riscv64 +#define gt_cnt_reset gt_cnt_reset_riscv64 +#define gt_cntfrq_access gt_cntfrq_access_riscv64 +#define gt_counter_access gt_counter_access_riscv64 +#define gt_ctl_write gt_ctl_write_riscv64 +#define gt_cval_write gt_cval_write_riscv64 +#define gt_get_countervalue gt_get_countervalue_riscv64 +#define gt_pct_access gt_pct_access_riscv64 +#define gt_ptimer_access gt_ptimer_access_riscv64 +#define gt_recalc_timer gt_recalc_timer_riscv64 +#define gt_timer_access gt_timer_access_riscv64 +#define gt_tval_read gt_tval_read_riscv64 +#define gt_tval_write gt_tval_write_riscv64 +#define gt_vct_access gt_vct_access_riscv64 +#define gt_vtimer_access gt_vtimer_access_riscv64 +#define guest_phys_blocks_free guest_phys_blocks_free_riscv64 +#define guest_phys_blocks_init guest_phys_blocks_init_riscv64 +#define handle_vcvt handle_vcvt_riscv64 +#define handle_vminmaxnm handle_vminmaxnm_riscv64 +#define handle_vrint handle_vrint_riscv64 +#define handle_vsel handle_vsel_riscv64 +#define has_help_option has_help_option_riscv64 +#define have_avx1 have_avx1_riscv64 +#define have_avx2 have_avx2_riscv64 +#define have_bmi1 have_bmi1_riscv64 +#define have_bmi2 have_bmi2_riscv64 +#define have_popcnt have_popcnt_riscv64 +#define hcr_write hcr_write_riscv64 +#define helper_access_check_cp_reg helper_access_check_cp_reg_riscv64 +#define helper_add_saturate helper_add_saturate_riscv64 +#define helper_add_setq helper_add_setq_riscv64 +#define helper_add_usaturate helper_add_usaturate_riscv64 +#define helper_atomic_add_fetchb helper_atomic_add_fetchb_riscv64 +#define helper_atomic_add_fetchb_mmu helper_atomic_add_fetchb_mmu_riscv64 +#define helper_atomic_add_fetchl_be helper_atomic_add_fetchl_be_riscv64 +#define helper_atomic_add_fetchl_be_mmu helper_atomic_add_fetchl_be_mmu_riscv64 +#define helper_atomic_add_fetchl_le helper_atomic_add_fetchl_le_riscv64 +#define helper_atomic_add_fetchl_le_mmu helper_atomic_add_fetchl_le_mmu_riscv64 +#define helper_atomic_add_fetchq_be helper_atomic_add_fetchq_be_riscv64 +#define helper_atomic_add_fetchq_be_mmu helper_atomic_add_fetchq_be_mmu_riscv64 +#define helper_atomic_add_fetchq_le helper_atomic_add_fetchq_le_riscv64 +#define helper_atomic_add_fetchq_le_mmu helper_atomic_add_fetchq_le_mmu_riscv64 +#define helper_atomic_add_fetchw_be helper_atomic_add_fetchw_be_riscv64 +#define helper_atomic_add_fetchw_be_mmu helper_atomic_add_fetchw_be_mmu_riscv64 +#define helper_atomic_add_fetchw_le helper_atomic_add_fetchw_le_riscv64 +#define helper_atomic_add_fetchw_le_mmu helper_atomic_add_fetchw_le_mmu_riscv64 +#define helper_atomic_and_fetchb helper_atomic_and_fetchb_riscv64 +#define helper_atomic_and_fetchb_le_mmu helper_atomic_and_fetchb_le_mmu_riscv64 +#define helper_atomic_and_fetchb_mmu helper_atomic_and_fetchb_mmu_riscv64 +#define helper_atomic_and_fetchl_be helper_atomic_and_fetchl_be_riscv64 +#define helper_atomic_and_fetchl_be_mmu helper_atomic_and_fetchl_be_mmu_riscv64 +#define helper_atomic_and_fetchl_le helper_atomic_and_fetchl_le_riscv64 +#define helper_atomic_and_fetchl_le_mmu helper_atomic_and_fetchl_le_mmu_riscv64 +#define helper_atomic_and_fetchq_be helper_atomic_and_fetchq_be_riscv64 +#define helper_atomic_and_fetchq_be_mmu helper_atomic_and_fetchq_be_mmu_riscv64 +#define helper_atomic_and_fetchq_le helper_atomic_and_fetchq_le_riscv64 +#define helper_atomic_and_fetchq_le_mmu helper_atomic_and_fetchq_le_mmu_riscv64 +#define helper_atomic_and_fetchw_be helper_atomic_and_fetchw_be_riscv64 +#define helper_atomic_and_fetchw_be_mmu helper_atomic_and_fetchw_be_mmu_riscv64 +#define helper_atomic_and_fetchw_le helper_atomic_and_fetchw_le_riscv64 +#define helper_atomic_and_fetchw_le_mmu helper_atomic_and_fetchw_le_mmu_riscv64 +#define helper_atomic_cmpxchgb helper_atomic_cmpxchgb_riscv64 +#define helper_atomic_cmpxchgb helper_atomic_cmpxchgb_riscv64 +#define helper_atomic_cmpxchgb_mmu helper_atomic_cmpxchgb_mmu_riscv64 +#define helper_atomic_cmpxchgl_be helper_atomic_cmpxchgl_be_riscv64 +#define helper_atomic_cmpxchgl_be_mmu helper_atomic_cmpxchgl_be_mmu_riscv64 +#define helper_atomic_cmpxchgl_le helper_atomic_cmpxchgl_le_riscv64 +#define helper_atomic_cmpxchgl_le_mmu helper_atomic_cmpxchgl_le_mmu_riscv64 +#define helper_atomic_cmpxchgo_be helper_atomic_cmpxchgo_be_riscv64 +#define helper_atomic_cmpxchgo_be_mmu helper_atomic_cmpxchgo_be_mmu_riscv64 +#define helper_atomic_cmpxchgo_le helper_atomic_cmpxchgo_le_riscv64 +#define helper_atomic_cmpxchgo_le_mmu helper_atomic_cmpxchgo_le_mmu_riscv64 +#define helper_atomic_cmpxchgq_be helper_atomic_cmpxchgq_be_riscv64 +#define helper_atomic_cmpxchgq_be_mmu helper_atomic_cmpxchgq_be_mmu_riscv64 +#define helper_atomic_cmpxchgq_le helper_atomic_cmpxchgq_le_riscv64 +#define helper_atomic_cmpxchgq_le_mmu helper_atomic_cmpxchgq_le_mmu_riscv64 +#define helper_atomic_cmpxchgw_be helper_atomic_cmpxchgw_be_riscv64 +#define helper_atomic_cmpxchgw_be_mmu helper_atomic_cmpxchgw_be_mmu_riscv64 +#define helper_atomic_cmpxchgw_le helper_atomic_cmpxchgw_le_riscv64 +#define helper_atomic_cmpxchgw_le_mmu helper_atomic_cmpxchgw_le_mmu_riscv64 +#define helper_atomic_fetch_addb helper_atomic_fetch_addb_riscv64 +#define helper_atomic_fetch_addb_mmu helper_atomic_fetch_addb_mmu_riscv64 +#define helper_atomic_fetch_addl_be helper_atomic_fetch_addl_be_riscv64 +#define helper_atomic_fetch_addl_be_mmu helper_atomic_fetch_addl_be_mmu_riscv64 +#define helper_atomic_fetch_addl_le helper_atomic_fetch_addl_le_riscv64 +#define helper_atomic_fetch_addl_le_mmu helper_atomic_fetch_addl_le_mmu_riscv64 +#define helper_atomic_fetch_addq_be helper_atomic_fetch_addq_be_riscv64 +#define helper_atomic_fetch_addq_be_mmu helper_atomic_fetch_addq_be_mmu_riscv64 +#define helper_atomic_fetch_addq_le helper_atomic_fetch_addq_le_riscv64 +#define helper_atomic_fetch_addq_le_mmu helper_atomic_fetch_addq_le_mmu_riscv64 +#define helper_atomic_fetch_addw_be helper_atomic_fetch_addw_be_riscv64 +#define helper_atomic_fetch_addw_be_mmu helper_atomic_fetch_addw_be_mmu_riscv64 +#define helper_atomic_fetch_addw_le helper_atomic_fetch_addw_le_riscv64 +#define helper_atomic_fetch_addw_le_mmu helper_atomic_fetch_addw_le_mmu_riscv64 +#define helper_atomic_fetch_andb helper_atomic_fetch_andb_riscv64 +#define helper_atomic_fetch_andb_mmu helper_atomic_fetch_andb_mmu_riscv64 +#define helper_atomic_fetch_andl_be helper_atomic_fetch_andl_be_riscv64 +#define helper_atomic_fetch_andl_be_mmu helper_atomic_fetch_andl_be_mmu_riscv64 +#define helper_atomic_fetch_andl_le helper_atomic_fetch_andl_le_riscv64 +#define helper_atomic_fetch_andl_le_mmu helper_atomic_fetch_andl_le_mmu_riscv64 +#define helper_atomic_fetch_andq_be helper_atomic_fetch_andq_be_riscv64 +#define helper_atomic_fetch_andq_be_mmu helper_atomic_fetch_andq_be_mmu_riscv64 +#define helper_atomic_fetch_andq_le helper_atomic_fetch_andq_le_riscv64 +#define helper_atomic_fetch_andq_le_mmu helper_atomic_fetch_andq_le_mmu_riscv64 +#define helper_atomic_fetch_andw_be helper_atomic_fetch_andw_be_riscv64 +#define helper_atomic_fetch_andw_be_mmu helper_atomic_fetch_andw_be_mmu_riscv64 +#define helper_atomic_fetch_andw_le helper_atomic_fetch_andw_le_riscv64 +#define helper_atomic_fetch_andw_le_mmu helper_atomic_fetch_andw_le_mmu_riscv64 +#define helper_atomic_fetch_orb helper_atomic_fetch_orb_riscv64 +#define helper_atomic_fetch_orb_mmu helper_atomic_fetch_orb_mmu_riscv64 +#define helper_atomic_fetch_orl_be helper_atomic_fetch_orl_be_riscv64 +#define helper_atomic_fetch_orl_be_mmu helper_atomic_fetch_orl_be_mmu_riscv64 +#define helper_atomic_fetch_orl_le helper_atomic_fetch_orl_le_riscv64 +#define helper_atomic_fetch_orl_le_mmu helper_atomic_fetch_orl_le_mmu_riscv64 +#define helper_atomic_fetch_orq_be helper_atomic_fetch_orq_be_riscv64 +#define helper_atomic_fetch_orq_be_mmu helper_atomic_fetch_orq_be_mmu_riscv64 +#define helper_atomic_fetch_orq_le helper_atomic_fetch_orq_le_riscv64 +#define helper_atomic_fetch_orq_le_mmu helper_atomic_fetch_orq_le_mmu_riscv64 +#define helper_atomic_fetch_orw_be helper_atomic_fetch_orw_be_riscv64 +#define helper_atomic_fetch_orw_be_mmu helper_atomic_fetch_orw_be_mmu_riscv64 +#define helper_atomic_fetch_orw_le helper_atomic_fetch_orw_le_riscv64 +#define helper_atomic_fetch_orw_le_mmu helper_atomic_fetch_orw_le_mmu_riscv64 +#define helper_atomic_fetch_smaxb_mmu helper_atomic_fetch_smaxb_mmu_riscv64 +#define helper_atomic_fetch_smaxb helper_atomic_fetch_smaxb_riscv64 +#define helper_atomic_fetch_smaxl_be_mmu helper_atomic_fetch_smaxl_be_mmu_riscv64 +#define helper_atomic_fetch_smaxl_be helper_atomic_fetch_smaxl_be_riscv64 +#define helper_atomic_fetch_smaxq_be_mmu helper_atomic_fetch_smaxq_be_mmu_riscv64 +#define helper_atomic_fetch_smaxq_be helper_atomic_fetch_smaxq_be_riscv64 +#define helper_atomic_fetch_smaxw_be_mmu helper_atomic_fetch_smaxw_be_mmu_riscv64 +#define helper_atomic_fetch_smaxw_be helper_atomic_fetch_smaxw_be_riscv64 +#define helper_atomic_fetch_sminb_mmu helper_atomic_fetch_sminb_mmu_riscv64 +#define helper_atomic_fetch_sminb helper_atomic_fetch_sminb_riscv64 +#define helper_atomic_fetch_sminl_be_mmu helper_atomic_fetch_sminl_be_mmu_riscv64 +#define helper_atomic_fetch_sminl_be helper_atomic_fetch_sminl_be_riscv64 +#define helper_atomic_fetch_sminq_be_mmu helper_atomic_fetch_sminq_be_mmu_riscv64 +#define helper_atomic_fetch_sminq_be helper_atomic_fetch_sminq_be_riscv64 +#define helper_atomic_fetch_sminw_be_mmu helper_atomic_fetch_sminw_be_mmu_riscv64 +#define helper_atomic_fetch_sminw_be helper_atomic_fetch_sminw_be_riscv64 +#define helper_atomic_fetch_umaxb_mmu helper_atomic_fetch_umaxb_mmu_riscv64 +#define helper_atomic_fetch_umaxb helper_atomic_fetch_umaxb_riscv64 +#define helper_atomic_fetch_umaxl_be_mmu helper_atomic_fetch_umaxl_be_mmu_riscv64 +#define helper_atomic_fetch_umaxl_be helper_atomic_fetch_umaxl_be_riscv64 +#define helper_atomic_fetch_umaxq_be_mmu helper_atomic_fetch_umaxq_be_mmu_riscv64 +#define helper_atomic_fetch_umaxq_be helper_atomic_fetch_umaxq_be_riscv64 +#define helper_atomic_fetch_umaxw_be_mmu helper_atomic_fetch_umaxw_be_mmu_riscv64 +#define helper_atomic_fetch_umaxw_be helper_atomic_fetch_umaxw_be_riscv64 +#define helper_atomic_fetch_uminb_mmu helper_atomic_fetch_uminb_mmu_riscv64 +#define helper_atomic_fetch_uminb helper_atomic_fetch_uminb_riscv64 +#define helper_atomic_fetch_uminl_be_mmu helper_atomic_fetch_uminl_be_mmu_riscv64 +#define helper_atomic_fetch_uminl_be helper_atomic_fetch_uminl_be_riscv64 +#define helper_atomic_fetch_uminq_be_mmu helper_atomic_fetch_uminq_be_mmu_riscv64 +#define helper_atomic_fetch_uminq_be helper_atomic_fetch_uminq_be_riscv64 +#define helper_atomic_fetch_uminw_be_mmu helper_atomic_fetch_uminw_be_mmu_riscv64 +#define helper_atomic_fetch_uminw_be helper_atomic_fetch_uminw_be_riscv64 +#define helper_atomic_fetch_smaxl_le_mmu helper_atomic_fetch_smaxl_le_mmu_riscv64 +#define helper_atomic_fetch_smaxl_le helper_atomic_fetch_smaxl_le_riscv64 +#define helper_atomic_fetch_smaxq_le_mmu helper_atomic_fetch_smaxq_le_mmu_riscv64 +#define helper_atomic_fetch_smaxq_le helper_atomic_fetch_smaxq_le_riscv64 +#define helper_atomic_fetch_smaxw_le_mmu helper_atomic_fetch_smaxw_le_mmu_riscv64 +#define helper_atomic_fetch_smaxw_le helper_atomic_fetch_smaxw_le_riscv64 +#define helper_atomic_fetch_sminl_le_mmu helper_atomic_fetch_sminl_le_mmu_riscv64 +#define helper_atomic_fetch_sminl_le helper_atomic_fetch_sminl_le_riscv64 +#define helper_atomic_fetch_sminq_le_mmu helper_atomic_fetch_sminq_le_mmu_riscv64 +#define helper_atomic_fetch_sminq_le helper_atomic_fetch_sminq_le_riscv64 +#define helper_atomic_fetch_sminw_le_mmu helper_atomic_fetch_sminw_le_mmu_riscv64 +#define helper_atomic_fetch_sminw_le helper_atomic_fetch_sminw_le_riscv64 +#define helper_atomic_fetch_umaxl_le_mmu helper_atomic_fetch_umaxl_le_mmu_riscv64 +#define helper_atomic_fetch_umaxl_le helper_atomic_fetch_umaxl_le_riscv64 +#define helper_atomic_fetch_umaxq_le_mmu helper_atomic_fetch_umaxq_le_mmu_riscv64 +#define helper_atomic_fetch_umaxq_le helper_atomic_fetch_umaxq_le_riscv64 +#define helper_atomic_fetch_umaxw_le_mmu helper_atomic_fetch_umaxw_le_mmu_riscv64 +#define helper_atomic_fetch_umaxw_le helper_atomic_fetch_umaxw_le_riscv64 +#define helper_atomic_fetch_uminl_le_mmu helper_atomic_fetch_uminl_le_mmu_riscv64 +#define helper_atomic_fetch_uminl_le helper_atomic_fetch_uminl_le_riscv64 +#define helper_atomic_fetch_uminq_le_mmu helper_atomic_fetch_uminq_le_mmu_riscv64 +#define helper_atomic_fetch_uminq_le helper_atomic_fetch_uminq_le_riscv64 +#define helper_atomic_fetch_uminw_le_mmu helper_atomic_fetch_uminw_le_mmu_riscv64 +#define helper_atomic_fetch_uminw_le helper_atomic_fetch_uminw_le_riscv64 +#define helper_atomic_fetch_xorb helper_atomic_fetch_xorb_riscv64 +#define helper_atomic_fetch_xorb_mmu helper_atomic_fetch_xorb_mmu_riscv64 +#define helper_atomic_fetch_xorl_be helper_atomic_fetch_xorl_be_riscv64 +#define helper_atomic_fetch_xorl_be_mmu helper_atomic_fetch_xorl_be_mmu_riscv64 +#define helper_atomic_fetch_xorl_le helper_atomic_fetch_xorl_le_riscv64 +#define helper_atomic_fetch_xorl_le_mmu helper_atomic_fetch_xorl_le_mmu_riscv64 +#define helper_atomic_fetch_xorq_be helper_atomic_fetch_xorq_be_riscv64 +#define helper_atomic_fetch_xorq_be_mmu helper_atomic_fetch_xorq_be_mmu_riscv64 +#define helper_atomic_fetch_xorq_le helper_atomic_fetch_xorq_le_riscv64 +#define helper_atomic_fetch_xorq_le_mmu helper_atomic_fetch_xorq_le_mmu_riscv64 +#define helper_atomic_fetch_xorw_be helper_atomic_fetch_xorw_be_riscv64 +#define helper_atomic_fetch_xorw_be_mmu helper_atomic_fetch_xorw_be_mmu_riscv64 +#define helper_atomic_fetch_xorw_le helper_atomic_fetch_xorw_le_riscv64 +#define helper_atomic_fetch_xorw_le_mmu helper_atomic_fetch_xorw_le_mmu_riscv64 +#define helper_atomic_ldo_be helper_atomic_ldo_be_riscv64 +#define helper_atomic_ldo_be_mmu helper_atomic_ldo_be_mmu_riscv64 +#define helper_atomic_ldo_le helper_atomic_ldo_le_riscv64 +#define helper_atomic_ldo_le_mmu helper_atomic_ldo_le_mmu_riscv64 +#define helper_atomic_or_fetchb helper_atomic_or_fetchb_riscv64 +#define helper_atomic_or_fetchb_mmu helper_atomic_or_fetchb_mmu_riscv64 +#define helper_atomic_or_fetchl_be helper_atomic_or_fetchl_be_riscv64 +#define helper_atomic_or_fetchl_be_mmu helper_atomic_or_fetchl_be_mmu_riscv64 +#define helper_atomic_or_fetchl_le helper_atomic_or_fetchl_le_riscv64 +#define helper_atomic_or_fetchl_le_mmu helper_atomic_or_fetchl_le_mmu_riscv64 +#define helper_atomic_or_fetchq_be helper_atomic_or_fetchq_be_riscv64 +#define helper_atomic_or_fetchq_be_mmu helper_atomic_or_fetchq_be_mmu_riscv64 +#define helper_atomic_or_fetchq_le helper_atomic_or_fetchq_le_riscv64 +#define helper_atomic_or_fetchq_le_mmu helper_atomic_or_fetchq_le_mmu_riscv64 +#define helper_atomic_or_fetchw_be helper_atomic_or_fetchw_be_riscv64 +#define helper_atomic_or_fetchw_be_mmu helper_atomic_or_fetchw_be_mmu_riscv64 +#define helper_atomic_or_fetchw_le helper_atomic_or_fetchw_le_riscv64 +#define helper_atomic_or_fetchw_le_mmu helper_atomic_or_fetchw_le_mmu_riscv64 +#define helper_atomic_smax_fetchb_mmu helper_atomic_smax_fetchb_mmu_riscv64 +#define helper_atomic_smax_fetchb helper_atomic_smax_fetchb_riscv64 +#define helper_atomic_smax_fetchl_be_mmu helper_atomic_smax_fetchl_be_mmu_riscv64 +#define helper_atomic_smax_fetchl_be helper_atomic_smax_fetchl_be_riscv64 +#define helper_atomic_smax_fetchq_be_mmu helper_atomic_smax_fetchq_be_mmu_riscv64 +#define helper_atomic_smax_fetchq_be helper_atomic_smax_fetchq_be_riscv64 +#define helper_atomic_smax_fetchw_be_mmu helper_atomic_smax_fetchw_be_mmu_riscv64 +#define helper_atomic_smax_fetchw_be helper_atomic_smax_fetchw_be_riscv64 +#define helper_atomic_smin_fetchb_mmu helper_atomic_smin_fetchb_mmu_riscv64 +#define helper_atomic_smin_fetchb helper_atomic_smin_fetchb_riscv64 +#define helper_atomic_smin_fetchl_be_mmu helper_atomic_smin_fetchl_be_mmu_riscv64 +#define helper_atomic_smin_fetchl_be helper_atomic_smin_fetchl_be_riscv64 +#define helper_atomic_smin_fetchq_be_mmu helper_atomic_smin_fetchq_be_mmu_riscv64 +#define helper_atomic_smin_fetchq_be helper_atomic_smin_fetchq_be_riscv64 +#define helper_atomic_smin_fetchw_be_mmu helper_atomic_smin_fetchw_be_mmu_riscv64 +#define helper_atomic_smin_fetchw_be helper_atomic_smin_fetchw_be_riscv64 +#define helper_atomic_smax_fetchl_le_mmu helper_atomic_smax_fetchl_le_mmu_riscv64 +#define helper_atomic_smax_fetchl_le helper_atomic_smax_fetchl_le_riscv64 +#define helper_atomic_smax_fetchq_le_mmu helper_atomic_smax_fetchq_le_mmu_riscv64 +#define helper_atomic_smax_fetchq_le helper_atomic_smax_fetchq_le_riscv64 +#define helper_atomic_smax_fetchw_le_mmu helper_atomic_smax_fetchw_le_mmu_riscv64 +#define helper_atomic_smax_fetchw_le helper_atomic_smax_fetchw_le_riscv64 +#define helper_atomic_smin_fetchl_le_mmu helper_atomic_smin_fetchl_le_mmu_riscv64 +#define helper_atomic_smin_fetchl_le helper_atomic_smin_fetchl_le_riscv64 +#define helper_atomic_smin_fetchq_le_mmu helper_atomic_smin_fetchq_le_mmu_riscv64 +#define helper_atomic_smin_fetchq_le helper_atomic_smin_fetchq_le_riscv64 +#define helper_atomic_smin_fetchw_le_mmu helper_atomic_smin_fetchw_le_mmu_riscv64 +#define helper_atomic_smin_fetchw_le helper_atomic_smin_fetchw_le_riscv64 +#define helper_atomic_sto_be helper_atomic_sto_be_riscv64 +#define helper_atomic_sto_be_mmu helper_atomic_sto_be_mmu_riscv64 +#define helper_atomic_sto_le helper_atomic_sto_le_riscv64 +#define helper_atomic_sto_le_mmu helper_atomic_sto_le_mmu_riscv64 +#define helper_atomic_umax_fetchb_mmu helper_atomic_umax_fetchb_mmu_riscv64 +#define helper_atomic_umax_fetchb helper_atomic_umax_fetchb_riscv64 +#define helper_atomic_umax_fetchl_be_mmu helper_atomic_umax_fetchl_be_mmu_riscv64 +#define helper_atomic_umax_fetchl_be helper_atomic_umax_fetchl_be_riscv64 +#define helper_atomic_umax_fetchq_be_mmu helper_atomic_umax_fetchq_be_mmu_riscv64 +#define helper_atomic_umax_fetchq_be helper_atomic_umax_fetchq_be_riscv64 +#define helper_atomic_umax_fetchw_be_mmu helper_atomic_umax_fetchw_be_mmu_riscv64 +#define helper_atomic_umax_fetchw_be helper_atomic_umax_fetchw_be_riscv64 +#define helper_atomic_umin_fetchb_mmu helper_atomic_umin_fetchb_mmu_riscv64 +#define helper_atomic_umin_fetchb helper_atomic_umin_fetchb_riscv64 +#define helper_atomic_umin_fetchl_be_mmu helper_atomic_umin_fetchl_be_mmu_riscv64 +#define helper_atomic_umin_fetchl_be helper_atomic_umin_fetchl_be_riscv64 +#define helper_atomic_umin_fetchq_be_mmu helper_atomic_umin_fetchq_be_mmu_riscv64 +#define helper_atomic_umin_fetchq_be helper_atomic_umin_fetchq_be_riscv64 +#define helper_atomic_umin_fetchw_be_mmu helper_atomic_umin_fetchw_be_mmu_riscv64 +#define helper_atomic_umin_fetchw_be helper_atomic_umin_fetchw_be_riscv64 +#define helper_atomic_umax_fetchl_le_mmu helper_atomic_umax_fetchl_le_mmu_riscv64 +#define helper_atomic_umax_fetchl_le helper_atomic_umax_fetchl_le_riscv64 +#define helper_atomic_umax_fetchq_le_mmu helper_atomic_umax_fetchq_le_mmu_riscv64 +#define helper_atomic_umax_fetchq_le helper_atomic_umax_fetchq_le_riscv64 +#define helper_atomic_umax_fetchw_le_mmu helper_atomic_umax_fetchw_le_mmu_riscv64 +#define helper_atomic_umax_fetchw_le helper_atomic_umax_fetchw_le_riscv64 +#define helper_atomic_umin_fetchl_le_mmu helper_atomic_umin_fetchl_le_mmu_riscv64 +#define helper_atomic_umin_fetchl_le helper_atomic_umin_fetchl_le_riscv64 +#define helper_atomic_umin_fetchq_le_mmu helper_atomic_umin_fetchq_le_mmu_riscv64 +#define helper_atomic_umin_fetchq_le helper_atomic_umin_fetchq_le_riscv64 +#define helper_atomic_umin_fetchw_le_mmu helper_atomic_umin_fetchw_le_mmu_riscv64 +#define helper_atomic_umin_fetchw_le helper_atomic_umin_fetchw_le_riscv64 +#define helper_atomic_xchgb helper_atomic_xchgb_riscv64 +#define helper_atomic_xchgb helper_atomic_xchgb_riscv64 +#define helper_atomic_xchgb_mmu helper_atomic_xchgb_mmu_riscv64 +#define helper_atomic_xchgl_be helper_atomic_xchgl_be_riscv64 +#define helper_atomic_xchgl_be_mmu helper_atomic_xchgl_be_mmu_riscv64 +#define helper_atomic_xchgl_le helper_atomic_xchgl_le_riscv64 +#define helper_atomic_xchgl_le_mmu helper_atomic_xchgl_le_mmu_riscv64 +#define helper_atomic_xchgq_be helper_atomic_xchgq_be_riscv64 +#define helper_atomic_xchgq_be_mmu helper_atomic_xchgq_be_mmu_riscv64 +#define helper_atomic_xchgq_le helper_atomic_xchgq_le_riscv64 +#define helper_atomic_xchgq_le_mmu helper_atomic_xchgq_le_mmu_riscv64 +#define helper_atomic_xchgw_be helper_atomic_xchgw_be_riscv64 +#define helper_atomic_xchgw_be_mmu helper_atomic_xchgw_be_mmu_riscv64 +#define helper_atomic_xchgw_le helper_atomic_xchgw_le_riscv64 +#define helper_atomic_xchgw_le_mmu helper_atomic_xchgw_le_mmu_riscv64 +#define helper_atomic_xor_fetchb helper_atomic_xor_fetchb_riscv64 +#define helper_atomic_xor_fetchb_mmu helper_atomic_xor_fetchb_mmu_riscv64 +#define helper_atomic_xor_fetchl_be helper_atomic_xor_fetchl_be_riscv64 +#define helper_atomic_xor_fetchl_be_mmu helper_atomic_xor_fetchl_be_mmu_riscv64 +#define helper_atomic_xor_fetchl_le helper_atomic_xor_fetchl_le_riscv64 +#define helper_atomic_xor_fetchl_le_mmu helper_atomic_xor_fetchl_le_mmu_riscv64 +#define helper_atomic_xor_fetchq_be helper_atomic_xor_fetchq_be_riscv64 +#define helper_atomic_xor_fetchq_be_mmu helper_atomic_xor_fetchq_be_mmu_riscv64 +#define helper_atomic_xor_fetchq_le helper_atomic_xor_fetchq_le_riscv64 +#define helper_atomic_xor_fetchq_le_mmu helper_atomic_xor_fetchq_le_mmu_riscv64 +#define helper_atomic_xor_fetchw_be helper_atomic_xor_fetchw_be_riscv64 +#define helper_atomic_xor_fetchw_be_mmu helper_atomic_xor_fetchw_be_mmu_riscv64 +#define helper_atomic_xor_fetchw_le helper_atomic_xor_fetchw_le_riscv64 +#define helper_atomic_xor_fetchw_le_mmu helper_atomic_xor_fetchw_le_mmu_riscv64 +#define helper_be_ldl_cmmu helper_be_ldl_cmmu_riscv64 +#define helper_be_ldq_cmmu helper_be_ldq_cmmu_riscv64 +#define helper_be_ldq_mmu helper_be_ldq_mmu_riscv64 +#define helper_be_ldsl_mmu helper_be_ldsl_mmu_riscv64 +#define helper_be_ldsw_mmu helper_be_ldsw_mmu_riscv64 +#define helper_be_ldul_mmu helper_be_ldul_mmu_riscv64 +#define helper_be_lduw_mmu helper_be_lduw_mmu_riscv64 +#define helper_be_ldw_cmmu helper_be_ldw_cmmu_riscv64 +#define helper_be_stl_mmu helper_be_stl_mmu_riscv64 +#define helper_be_stq_mmu helper_be_stq_mmu_riscv64 +#define helper_be_stw_mmu helper_be_stw_mmu_riscv64 +#define helper_clear_pstate_ss helper_clear_pstate_ss_riscv64 +#define helper_clrsb_i32 helper_clrsb_i32_riscv64 +#define helper_clrsb_i64 helper_clrsb_i64_riscv64 +#define helper_clz_i32 helper_clz_i32_riscv64 +#define helper_clz_i64 helper_clz_i64_riscv64 +#define helper_ctpop_i32 helper_ctpop_i32_riscv64 +#define helper_ctpop_i64 helper_ctpop_i64_riscv64 +#define helper_ctz_i32 helper_ctz_i32_riscv64 +#define helper_ctz_i64 helper_ctz_i64_riscv64 +#define helper_cpsr_read helper_cpsr_read_riscv64 +#define helper_cpsr_write helper_cpsr_write_riscv64 +#define helper_cpsr_write_eret helper_cpsr_write_eret_riscv64 +#define helper_crc32_arm helper_crc32_arm_riscv64 +#define helper_crc32c helper_crc32c_riscv64 +#define helper_crypto_aese helper_crypto_aese_riscv64 +#define helper_crypto_aesmc helper_crypto_aesmc_riscv64 +#define helper_crypto_sha1_3reg helper_crypto_sha1_3reg_riscv64 +#define helper_crypto_sha1h helper_crypto_sha1h_riscv64 +#define helper_crypto_sha1su1 helper_crypto_sha1su1_riscv64 +#define helper_crypto_sha256h helper_crypto_sha256h_riscv64 +#define helper_crypto_sha256h2 helper_crypto_sha256h2_riscv64 +#define helper_crypto_sha256su0 helper_crypto_sha256su0_riscv64 +#define helper_crypto_sha256su1 helper_crypto_sha256su1_riscv64 +#define helper_crypto_sha512h helper_crypto_sha512h_riscv64 +#define helper_crypto_sha512h2 helper_crypto_sha512h2_riscv64 +#define helper_crypto_sha512su0 helper_crypto_sha512su0_riscv64 +#define helper_crypto_sha512su1 helper_crypto_sha512su1_riscv64 +#define helper_crypto_sm3partw1 helper_crypto_sm3partw1_riscv64 +#define helper_crypto_sm3partw2 helper_crypto_sm3partw2_riscv64 +#define helper_crypto_sm3tt helper_crypto_sm3tt_riscv64 +#define helper_crypto_sm4e helper_crypto_sm4e_riscv64 +#define helper_crypto_sm4ekey helper_crypto_sm4ekey_riscv64 +#define helper_dc_zva helper_dc_zva_riscv64 +#define helper_div_i32 helper_div_i32_riscv64 +#define helper_div_i64 helper_div_i64_riscv64 +#define helper_divu_i32 helper_divu_i32_riscv64 +#define helper_divu_i64 helper_divu_i64_riscv64 +#define helper_double_saturate helper_double_saturate_riscv64 +#define helper_exception_bkpt_insn helper_exception_bkpt_insn_riscv64 +#define helper_exception_internal helper_exception_internal_riscv64 +#define helper_exception_return helper_exception_return_riscv64 +#define helper_exception_with_syndrome helper_exception_with_syndrome_riscv64 +#define helper_exit_atomic helper_exit_atomic_riscv64 +#define helper_get_cp_reg helper_get_cp_reg_riscv64 +#define helper_get_cp_reg64 helper_get_cp_reg64_riscv64 +#define helper_get_r13_banked helper_get_r13_banked_riscv64 +#define helper_get_user_reg helper_get_user_reg_riscv64 +#define helper_gvec_add8 helper_gvec_add8_riscv64 +#define helper_gvec_add16 helper_gvec_add16_riscv64 +#define helper_gvec_add32 helper_gvec_add32_riscv64 +#define helper_gvec_add64 helper_gvec_add64_riscv64 +#define helper_gvec_adds8 helper_gvec_adds8_riscv64 +#define helper_gvec_adds16 helper_gvec_adds16_riscv64 +#define helper_gvec_adds32 helper_gvec_adds32_riscv64 +#define helper_gvec_adds64 helper_gvec_adds64_riscv64 +#define helper_gvec_and helper_gvec_and_riscv64 +#define helper_gvec_andc helper_gvec_andc_riscv64 +#define helper_gvec_ands helper_gvec_ands_riscv64 +#define helper_gvec_dup8 helper_gvec_dup8_riscv64 +#define helper_gvec_dup16 helper_gvec_dup16_riscv64 +#define helper_gvec_dup32 helper_gvec_dup32_riscv64 +#define helper_gvec_dup64 helper_gvec_dup64_riscv64 +#define helper_gvec_eq8 helper_gvec_eq8_riscv64 +#define helper_gvec_eq16 helper_gvec_eq16_riscv64 +#define helper_gvec_eq32 helper_gvec_eq32_riscv64 +#define helper_gvec_eq64 helper_gvec_eq64_riscv64 +#define helper_gvec_fadd_d helper_gvec_fadd_d_riscv64 +#define helper_gvec_fadd_h helper_gvec_fadd_h_riscv64 +#define helper_gvec_fadd_s helper_gvec_fadd_s_riscv64 +#define helper_gvec_fcaddh helper_gvec_fcaddh_riscv64 +#define helper_gvec_fcadds helper_gvec_fcadds_riscv64 +#define helper_gvec_fcaddd helper_gvec_fcaddd_riscv64 +#define helper_gvec_fcmlad helper_gvec_fcmlad_riscv64 +#define helper_gvec_fcmlah helper_gvec_fcmlah_riscv64 +#define helper_gvec_fcmlah_idx helper_gvec_fcmlah_idx_riscv64 +#define helper_gvec_fcmlas helper_gvec_fcmlas_riscv64 +#define helper_gvec_fcmlas_idx helper_gvec_fcmlas_idx_riscv64 +#define helper_gvec_fmla_idx_d helper_gvec_fmla_idx_d_riscv64 +#define helper_gvec_fmla_idx_h helper_gvec_fmla_idx_h_riscv64 +#define helper_gvec_fmla_idx_s helper_gvec_fmla_idx_s_riscv64 +#define helper_gvec_fmul_d helper_gvec_fmul_d_riscv64 +#define helper_gvec_fmul_h helper_gvec_fmul_h_riscv64 +#define helper_gvec_fmul_s helper_gvec_fmul_s_riscv64 +#define helper_gvec_fmul_idx_d helper_gvec_fmul_idx_d_riscv64 +#define helper_gvec_fmul_idx_h helper_gvec_fmul_idx_h_riscv64 +#define helper_gvec_fmul_idx_s helper_gvec_fmul_idx_s_riscv64 +#define helper_gvec_frecpe_d helper_gvec_frecpe_d_riscv64 +#define helper_gvec_frecpe_h helper_gvec_frecpe_h_riscv64 +#define helper_gvec_frecpe_s helper_gvec_frecpe_s_riscv64 +#define helper_gvec_frsqrte_d helper_gvec_frsqrte_d_riscv64 +#define helper_gvec_frsqrte_h helper_gvec_frsqrte_h_riscv64 +#define helper_gvec_frsqrte_s helper_gvec_frsqrte_s_riscv64 +#define helper_gvec_fsub_d helper_gvec_fsub_d_riscv64 +#define helper_gvec_fsub_h helper_gvec_fsub_h_riscv64 +#define helper_gvec_fsub_s helper_gvec_fsub_s_riscv64 +#define helper_gvec_ftsmul_d helper_gvec_ftsmul_d_riscv64 +#define helper_gvec_ftsmul_h helper_gvec_ftsmul_h_riscv64 +#define helper_gvec_ftsmul_s helper_gvec_ftsmul_s_riscv64 +#define helper_gvec_le8 helper_gvec_le8_riscv64 +#define helper_gvec_le16 helper_gvec_le16_riscv64 +#define helper_gvec_le32 helper_gvec_le32_riscv64 +#define helper_gvec_le64 helper_gvec_le64_riscv64 +#define helper_gvec_leu8 helper_gvec_leu8_riscv64 +#define helper_gvec_leu16 helper_gvec_leu16_riscv64 +#define helper_gvec_leu32 helper_gvec_leu32_riscv64 +#define helper_gvec_leu64 helper_gvec_leu64_riscv64 +#define helper_gvec_lt8 helper_gvec_lt8_riscv64 +#define helper_gvec_lt16 helper_gvec_lt16_riscv64 +#define helper_gvec_lt32 helper_gvec_lt32_riscv64 +#define helper_gvec_lt64 helper_gvec_lt64_riscv64 +#define helper_gvec_ltu8 helper_gvec_ltu8_riscv64 +#define helper_gvec_ltu16 helper_gvec_ltu16_riscv64 +#define helper_gvec_ltu32 helper_gvec_ltu32_riscv64 +#define helper_gvec_ltu64 helper_gvec_ltu64_riscv64 +#define helper_gvec_mov helper_gvec_mov_riscv64 +#define helper_gvec_mul8 helper_gvec_mul8_riscv64 +#define helper_gvec_mul16 helper_gvec_mul16_riscv64 +#define helper_gvec_mul32 helper_gvec_mul32_riscv64 +#define helper_gvec_mul64 helper_gvec_mul64_riscv64 +#define helper_gvec_muls8 helper_gvec_muls8_riscv64 +#define helper_gvec_muls16 helper_gvec_muls16_riscv64 +#define helper_gvec_muls32 helper_gvec_muls32_riscv64 +#define helper_gvec_muls64 helper_gvec_muls64_riscv64 +#define helper_gvec_ne8 helper_gvec_ne8_riscv64 +#define helper_gvec_ne16 helper_gvec_ne16_riscv64 +#define helper_gvec_ne32 helper_gvec_ne32_riscv64 +#define helper_gvec_ne64 helper_gvec_ne64_riscv64 +#define helper_gvec_neg8 helper_gvec_neg8_riscv64 +#define helper_gvec_neg16 helper_gvec_neg16_riscv64 +#define helper_gvec_neg32 helper_gvec_neg32_riscv64 +#define helper_gvec_neg64 helper_gvec_neg64_riscv64 +#define helper_gvec_not helper_gvec_not_riscv64 +#define helper_gvec_or helper_gvec_or_riscv64 +#define helper_gvec_orc helper_gvec_orc_riscv64 +#define helper_gvec_ors helper_gvec_ors_riscv64 +#define helper_gvec_qrdmlah_s16 helper_gvec_qrdmlah_s16_riscv64 +#define helper_gvec_qrdmlah_s32 helper_gvec_qrdmlah_s32_riscv64 +#define helper_gvec_qrdmlsh_s16 helper_gvec_qrdmlsh_s16_riscv64 +#define helper_gvec_qrdmlsh_s32 helper_gvec_qrdmlsh_s32_riscv64 +#define helper_gvec_sar8i helper_gvec_sar8i_riscv64 +#define helper_gvec_sar16i helper_gvec_sar16i_riscv64 +#define helper_gvec_sar32i helper_gvec_sar32i_riscv64 +#define helper_gvec_sar64i helper_gvec_sar64i_riscv64 +#define helper_gvec_sdot_b helper_gvec_sdot_b_riscv64 +#define helper_gvec_sdot_h helper_gvec_sdot_h_riscv64 +#define helper_gvec_sdot_idx_b helper_gvec_sdot_idx_b_riscv64 +#define helper_gvec_sdot_idx_h helper_gvec_sdot_idx_h_riscv64 +#define helper_gvec_shl8i helper_gvec_shl8i_riscv64 +#define helper_gvec_shl16i helper_gvec_shl16i_riscv64 +#define helper_gvec_shl32i helper_gvec_shl32i_riscv64 +#define helper_gvec_shl64i helper_gvec_shl64i_riscv64 +#define helper_gvec_shr8i helper_gvec_shr8i_riscv64 +#define helper_gvec_shr16i helper_gvec_shr16i_riscv64 +#define helper_gvec_shr32i helper_gvec_shr32i_riscv64 +#define helper_gvec_shr64i helper_gvec_shr64i_riscv64 +#define helper_gvec_sub8 helper_gvec_sub8_riscv64 +#define helper_gvec_sub16 helper_gvec_sub16_riscv64 +#define helper_gvec_sub32 helper_gvec_sub32_riscv64 +#define helper_gvec_sub64 helper_gvec_sub64_riscv64 +#define helper_gvec_subs8 helper_gvec_subs8_riscv64 +#define helper_gvec_subs16 helper_gvec_subs16_riscv64 +#define helper_gvec_subs32 helper_gvec_subs32_riscv64 +#define helper_gvec_subs64 helper_gvec_subs64_riscv64 +#define helper_gvec_ssadd8 helper_gvec_ssadd8_riscv64 +#define helper_gvec_ssadd16 helper_gvec_ssadd16_riscv64 +#define helper_gvec_ssadd32 helper_gvec_ssadd32_riscv64 +#define helper_gvec_ssadd64 helper_gvec_ssadd64_riscv64 +#define helper_gvec_sssub8 helper_gvec_sssub8_riscv64 +#define helper_gvec_sssub16 helper_gvec_sssub16_riscv64 +#define helper_gvec_sssub32 helper_gvec_sssub32_riscv64 +#define helper_gvec_sssub64 helper_gvec_sssub64_riscv64 +#define helper_gvec_udot_b helper_gvec_udot_b_riscv64 +#define helper_gvec_udot_h helper_gvec_udot_h_riscv64 +#define helper_gvec_udot_idx_b helper_gvec_udot_idx_b_riscv64 +#define helper_gvec_udot_idx_h helper_gvec_udot_idx_h_riscv64 +#define helper_gvec_usadd8 helper_gvec_usadd8_riscv64 +#define helper_gvec_usadd16 helper_gvec_usadd16_riscv64 +#define helper_gvec_usadd32 helper_gvec_usadd32_riscv64 +#define helper_gvec_usadd64 helper_gvec_usadd64_riscv64 +#define helper_gvec_ussub8 helper_gvec_ussub8_riscv64 +#define helper_gvec_ussub16 helper_gvec_ussub16_riscv64 +#define helper_gvec_ussub32 helper_gvec_ussub32_riscv64 +#define helper_gvec_ussub64 helper_gvec_ussub64_riscv64 +#define helper_gvec_xor helper_gvec_xor_riscv64 +#define helper_gvec_xors helper_gvec_xors_riscv64 +#define helper_iwmmxt_addcb helper_iwmmxt_addcb_riscv64 +#define helper_iwmmxt_addcl helper_iwmmxt_addcl_riscv64 +#define helper_iwmmxt_addcw helper_iwmmxt_addcw_riscv64 +#define helper_iwmmxt_addnb helper_iwmmxt_addnb_riscv64 +#define helper_iwmmxt_addnl helper_iwmmxt_addnl_riscv64 +#define helper_iwmmxt_addnw helper_iwmmxt_addnw_riscv64 +#define helper_iwmmxt_addsb helper_iwmmxt_addsb_riscv64 +#define helper_iwmmxt_addsl helper_iwmmxt_addsl_riscv64 +#define helper_iwmmxt_addsw helper_iwmmxt_addsw_riscv64 +#define helper_iwmmxt_addub helper_iwmmxt_addub_riscv64 +#define helper_iwmmxt_addul helper_iwmmxt_addul_riscv64 +#define helper_iwmmxt_adduw helper_iwmmxt_adduw_riscv64 +#define helper_iwmmxt_align helper_iwmmxt_align_riscv64 +#define helper_iwmmxt_avgb0 helper_iwmmxt_avgb0_riscv64 +#define helper_iwmmxt_avgb1 helper_iwmmxt_avgb1_riscv64 +#define helper_iwmmxt_avgw0 helper_iwmmxt_avgw0_riscv64 +#define helper_iwmmxt_avgw1 helper_iwmmxt_avgw1_riscv64 +#define helper_iwmmxt_bcstb helper_iwmmxt_bcstb_riscv64 +#define helper_iwmmxt_bcstl helper_iwmmxt_bcstl_riscv64 +#define helper_iwmmxt_bcstw helper_iwmmxt_bcstw_riscv64 +#define helper_iwmmxt_cmpeqb helper_iwmmxt_cmpeqb_riscv64 +#define helper_iwmmxt_cmpeql helper_iwmmxt_cmpeql_riscv64 +#define helper_iwmmxt_cmpeqw helper_iwmmxt_cmpeqw_riscv64 +#define helper_iwmmxt_cmpgtsb helper_iwmmxt_cmpgtsb_riscv64 +#define helper_iwmmxt_cmpgtsl helper_iwmmxt_cmpgtsl_riscv64 +#define helper_iwmmxt_cmpgtsw helper_iwmmxt_cmpgtsw_riscv64 +#define helper_iwmmxt_cmpgtub helper_iwmmxt_cmpgtub_riscv64 +#define helper_iwmmxt_cmpgtul helper_iwmmxt_cmpgtul_riscv64 +#define helper_iwmmxt_cmpgtuw helper_iwmmxt_cmpgtuw_riscv64 +#define helper_iwmmxt_insr helper_iwmmxt_insr_riscv64 +#define helper_iwmmxt_macsw helper_iwmmxt_macsw_riscv64 +#define helper_iwmmxt_macuw helper_iwmmxt_macuw_riscv64 +#define helper_iwmmxt_maddsq helper_iwmmxt_maddsq_riscv64 +#define helper_iwmmxt_madduq helper_iwmmxt_madduq_riscv64 +#define helper_iwmmxt_maxsb helper_iwmmxt_maxsb_riscv64 +#define helper_iwmmxt_maxsl helper_iwmmxt_maxsl_riscv64 +#define helper_iwmmxt_maxsw helper_iwmmxt_maxsw_riscv64 +#define helper_iwmmxt_maxub helper_iwmmxt_maxub_riscv64 +#define helper_iwmmxt_maxul helper_iwmmxt_maxul_riscv64 +#define helper_iwmmxt_maxuw helper_iwmmxt_maxuw_riscv64 +#define helper_iwmmxt_minsb helper_iwmmxt_minsb_riscv64 +#define helper_iwmmxt_minsl helper_iwmmxt_minsl_riscv64 +#define helper_iwmmxt_minsw helper_iwmmxt_minsw_riscv64 +#define helper_iwmmxt_minub helper_iwmmxt_minub_riscv64 +#define helper_iwmmxt_minul helper_iwmmxt_minul_riscv64 +#define helper_iwmmxt_minuw helper_iwmmxt_minuw_riscv64 +#define helper_iwmmxt_msbb helper_iwmmxt_msbb_riscv64 +#define helper_iwmmxt_msbl helper_iwmmxt_msbl_riscv64 +#define helper_iwmmxt_msbw helper_iwmmxt_msbw_riscv64 +#define helper_iwmmxt_muladdsl helper_iwmmxt_muladdsl_riscv64 +#define helper_iwmmxt_muladdsw helper_iwmmxt_muladdsw_riscv64 +#define helper_iwmmxt_muladdswl helper_iwmmxt_muladdswl_riscv64 +#define helper_iwmmxt_mulshw helper_iwmmxt_mulshw_riscv64 +#define helper_iwmmxt_mulslw helper_iwmmxt_mulslw_riscv64 +#define helper_iwmmxt_muluhw helper_iwmmxt_muluhw_riscv64 +#define helper_iwmmxt_mululw helper_iwmmxt_mululw_riscv64 +#define helper_iwmmxt_packsl helper_iwmmxt_packsl_riscv64 +#define helper_iwmmxt_packsq helper_iwmmxt_packsq_riscv64 +#define helper_iwmmxt_packsw helper_iwmmxt_packsw_riscv64 +#define helper_iwmmxt_packul helper_iwmmxt_packul_riscv64 +#define helper_iwmmxt_packuq helper_iwmmxt_packuq_riscv64 +#define helper_iwmmxt_packuw helper_iwmmxt_packuw_riscv64 +#define helper_iwmmxt_rorl helper_iwmmxt_rorl_riscv64 +#define helper_iwmmxt_rorq helper_iwmmxt_rorq_riscv64 +#define helper_iwmmxt_rorw helper_iwmmxt_rorw_riscv64 +#define helper_iwmmxt_sadb helper_iwmmxt_sadb_riscv64 +#define helper_iwmmxt_sadw helper_iwmmxt_sadw_riscv64 +#define helper_iwmmxt_setpsr_nz helper_iwmmxt_setpsr_nz_riscv64 +#define helper_iwmmxt_shufh helper_iwmmxt_shufh_riscv64 +#define helper_iwmmxt_slll helper_iwmmxt_slll_riscv64 +#define helper_iwmmxt_sllq helper_iwmmxt_sllq_riscv64 +#define helper_iwmmxt_sllw helper_iwmmxt_sllw_riscv64 +#define helper_iwmmxt_sral helper_iwmmxt_sral_riscv64 +#define helper_iwmmxt_sraq helper_iwmmxt_sraq_riscv64 +#define helper_iwmmxt_sraw helper_iwmmxt_sraw_riscv64 +#define helper_iwmmxt_srll helper_iwmmxt_srll_riscv64 +#define helper_iwmmxt_srlq helper_iwmmxt_srlq_riscv64 +#define helper_iwmmxt_srlw helper_iwmmxt_srlw_riscv64 +#define helper_iwmmxt_subnb helper_iwmmxt_subnb_riscv64 +#define helper_iwmmxt_subnl helper_iwmmxt_subnl_riscv64 +#define helper_iwmmxt_subnw helper_iwmmxt_subnw_riscv64 +#define helper_iwmmxt_subsb helper_iwmmxt_subsb_riscv64 +#define helper_iwmmxt_subsl helper_iwmmxt_subsl_riscv64 +#define helper_iwmmxt_subsw helper_iwmmxt_subsw_riscv64 +#define helper_iwmmxt_subub helper_iwmmxt_subub_riscv64 +#define helper_iwmmxt_subul helper_iwmmxt_subul_riscv64 +#define helper_iwmmxt_subuw helper_iwmmxt_subuw_riscv64 +#define helper_iwmmxt_unpackhb helper_iwmmxt_unpackhb_riscv64 +#define helper_iwmmxt_unpackhl helper_iwmmxt_unpackhl_riscv64 +#define helper_iwmmxt_unpackhsb helper_iwmmxt_unpackhsb_riscv64 +#define helper_iwmmxt_unpackhsl helper_iwmmxt_unpackhsl_riscv64 +#define helper_iwmmxt_unpackhsw helper_iwmmxt_unpackhsw_riscv64 +#define helper_iwmmxt_unpackhub helper_iwmmxt_unpackhub_riscv64 +#define helper_iwmmxt_unpackhul helper_iwmmxt_unpackhul_riscv64 +#define helper_iwmmxt_unpackhuw helper_iwmmxt_unpackhuw_riscv64 +#define helper_iwmmxt_unpackhw helper_iwmmxt_unpackhw_riscv64 +#define helper_iwmmxt_unpacklb helper_iwmmxt_unpacklb_riscv64 +#define helper_iwmmxt_unpackll helper_iwmmxt_unpackll_riscv64 +#define helper_iwmmxt_unpacklsb helper_iwmmxt_unpacklsb_riscv64 +#define helper_iwmmxt_unpacklsl helper_iwmmxt_unpacklsl_riscv64 +#define helper_iwmmxt_unpacklsw helper_iwmmxt_unpacklsw_riscv64 +#define helper_iwmmxt_unpacklub helper_iwmmxt_unpacklub_riscv64 +#define helper_iwmmxt_unpacklul helper_iwmmxt_unpacklul_riscv64 +#define helper_iwmmxt_unpackluw helper_iwmmxt_unpackluw_riscv64 +#define helper_iwmmxt_unpacklw helper_iwmmxt_unpacklw_riscv64 +#define helper_ldb_cmmu helper_ldb_cmmu_riscv64 +#define helper_ldb_mmu helper_ldb_mmu_riscv64 +#define helper_ldl_cmmu helper_ldl_cmmu_riscv64 +#define helper_ldl_mmu helper_ldl_mmu_riscv64 +#define helper_ldq_cmmu helper_ldq_cmmu_riscv64 +#define helper_ldq_mmu helper_ldq_mmu_riscv64 +#define helper_ldw_cmmu helper_ldw_cmmu_riscv64 +#define helper_ldw_mmu helper_ldw_mmu_riscv64 +#define helper_le_ldl_cmmu helper_le_ldl_cmmu_riscv64 +#define helper_le_ldq_cmmu helper_le_ldq_cmmu_riscv64 +#define helper_le_ldq_mmu helper_le_ldq_mmu_riscv64 +#define helper_le_ldsl_mmu helper_le_ldsl_mmu_riscv64 +#define helper_le_ldsw_mmu helper_le_ldsw_mmu_riscv64 +#define helper_le_ldul_mmu helper_le_ldul_mmu_riscv64 +#define helper_le_lduw_mmu helper_le_lduw_mmu_riscv64 +#define helper_le_ldw_cmmu helper_le_ldw_cmmu_riscv64 +#define helper_le_stl_mmu helper_le_stl_mmu_riscv64 +#define helper_le_stq_mmu helper_le_stq_mmu_riscv64 +#define helper_le_stw_mmu helper_le_stw_mmu_riscv64 +#define helper_lookup_tb_ptr helper_lookup_tb_ptr_riscv64 +#define helper_mulsh_i32 helper_mulsh_i32_riscv64 +#define helper_mulsh_i64 helper_mulsh_i64_riscv64 +#define helper_muluh_i32 helper_muluh_i32_riscv64 +#define helper_muluh_i64 helper_muluh_i64_riscv64 +#define helper_mrs_banked helper_mrs_banked_riscv64 +#define helper_msa_ld_b helper_msa_ld_b_riscv64 +#define helper_msa_ld_d helper_msa_ld_d_riscv64 +#define helper_msa_ld_h helper_msa_ld_h_riscv64 +#define helper_msa_ld_w helper_msa_ld_w_riscv64 +#define helper_msa_st_b helper_msa_st_b_riscv64 +#define helper_msa_st_d helper_msa_st_d_riscv64 +#define helper_msa_st_h helper_msa_st_h_riscv64 +#define helper_msa_st_w helper_msa_st_w_riscv64 +#define helper_msr_banked helper_msr_banked_riscv64 +#define helper_msr_i_pstate helper_msr_i_pstate_riscv64 +#define helper_neon_abd_f32 helper_neon_abd_f32_riscv64 +#define helper_neon_abd_s16 helper_neon_abd_s16_riscv64 +#define helper_neon_abd_s32 helper_neon_abd_s32_riscv64 +#define helper_neon_abd_s8 helper_neon_abd_s8_riscv64 +#define helper_neon_abd_u16 helper_neon_abd_u16_riscv64 +#define helper_neon_abd_u32 helper_neon_abd_u32_riscv64 +#define helper_neon_abd_u8 helper_neon_abd_u8_riscv64 +#define helper_neon_abdl_s16 helper_neon_abdl_s16_riscv64 +#define helper_neon_abdl_s32 helper_neon_abdl_s32_riscv64 +#define helper_neon_abdl_s64 helper_neon_abdl_s64_riscv64 +#define helper_neon_abdl_u16 helper_neon_abdl_u16_riscv64 +#define helper_neon_abdl_u32 helper_neon_abdl_u32_riscv64 +#define helper_neon_abdl_u64 helper_neon_abdl_u64_riscv64 +#define helper_neon_abs_s16 helper_neon_abs_s16_riscv64 +#define helper_neon_abs_s8 helper_neon_abs_s8_riscv64 +#define helper_neon_acge_f32 helper_neon_acge_f32_riscv64 +#define helper_neon_acge_f64 helper_neon_acge_f64_riscv64 +#define helper_neon_acgt_f32 helper_neon_acgt_f32_riscv64 +#define helper_neon_acgt_f64 helper_neon_acgt_f64_riscv64 +#define helper_neon_add_u16 helper_neon_add_u16_riscv64 +#define helper_neon_add_u8 helper_neon_add_u8_riscv64 +#define helper_neon_addl_saturate_s32 helper_neon_addl_saturate_s32_riscv64 +#define helper_neon_addl_saturate_s64 helper_neon_addl_saturate_s64_riscv64 +#define helper_neon_addl_u16 helper_neon_addl_u16_riscv64 +#define helper_neon_addl_u32 helper_neon_addl_u32_riscv64 +#define helper_neon_ceq_f32 helper_neon_ceq_f32_riscv64 +#define helper_neon_ceq_u16 helper_neon_ceq_u16_riscv64 +#define helper_neon_ceq_u32 helper_neon_ceq_u32_riscv64 +#define helper_neon_ceq_u8 helper_neon_ceq_u8_riscv64 +#define helper_neon_cge_f32 helper_neon_cge_f32_riscv64 +#define helper_neon_cge_s16 helper_neon_cge_s16_riscv64 +#define helper_neon_cge_s32 helper_neon_cge_s32_riscv64 +#define helper_neon_cge_s8 helper_neon_cge_s8_riscv64 +#define helper_neon_cge_u16 helper_neon_cge_u16_riscv64 +#define helper_neon_cge_u32 helper_neon_cge_u32_riscv64 +#define helper_neon_cge_u8 helper_neon_cge_u8_riscv64 +#define helper_neon_cgt_f32 helper_neon_cgt_f32_riscv64 +#define helper_neon_cgt_s16 helper_neon_cgt_s16_riscv64 +#define helper_neon_cgt_s32 helper_neon_cgt_s32_riscv64 +#define helper_neon_cgt_s8 helper_neon_cgt_s8_riscv64 +#define helper_neon_cgt_u16 helper_neon_cgt_u16_riscv64 +#define helper_neon_cgt_u32 helper_neon_cgt_u32_riscv64 +#define helper_neon_cgt_u8 helper_neon_cgt_u8_riscv64 +#define helper_neon_cls_s16 helper_neon_cls_s16_riscv64 +#define helper_neon_cls_s32 helper_neon_cls_s32_riscv64 +#define helper_neon_cls_s8 helper_neon_cls_s8_riscv64 +#define helper_neon_clz_u16 helper_neon_clz_u16_riscv64 +#define helper_neon_clz_u8 helper_neon_clz_u8_riscv64 +#define helper_neon_cnt_u8 helper_neon_cnt_u8_riscv64 +#define helper_neon_fcvt_f16_to_f32 helper_neon_fcvt_f16_to_f32_riscv64 +#define helper_neon_fcvt_f32_to_f16 helper_neon_fcvt_f32_to_f16_riscv64 +#define helper_neon_hadd_s16 helper_neon_hadd_s16_riscv64 +#define helper_neon_hadd_s32 helper_neon_hadd_s32_riscv64 +#define helper_neon_hadd_s8 helper_neon_hadd_s8_riscv64 +#define helper_neon_hadd_u16 helper_neon_hadd_u16_riscv64 +#define helper_neon_hadd_u32 helper_neon_hadd_u32_riscv64 +#define helper_neon_hadd_u8 helper_neon_hadd_u8_riscv64 +#define helper_neon_hsub_s16 helper_neon_hsub_s16_riscv64 +#define helper_neon_hsub_s32 helper_neon_hsub_s32_riscv64 +#define helper_neon_hsub_s8 helper_neon_hsub_s8_riscv64 +#define helper_neon_hsub_u16 helper_neon_hsub_u16_riscv64 +#define helper_neon_hsub_u32 helper_neon_hsub_u32_riscv64 +#define helper_neon_hsub_u8 helper_neon_hsub_u8_riscv64 +#define helper_neon_max_s16 helper_neon_max_s16_riscv64 +#define helper_neon_max_s32 helper_neon_max_s32_riscv64 +#define helper_neon_max_s8 helper_neon_max_s8_riscv64 +#define helper_neon_max_u16 helper_neon_max_u16_riscv64 +#define helper_neon_max_u32 helper_neon_max_u32_riscv64 +#define helper_neon_max_u8 helper_neon_max_u8_riscv64 +#define helper_neon_min_s16 helper_neon_min_s16_riscv64 +#define helper_neon_min_s32 helper_neon_min_s32_riscv64 +#define helper_neon_min_s8 helper_neon_min_s8_riscv64 +#define helper_neon_min_u16 helper_neon_min_u16_riscv64 +#define helper_neon_min_u32 helper_neon_min_u32_riscv64 +#define helper_neon_min_u8 helper_neon_min_u8_riscv64 +#define helper_neon_mul_p8 helper_neon_mul_p8_riscv64 +#define helper_neon_mul_u16 helper_neon_mul_u16_riscv64 +#define helper_neon_mul_u8 helper_neon_mul_u8_riscv64 +#define helper_neon_mull_p8 helper_neon_mull_p8_riscv64 +#define helper_neon_mull_s16 helper_neon_mull_s16_riscv64 +#define helper_neon_mull_s8 helper_neon_mull_s8_riscv64 +#define helper_neon_mull_u16 helper_neon_mull_u16_riscv64 +#define helper_neon_mull_u8 helper_neon_mull_u8_riscv64 +#define helper_neon_narrow_high_u16 helper_neon_narrow_high_u16_riscv64 +#define helper_neon_narrow_high_u8 helper_neon_narrow_high_u8_riscv64 +#define helper_neon_narrow_round_high_u16 helper_neon_narrow_round_high_u16_riscv64 +#define helper_neon_narrow_round_high_u8 helper_neon_narrow_round_high_u8_riscv64 +#define helper_neon_narrow_sat_s16 helper_neon_narrow_sat_s16_riscv64 +#define helper_neon_narrow_sat_s32 helper_neon_narrow_sat_s32_riscv64 +#define helper_neon_narrow_sat_s8 helper_neon_narrow_sat_s8_riscv64 +#define helper_neon_narrow_sat_u16 helper_neon_narrow_sat_u16_riscv64 +#define helper_neon_narrow_sat_u32 helper_neon_narrow_sat_u32_riscv64 +#define helper_neon_narrow_sat_u8 helper_neon_narrow_sat_u8_riscv64 +#define helper_neon_narrow_u16 helper_neon_narrow_u16_riscv64 +#define helper_neon_narrow_u8 helper_neon_narrow_u8_riscv64 +#define helper_neon_negl_u16 helper_neon_negl_u16_riscv64 +#define helper_neon_negl_u32 helper_neon_negl_u32_riscv64 +#define helper_neon_padd_u16 helper_neon_padd_u16_riscv64 +#define helper_neon_padd_u8 helper_neon_padd_u8_riscv64 +#define helper_neon_paddl_u16 helper_neon_paddl_u16_riscv64 +#define helper_neon_paddl_u32 helper_neon_paddl_u32_riscv64 +#define helper_neon_pmax_s16 helper_neon_pmax_s16_riscv64 +#define helper_neon_pmax_s8 helper_neon_pmax_s8_riscv64 +#define helper_neon_pmax_u16 helper_neon_pmax_u16_riscv64 +#define helper_neon_pmax_u8 helper_neon_pmax_u8_riscv64 +#define helper_neon_pmin_s16 helper_neon_pmin_s16_riscv64 +#define helper_neon_pmin_s8 helper_neon_pmin_s8_riscv64 +#define helper_neon_pmin_u16 helper_neon_pmin_u16_riscv64 +#define helper_neon_pmin_u8 helper_neon_pmin_u8_riscv64 +#define helper_neon_pmull_64_hi helper_neon_pmull_64_hi_riscv64 +#define helper_neon_pmull_64_lo helper_neon_pmull_64_lo_riscv64 +#define helper_neon_qabs_s16 helper_neon_qabs_s16_riscv64 +#define helper_neon_qabs_s32 helper_neon_qabs_s32_riscv64 +#define helper_neon_qabs_s64 helper_neon_qabs_s64_riscv64 +#define helper_neon_qabs_s8 helper_neon_qabs_s8_riscv64 +#define helper_neon_qadd_s16 helper_neon_qadd_s16_riscv64 +#define helper_neon_qadd_s32 helper_neon_qadd_s32_riscv64 +#define helper_neon_qadd_s64 helper_neon_qadd_s64_riscv64 +#define helper_neon_qadd_s8 helper_neon_qadd_s8_riscv64 +#define helper_neon_qadd_u16 helper_neon_qadd_u16_riscv64 +#define helper_neon_qadd_u32 helper_neon_qadd_u32_riscv64 +#define helper_neon_qadd_u64 helper_neon_qadd_u64_riscv64 +#define helper_neon_qadd_u8 helper_neon_qadd_u8_riscv64 +#define helper_neon_qdmulh_s16 helper_neon_qdmulh_s16_riscv64 +#define helper_neon_qdmulh_s32 helper_neon_qdmulh_s32_riscv64 +#define helper_neon_qneg_s16 helper_neon_qneg_s16_riscv64 +#define helper_neon_qneg_s32 helper_neon_qneg_s32_riscv64 +#define helper_neon_qneg_s64 helper_neon_qneg_s64_riscv64 +#define helper_neon_qneg_s8 helper_neon_qneg_s8_riscv64 +#define helper_neon_qrdmlah_s16 helper_neon_qrdmlah_s16_riscv64 +#define helper_neon_qrdmlah_s32 helper_neon_qrdmlah_s32_riscv64 +#define helper_neon_qrdmlsh_s16 helper_neon_qrdmlsh_s16_riscv64 +#define helper_neon_qrdmlsh_s32 helper_neon_qrdmlsh_s32_riscv64 +#define helper_neon_qrdmulh_s16 helper_neon_qrdmulh_s16_riscv64 +#define helper_neon_qrdmulh_s32 helper_neon_qrdmulh_s32_riscv64 +#define helper_neon_qrshl_s16 helper_neon_qrshl_s16_riscv64 +#define helper_neon_qrshl_s32 helper_neon_qrshl_s32_riscv64 +#define helper_neon_qrshl_s64 helper_neon_qrshl_s64_riscv64 +#define helper_neon_qrshl_s8 helper_neon_qrshl_s8_riscv64 +#define helper_neon_qrshl_u16 helper_neon_qrshl_u16_riscv64 +#define helper_neon_qrshl_u32 helper_neon_qrshl_u32_riscv64 +#define helper_neon_qrshl_u64 helper_neon_qrshl_u64_riscv64 +#define helper_neon_qrshl_u8 helper_neon_qrshl_u8_riscv64 +#define helper_neon_qshl_s16 helper_neon_qshl_s16_riscv64 +#define helper_neon_qshl_s32 helper_neon_qshl_s32_riscv64 +#define helper_neon_qshl_s64 helper_neon_qshl_s64_riscv64 +#define helper_neon_qshl_s8 helper_neon_qshl_s8_riscv64 +#define helper_neon_qshl_u16 helper_neon_qshl_u16_riscv64 +#define helper_neon_qshl_u32 helper_neon_qshl_u32_riscv64 +#define helper_neon_qshl_u64 helper_neon_qshl_u64_riscv64 +#define helper_neon_qshl_u8 helper_neon_qshl_u8_riscv64 +#define helper_neon_qshlu_s16 helper_neon_qshlu_s16_riscv64 +#define helper_neon_qshlu_s32 helper_neon_qshlu_s32_riscv64 +#define helper_neon_qshlu_s64 helper_neon_qshlu_s64_riscv64 +#define helper_neon_qshlu_s8 helper_neon_qshlu_s8_riscv64 +#define helper_neon_qsub_s16 helper_neon_qsub_s16_riscv64 +#define helper_neon_qsub_s32 helper_neon_qsub_s32_riscv64 +#define helper_neon_qsub_s64 helper_neon_qsub_s64_riscv64 +#define helper_neon_qsub_s8 helper_neon_qsub_s8_riscv64 +#define helper_neon_qsub_u16 helper_neon_qsub_u16_riscv64 +#define helper_neon_qsub_u32 helper_neon_qsub_u32_riscv64 +#define helper_neon_qsub_u64 helper_neon_qsub_u64_riscv64 +#define helper_neon_qsub_u8 helper_neon_qsub_u8_riscv64 +#define helper_neon_qunzip16 helper_neon_qunzip16_riscv64 +#define helper_neon_qunzip32 helper_neon_qunzip32_riscv64 +#define helper_neon_qunzip8 helper_neon_qunzip8_riscv64 +#define helper_neon_qzip16 helper_neon_qzip16_riscv64 +#define helper_neon_qzip32 helper_neon_qzip32_riscv64 +#define helper_neon_qzip8 helper_neon_qzip8_riscv64 +#define helper_neon_rbit_u8 helper_neon_rbit_u8_riscv64 +#define helper_neon_rhadd_s16 helper_neon_rhadd_s16_riscv64 +#define helper_neon_rhadd_s32 helper_neon_rhadd_s32_riscv64 +#define helper_neon_rhadd_s8 helper_neon_rhadd_s8_riscv64 +#define helper_neon_rhadd_u16 helper_neon_rhadd_u16_riscv64 +#define helper_neon_rhadd_u32 helper_neon_rhadd_u32_riscv64 +#define helper_neon_rhadd_u8 helper_neon_rhadd_u8_riscv64 +#define helper_neon_rshl_s16 helper_neon_rshl_s16_riscv64 +#define helper_neon_rshl_s32 helper_neon_rshl_s32_riscv64 +#define helper_neon_rshl_s64 helper_neon_rshl_s64_riscv64 +#define helper_neon_rshl_s8 helper_neon_rshl_s8_riscv64 +#define helper_neon_rshl_u16 helper_neon_rshl_u16_riscv64 +#define helper_neon_rshl_u32 helper_neon_rshl_u32_riscv64 +#define helper_neon_rshl_u64 helper_neon_rshl_u64_riscv64 +#define helper_neon_rshl_u8 helper_neon_rshl_u8_riscv64 +#define helper_neon_shl_s16 helper_neon_shl_s16_riscv64 +#define helper_neon_shl_s32 helper_neon_shl_s32_riscv64 +#define helper_neon_shl_s64 helper_neon_shl_s64_riscv64 +#define helper_neon_shl_s8 helper_neon_shl_s8_riscv64 +#define helper_neon_shl_u16 helper_neon_shl_u16_riscv64 +#define helper_neon_shl_u32 helper_neon_shl_u32_riscv64 +#define helper_neon_shl_u64 helper_neon_shl_u64_riscv64 +#define helper_neon_shl_u8 helper_neon_shl_u8_riscv64 +#define helper_neon_sqadd_u16 helper_neon_sqadd_u16_riscv64 +#define helper_neon_sqadd_u32 helper_neon_sqadd_u32_riscv64 +#define helper_neon_sqadd_u64 helper_neon_sqadd_u64_riscv64 +#define helper_neon_sqadd_u8 helper_neon_sqadd_u8_riscv64 +#define helper_neon_sub_u16 helper_neon_sub_u16_riscv64 +#define helper_neon_sub_u8 helper_neon_sub_u8_riscv64 +#define helper_neon_subl_u16 helper_neon_subl_u16_riscv64 +#define helper_neon_subl_u32 helper_neon_subl_u32_riscv64 +#define helper_neon_tbl helper_neon_tbl_riscv64 +#define helper_neon_tst_u16 helper_neon_tst_u16_riscv64 +#define helper_neon_tst_u32 helper_neon_tst_u32_riscv64 +#define helper_neon_tst_u8 helper_neon_tst_u8_riscv64 +#define helper_neon_unarrow_sat16 helper_neon_unarrow_sat16_riscv64 +#define helper_neon_unarrow_sat32 helper_neon_unarrow_sat32_riscv64 +#define helper_neon_unarrow_sat8 helper_neon_unarrow_sat8_riscv64 +#define helper_neon_unzip16 helper_neon_unzip16_riscv64 +#define helper_neon_unzip8 helper_neon_unzip8_riscv64 +#define helper_neon_uqadd_s16 helper_neon_uqadd_s16_riscv64 +#define helper_neon_uqadd_s32 helper_neon_uqadd_s32_riscv64 +#define helper_neon_uqadd_s64 helper_neon_uqadd_s64_riscv64 +#define helper_neon_uqadd_s8 helper_neon_uqadd_s8_riscv64 +#define helper_neon_widen_s16 helper_neon_widen_s16_riscv64 +#define helper_neon_widen_s8 helper_neon_widen_s8_riscv64 +#define helper_neon_widen_u16 helper_neon_widen_u16_riscv64 +#define helper_neon_widen_u8 helper_neon_widen_u8_riscv64 +#define helper_neon_zip16 helper_neon_zip16_riscv64 +#define helper_neon_zip8 helper_neon_zip8_riscv64 +#define helper_power_down helper_power_down_riscv64 +#define helper_pre_hvc helper_pre_hvc_riscv64 +#define helper_pre_smc helper_pre_smc_riscv64 +#define helper_qadd16 helper_qadd16_riscv64 +#define helper_qadd8 helper_qadd8_riscv64 +#define helper_qaddsubx helper_qaddsubx_riscv64 +#define helper_qsub16 helper_qsub16_riscv64 +#define helper_qsub8 helper_qsub8_riscv64 +#define helper_qsubaddx helper_qsubaddx_riscv64 +#define helper_raise_exception helper_raise_exception_riscv64 +#define helper_rbit helper_rbit_riscv64 +#define helper_recpe_f16 helper_recpe_f16_riscv64 +#define helper_recpe_f32 helper_recpe_f32_riscv64 +#define helper_recpe_f64 helper_recpe_f64_riscv64 +#define helper_recpe_u32 helper_recpe_u32_riscv64 +#define helper_recps_f32 helper_recps_f32_riscv64 +#define helper_rem_i32 helper_rem_i32_riscv64 +#define helper_rem_i64 helper_rem_i64_riscv64 +#define helper_remu_i32 helper_remu_i32_riscv64 +#define helper_remu_i64 helper_remu_i64_riscv64 +#define helper_ret_ldb_cmmu helper_ret_ldb_cmmu_riscv64 +#define helper_ret_ldsb_mmu helper_ret_ldsb_mmu_riscv64 +#define helper_ret_ldub_mmu helper_ret_ldub_mmu_riscv64 +#define helper_ret_stb_mmu helper_ret_stb_mmu_riscv64 +#define helper_rintd helper_rintd_riscv64 +#define helper_rintd_exact helper_rintd_exact_riscv64 +#define helper_rints helper_rints_riscv64 +#define helper_rints_exact helper_rints_exact_riscv64 +#define helper_ror_cc helper_ror_cc_riscv64 +#define helper_rsqrte_f16 helper_rsqrte_f16_riscv64 +#define helper_rsqrte_f32 helper_rsqrte_f32_riscv64 +#define helper_rsqrte_f64 helper_rsqrte_f64_riscv64 +#define helper_rsqrte_u32 helper_rsqrte_u32_riscv64 +#define helper_rsqrts_f32 helper_rsqrts_f32_riscv64 +#define helper_sadd16 helper_sadd16_riscv64 +#define helper_sadd8 helper_sadd8_riscv64 +#define helper_saddsubx helper_saddsubx_riscv64 +#define helper_sar_cc helper_sar_cc_riscv64 +#define helper_sar_i32 helper_sar_i32_riscv64 +#define helper_sar_i64 helper_sar_i64_riscv64 +#define helper_sdiv helper_sdiv_riscv64 +#define helper_sel_flags helper_sel_flags_riscv64 +#define helper_set_cp_reg helper_set_cp_reg_riscv64 +#define helper_set_cp_reg64 helper_set_cp_reg64_riscv64 +#define helper_set_neon_rmode helper_set_neon_rmode_riscv64 +#define helper_set_r13_banked helper_set_r13_banked_riscv64 +#define helper_set_rmode helper_set_rmode_riscv64 +#define helper_set_user_reg helper_set_user_reg_riscv64 +#define helper_setend helper_setend_riscv64 +#define helper_shadd16 helper_shadd16_riscv64 +#define helper_shadd8 helper_shadd8_riscv64 +#define helper_shaddsubx helper_shaddsubx_riscv64 +#define helper_shl_cc helper_shl_cc_riscv64 +#define helper_shl_i64 helper_shl_i64_riscv64 +#define helper_shr_cc helper_shr_cc_riscv64 +#define helper_shr_i32 helper_shr_i32_riscv64 +#define helper_shr_i64 helper_shr_i64_riscv64 +#define helper_shsub16 helper_shsub16_riscv64 +#define helper_shsub8 helper_shsub8_riscv64 +#define helper_shsubaddx helper_shsubaddx_riscv64 +#define helper_ssat helper_ssat_riscv64 +#define helper_ssat16 helper_ssat16_riscv64 +#define helper_ssub16 helper_ssub16_riscv64 +#define helper_ssub8 helper_ssub8_riscv64 +#define helper_ssubaddx helper_ssubaddx_riscv64 +#define helper_stb_mmu helper_stb_mmu_riscv64 +#define helper_stl_mmu helper_stl_mmu_riscv64 +#define helper_stq_mmu helper_stq_mmu_riscv64 +#define helper_stw_mmu helper_stw_mmu_riscv64 +#define helper_sub_saturate helper_sub_saturate_riscv64 +#define helper_sub_usaturate helper_sub_usaturate_riscv64 +#define helper_sxtb16 helper_sxtb16_riscv64 +#define helper_uadd16 helper_uadd16_riscv64 +#define helper_uadd8 helper_uadd8_riscv64 +#define helper_uaddsubx helper_uaddsubx_riscv64 +#define helper_udiv helper_udiv_riscv64 +#define helper_uhadd16 helper_uhadd16_riscv64 +#define helper_uhadd8 helper_uhadd8_riscv64 +#define helper_uhaddsubx helper_uhaddsubx_riscv64 +#define helper_uhsub16 helper_uhsub16_riscv64 +#define helper_uhsub8 helper_uhsub8_riscv64 +#define helper_uhsubaddx helper_uhsubaddx_riscv64 +#define helper_uqadd16 helper_uqadd16_riscv64 +#define helper_uqadd8 helper_uqadd8_riscv64 +#define helper_uqaddsubx helper_uqaddsubx_riscv64 +#define helper_uqsub16 helper_uqsub16_riscv64 +#define helper_uqsub8 helper_uqsub8_riscv64 +#define helper_uqsubaddx helper_uqsubaddx_riscv64 +#define helper_usad8 helper_usad8_riscv64 +#define helper_usat helper_usat_riscv64 +#define helper_usat16 helper_usat16_riscv64 +#define helper_usub16 helper_usub16_riscv64 +#define helper_usub8 helper_usub8_riscv64 +#define helper_usubaddx helper_usubaddx_riscv64 +#define helper_uxtb16 helper_uxtb16_riscv64 +#define helper_v7m_blxns helper_v7m_blxns_riscv64 +#define helper_v7m_bxns helper_v7m_bxns_riscv64 +#define helper_v7m_mrs helper_v7m_mrs_riscv64 +#define helper_v7m_msr helper_v7m_msr_riscv64 +#define helper_v7m_tt helper_v7m_tt_riscv64 +#define helper_vfp_absd helper_vfp_absd_riscv64 +#define helper_vfp_abss helper_vfp_abss_riscv64 +#define helper_vfp_addd helper_vfp_addd_riscv64 +#define helper_vfp_adds helper_vfp_adds_riscv64 +#define helper_vfp_cmpd helper_vfp_cmpd_riscv64 +#define helper_vfp_cmph_a64 helper_vfp_cmph_a64_riscv64 +#define helper_vfp_cmped helper_vfp_cmped_riscv64 +#define helper_vfp_cmpeh_a64 helper_vfp_cmpeh_a64_riscv64 +#define helper_vfp_cmpes helper_vfp_cmpes_riscv64 +#define helper_vfp_cmps helper_vfp_cmps_riscv64 +#define helper_vfp_divd helper_vfp_divd_riscv64 +#define helper_vfp_divs helper_vfp_divs_riscv64 +#define helper_vfp_fcvt_f16_to_f32 helper_vfp_fcvt_f16_to_f32_riscv64 +#define helper_vfp_fcvt_f16_to_f64 helper_vfp_fcvt_f16_to_f64_riscv64 +#define helper_vfp_fcvt_f32_to_f16 helper_vfp_fcvt_f32_to_f16_riscv64 +#define helper_vfp_fcvt_f64_to_f16 helper_vfp_fcvt_f64_to_f16_riscv64 +#define helper_vfp_fcvtds helper_vfp_fcvtds_riscv64 +#define helper_vfp_fcvtsd helper_vfp_fcvtsd_riscv64 +#define helper_vfp_get_fpscr helper_vfp_get_fpscr_riscv64 +#define helper_vfp_maxd helper_vfp_maxd_riscv64 +#define helper_vfp_maxnumd helper_vfp_maxnumd_riscv64 +#define helper_vfp_maxnums helper_vfp_maxnums_riscv64 +#define helper_vfp_maxs helper_vfp_maxs_riscv64 +#define helper_vfp_mind helper_vfp_mind_riscv64 +#define helper_vfp_minnumd helper_vfp_minnumd_riscv64 +#define helper_vfp_minnums helper_vfp_minnums_riscv64 +#define helper_vfp_mins helper_vfp_mins_riscv64 +#define helper_vfp_muladdd helper_vfp_muladdd_riscv64 +#define helper_vfp_muladds helper_vfp_muladds_riscv64 +#define helper_vfp_muld helper_vfp_muld_riscv64 +#define helper_vfp_muls helper_vfp_muls_riscv64 +#define helper_vfp_negd helper_vfp_negd_riscv64 +#define helper_vfp_negs helper_vfp_negs_riscv64 +#define helper_vfp_set_fpscr helper_vfp_set_fpscr_riscv64 +#define helper_vfp_shtod helper_vfp_shtod_riscv64 +#define helper_vfp_shtos helper_vfp_shtos_riscv64 +#define helper_vfp_sitod helper_vfp_sitod_riscv64 +#define helper_vfp_sitoh helper_vfp_sitoh_riscv64 +#define helper_vfp_sitos helper_vfp_sitos_riscv64 +#define helper_vfp_sltod helper_vfp_sltod_riscv64 +#define helper_vfp_sltoh helper_vfp_sltoh_riscv64 +#define helper_vfp_sltos helper_vfp_sltos_riscv64 +#define helper_vfp_sqrtd helper_vfp_sqrtd_riscv64 +#define helper_vfp_sqrts helper_vfp_sqrts_riscv64 +#define helper_vfp_sqtod helper_vfp_sqtod_riscv64 +#define helper_vfp_sqtoh helper_vfp_sqtoh_riscv64 +#define helper_vfp_sqtos helper_vfp_sqtos_riscv64 +#define helper_vfp_subd helper_vfp_subd_riscv64 +#define helper_vfp_subs helper_vfp_subs_riscv64 +#define helper_vfp_toshd helper_vfp_toshd_riscv64 +#define helper_vfp_toshd_round_to_zero helper_vfp_toshd_round_to_zero_riscv64 +#define helper_vfp_toshh helper_vfp_toshh_riscv64 +#define helper_vfp_toshs helper_vfp_toshs_riscv64 +#define helper_vfp_toshs_round_to_zero helper_vfp_toshs_round_to_zero_riscv64 +#define helper_vfp_tosid helper_vfp_tosid_riscv64 +#define helper_vfp_tosih helper_vfp_tosih_riscv64 +#define helper_vfp_tosis helper_vfp_tosis_riscv64 +#define helper_vfp_tosizd helper_vfp_tosizd_riscv64 +#define helper_vfp_tosizh helper_vfp_tosizh_riscv64 +#define helper_vfp_tosizs helper_vfp_tosizs_riscv64 +#define helper_vfp_tosld helper_vfp_tosld_riscv64 +#define helper_vfp_tosld_round_to_zero helper_vfp_tosld_round_to_zero_riscv64 +#define helper_vfp_toslh helper_vfp_toslh_riscv64 +#define helper_vfp_tosls helper_vfp_tosls_riscv64 +#define helper_vfp_tosls_round_to_zero helper_vfp_tosls_round_to_zero_riscv64 +#define helper_vfp_tosqd helper_vfp_tosqd_riscv64 +#define helper_vfp_tosqh helper_vfp_tosqh_riscv64 +#define helper_vfp_tosqs helper_vfp_tosqs_riscv64 +#define helper_vfp_touhd helper_vfp_touhd_riscv64 +#define helper_vfp_touhd_round_to_zero helper_vfp_touhd_round_to_zero_riscv64 +#define helper_vfp_touhh helper_vfp_touhh_riscv64 +#define helper_vfp_touhs helper_vfp_touhs_riscv64 +#define helper_vfp_touhs_round_to_zero helper_vfp_touhs_round_to_zero_riscv64 +#define helper_vfp_touid helper_vfp_touid_riscv64 +#define helper_vfp_touih helper_vfp_touih_riscv64 +#define helper_vfp_touis helper_vfp_touis_riscv64 +#define helper_vfp_touizd helper_vfp_touizd_riscv64 +#define helper_vfp_touizh helper_vfp_touizh_riscv64 +#define helper_vfp_touizs helper_vfp_touizs_riscv64 +#define helper_vfp_tould helper_vfp_tould_riscv64 +#define helper_vfp_tould_round_to_zero helper_vfp_tould_round_to_zero_riscv64 +#define helper_vfp_toulh helper_vfp_toulh_riscv64 +#define helper_vfp_touls helper_vfp_touls_riscv64 +#define helper_vfp_touls_round_to_zero helper_vfp_touls_round_to_zero_riscv64 +#define helper_vfp_touqd helper_vfp_touqd_riscv64 +#define helper_vfp_touqh helper_vfp_touqh_riscv64 +#define helper_vfp_touqs helper_vfp_touqs_riscv64 +#define helper_vfp_uhtod helper_vfp_uhtod_riscv64 +#define helper_vfp_uhtos helper_vfp_uhtos_riscv64 +#define helper_vfp_uitod helper_vfp_uitod_riscv64 +#define helper_vfp_uitoh helper_vfp_uitoh_riscv64 +#define helper_vfp_uitos helper_vfp_uitos_riscv64 +#define helper_vfp_ultod helper_vfp_ultod_riscv64 +#define helper_vfp_ultoh helper_vfp_ultoh_riscv64 +#define helper_vfp_ultos helper_vfp_ultos_riscv64 +#define helper_vfp_uqtod helper_vfp_uqtod_riscv64 +#define helper_vfp_uqtoh helper_vfp_uqtoh_riscv64 +#define helper_vfp_uqtos helper_vfp_uqtos_riscv64 +#define helper_wfe helper_wfe_riscv64 +#define helper_wfi helper_wfi_riscv64 +#define helper_yield helper_yield_riscv64 +#define hex2decimal hex2decimal_riscv64 +#define hw_breakpoint_update hw_breakpoint_update_riscv64 +#define hw_breakpoint_update_all hw_breakpoint_update_all_riscv64 +#define hw_watchpoint_update hw_watchpoint_update_riscv64 +#define hw_watchpoint_update_all hw_watchpoint_update_all_riscv64 +#define init_cpreg_list init_cpreg_list_riscv64 +#define init_lists init_lists_riscv64 +#define input_type_enum input_type_enum_riscv64 +#define int128_2_64 int128_2_64_riscv64 +#define int128_add int128_add_riscv64 +#define int128_addto int128_addto_riscv64 +#define int128_and int128_and_riscv64 +#define int128_eq int128_eq_riscv64 +#define int128_ge int128_ge_riscv64 +#define int128_get64 int128_get64_riscv64 +#define int128_gt int128_gt_riscv64 +#define int128_le int128_le_riscv64 +#define int128_lt int128_lt_riscv64 +#define int128_make64 int128_make64_riscv64 +#define int128_max int128_max_riscv64 +#define int128_min int128_min_riscv64 +#define int128_ne int128_ne_riscv64 +#define int128_neg int128_neg_riscv64 +#define int128_nz int128_nz_riscv64 +#define int128_rshift int128_rshift_riscv64 +#define int128_sub int128_sub_riscv64 +#define int128_subfrom int128_subfrom_riscv64 +#define int128_zero int128_zero_riscv64 +#define int16_to_float16 int16_to_float16_riscv64 +#define int16_to_float16_scalbn int16_to_float16_scalbn_riscv64 +#define int16_to_float32 int16_to_float32_riscv64 +#define int16_to_float32_scalbn int16_to_float32_scalbn_riscv64 +#define int16_to_float64 int16_to_float64_riscv64 +#define int16_to_float64_scalbn int16_to_float64_scalbn_riscv64 +#define int32_to_float128 int32_to_float128_riscv64 +#define int32_to_float16 int32_to_float16_riscv64 +#define int32_to_float16_scalbn int32_to_float16_scalbn_riscv64 +#define int32_to_float32 int32_to_float32_riscv64 +#define int32_to_float32_scalbn int32_to_float32_scalbn_riscv64 +#define int32_to_float64 int32_to_float64_riscv64 +#define int32_to_float64_scalbn int32_to_float64_scalbn_riscv64 +#define int32_to_floatx80 int32_to_floatx80_riscv64 +#define int64_to_float128 int64_to_float128_riscv64 +#define int64_to_float16 int64_to_float16_riscv64 +#define int64_to_float16_scalbn int64_to_float16_scalbn_riscv64 +#define int64_to_float32 int64_to_float32_riscv64 +#define int64_to_float32_scalbn int64_to_float32_scalbn_riscv64 +#define int64_to_float64 int64_to_float64_riscv64 +#define int64_to_float64_scalbn int64_to_float64_scalbn_riscv64 +#define int64_to_floatx80 int64_to_floatx80_riscv64 +#define invalidate_and_set_dirty invalidate_and_set_dirty_riscv64 +#define invalidate_page_bitmap invalidate_page_bitmap_riscv64 +#define io_readb io_readb_riscv64 +#define io_readl io_readl_riscv64 +#define io_readq io_readq_riscv64 +#define io_readw io_readw_riscv64 +#define io_writeb io_writeb_riscv64 +#define io_writel io_writel_riscv64 +#define io_writeq io_writeq_riscv64 +#define io_writew io_writew_riscv64 +#define iotlb_to_section iotlb_to_section_riscv64 +#define is_a64 is_a64_riscv64 +#define is_help_option is_help_option_riscv64 +#define is_valid_option_list is_valid_option_list_riscv64 +#define isr_read isr_read_riscv64 +#define iwmmxt_load_creg iwmmxt_load_creg_riscv64 +#define iwmmxt_load_reg iwmmxt_load_reg_riscv64 +#define iwmmxt_store_creg iwmmxt_store_creg_riscv64 +#define iwmmxt_store_reg iwmmxt_store_reg_riscv64 +#define kvm_to_cpreg_id kvm_to_cpreg_id_riscv64 +#define last_ram_offset last_ram_offset_riscv64 +#define ldl_be_p ldl_be_p_riscv64 +#define ldl_be_phys ldl_be_phys_riscv64 +#define ldl_be_phys_cached ldl_be_phys_cached_riscv64 +#define ldl_he_p ldl_he_p_riscv64 +#define ldl_le_p ldl_le_p_riscv64 +#define ldl_le_phys ldl_le_phys_riscv64 +#define ldl_le_phys_cached ldl_le_phys_cached_riscv64 +#define ldl_phys ldl_phys_riscv64 +#define ldl_phys_cached ldl_phys_cached_riscv64 +#define ldl_phys_internal ldl_phys_internal_riscv64 +#define ldq_be_p ldq_be_p_riscv64 +#define ldq_be_phys ldq_be_phys_riscv64 +#define ldq_be_phys_cached ldq_be_phys_cached_riscv64 +#define ldq_he_p ldq_he_p_riscv64 +#define ldq_le_p ldq_le_p_riscv64 +#define ldq_le_phys ldq_le_phys_riscv64 +#define ldq_le_phys_cached ldq_le_phys_cached_riscv64 +#define ldq_phys ldq_phys_riscv64 +#define ldq_phys_cached ldq_phys_cached_riscv64 +#define ldq_phys_internal ldq_phys_internal_riscv64 +#define ldst_name ldst_name_riscv64 +#define ldub_p ldub_p_riscv64 +#define ldub_phys ldub_phys_riscv64 +#define ldub_phys_cached ldub_phys_cached_riscv64 +#define lduw_be_p lduw_be_p_riscv64 +#define lduw_be_phys lduw_be_phys_riscv64 +#define lduw_be_phys_cached lduw_be_phys_cached_riscv64 +#define lduw_he_p lduw_he_p_riscv64 +#define lduw_le_p lduw_le_p_riscv64 +#define lduw_le_phys lduw_le_phys_riscv64 +#define lduw_le_phys_cached lduw_le_phys_cached_riscv64 +#define lduw_phys lduw_phys_riscv64 +#define lduw_phys_cached lduw_phys_cached_riscv64 +#define lduw_phys_internal lduw_phys_internal_riscv64 +#define le128 le128_riscv64 +#define linked_bp_matches linked_bp_matches_riscv64 +#define listener_add_address_space listener_add_address_space_riscv64 +#define load_cpu_offset load_cpu_offset_riscv64 +#define load_reg load_reg_riscv64 +#define load_reg_var load_reg_var_riscv64 +#define log_cpu_state log_cpu_state_riscv64 +#define lpae_cp_reginfo lpae_cp_reginfo_riscv64 +#define lt128 lt128_riscv64 +#define machine_class_init machine_class_init_riscv64 +#define machine_finalize machine_finalize_riscv64 +#define machine_info machine_info_riscv64 +#define machine_initfn machine_initfn_riscv64 +#define machine_register_types machine_register_types_riscv64 +#define machvirt_init machvirt_init_riscv64 +#define machvirt_machine_init machvirt_machine_init_riscv64 +#define maj maj_riscv64 +#define mapping_conflict mapping_conflict_riscv64 +#define mapping_contiguous mapping_contiguous_riscv64 +#define mapping_have_same_region mapping_have_same_region_riscv64 +#define mapping_merge mapping_merge_riscv64 +#define memory_access_size memory_access_size_riscv64 +#define memory_free memory_free_riscv64 +#define memory_init memory_init_riscv64 +#define memory_listener_match memory_listener_match_riscv64 +#define memory_listener_register memory_listener_register_riscv64 +#define memory_listener_unregister memory_listener_unregister_riscv64 +#define memory_map memory_map_riscv64 +#define memory_map_init memory_map_init_riscv64 +#define memory_map_ptr memory_map_ptr_riscv64 +#define memory_mapping_filter memory_mapping_filter_riscv64 +#define memory_mapping_list_add_mapping_sorted memory_mapping_list_add_mapping_sorted_riscv64 +#define memory_mapping_list_add_merge_sorted memory_mapping_list_add_merge_sorted_riscv64 +#define memory_mapping_list_free memory_mapping_list_free_riscv64 +#define memory_mapping_list_init memory_mapping_list_init_riscv64 +#define memory_region_access_valid memory_region_access_valid_riscv64 +#define memory_region_add_subregion memory_region_add_subregion_riscv64 +#define memory_region_add_subregion_common memory_region_add_subregion_common_riscv64 +#define memory_region_add_subregion_overlap memory_region_add_subregion_overlap_riscv64 +#define memory_region_big_endian memory_region_big_endian_riscv64 +#define memory_region_clear_global_locking memory_region_clear_global_locking_riscv64 +#define memory_region_clear_pending memory_region_clear_pending_riscv64 +#define memory_region_del_subregion memory_region_del_subregion_riscv64 +#define memory_region_destructor_alias memory_region_destructor_alias_riscv64 +#define memory_region_destructor_none memory_region_destructor_none_riscv64 +#define memory_region_destructor_ram memory_region_destructor_ram_riscv64 +#define memory_region_destructor_ram_from_ptr memory_region_destructor_ram_from_ptr_riscv64 +#define memory_region_dispatch_read memory_region_dispatch_read_riscv64 +#define memory_region_dispatch_read1 memory_region_dispatch_read1_riscv64 +#define memory_region_dispatch_write memory_region_dispatch_write_riscv64 +#define memory_region_escape_name memory_region_escape_name_riscv64 +#define memory_region_finalize memory_region_finalize_riscv64 +#define memory_region_find memory_region_find_riscv64 +#define memory_region_from_host memory_region_from_host_riscv64 +#define memory_region_get_addr memory_region_get_addr_riscv64 +#define memory_region_get_alignment memory_region_get_alignment_riscv64 +#define memory_region_get_container memory_region_get_container_riscv64 +#define memory_region_get_dirty_log_mask memory_region_get_dirty_log_mask_riscv64 +#define memory_region_get_fd memory_region_get_fd_riscv64 +#define memory_region_get_may_overlap memory_region_get_may_overlap_riscv64 +#define memory_region_get_priority memory_region_get_priority_riscv64 +#define memory_region_get_ram_addr memory_region_get_ram_addr_riscv64 +#define memory_region_get_ram_ptr memory_region_get_ram_ptr_riscv64 +#define memory_region_get_size memory_region_get_size_riscv64 +#define memory_region_info memory_region_info_riscv64 +#define memory_region_init memory_region_init_riscv64 +#define memory_region_init_alias memory_region_init_alias_riscv64 +#define memory_region_init_io memory_region_init_io_riscv64 +#define memory_region_init_ram_device_ptr memory_region_init_ram_device_ptr_riscv64 +#define memory_region_init_ram_nomigrate memory_region_init_ram_nomigrate_riscv64 +#define memory_region_init_ram_ptr memory_region_init_ram_ptr_riscv64 +#define memory_region_init_reservation memory_region_init_reservation_riscv64 +#define memory_region_init_resizeable_ram memory_region_init_resizeable_ram_riscv64 +#define memory_region_init_rom_nomigrate memory_region_init_rom_nomigrate_riscv64 +#define memory_region_initfn memory_region_initfn_riscv64 +#define memory_region_is_logging memory_region_is_logging_riscv64 +#define memory_region_is_mapped memory_region_is_mapped_riscv64 +#define memory_region_is_ram_device memory_region_is_ram_device_riscv64 +#define memory_region_is_unassigned memory_region_is_unassigned_riscv64 +#define memory_region_name memory_region_name_riscv64 +#define memory_region_need_escape memory_region_need_escape_riscv64 +#define memory_region_oldmmio_read_accessor memory_region_oldmmio_read_accessor_riscv64 +#define memory_region_oldmmio_write_accessor memory_region_oldmmio_write_accessor_riscv64 +#define memory_region_present memory_region_present_riscv64 +#define memory_region_read_accessor memory_region_read_accessor_riscv64 +#define memory_region_readd_subregion memory_region_readd_subregion_riscv64 +#define memory_region_ref memory_region_ref_riscv64 +#define memory_region_resolve_container memory_region_resolve_container_riscv64 +#define memory_region_rom_device_set_romd memory_region_rom_device_set_romd_riscv64 +#define memory_region_section_get_iotlb memory_region_section_get_iotlb_riscv64 +#define memory_region_set_address memory_region_set_address_riscv64 +#define memory_region_set_alias_offset memory_region_set_alias_offset_riscv64 +#define memory_region_set_enabled memory_region_set_enabled_riscv64 +#define memory_region_set_readonly memory_region_set_readonly_riscv64 +#define memory_region_set_size memory_region_set_size_riscv64 +#define memory_region_size memory_region_size_riscv64 +#define memory_region_to_address_space memory_region_to_address_space_riscv64 +#define memory_region_transaction_begin memory_region_transaction_begin_riscv64 +#define memory_region_transaction_commit memory_region_transaction_commit_riscv64 +#define memory_region_unref memory_region_unref_riscv64 +#define memory_region_update_container_subregions memory_region_update_container_subregions_riscv64 +#define memory_region_write_accessor memory_region_write_accessor_riscv64 +#define memory_region_wrong_endianness memory_region_wrong_endianness_riscv64 +#define memory_register_types memory_register_types_riscv64 +#define memory_try_enable_merging memory_try_enable_merging_riscv64 +#define memory_unmap memory_unmap_riscv64 +#define module_call_init module_call_init_riscv64 +#define module_load module_load_riscv64 +#define mpidr_cp_reginfo mpidr_cp_reginfo_riscv64 +#define mpidr_read mpidr_read_riscv64 +#define msr_mask msr_mask_riscv64 +#define mul128By64To192 mul128By64To192_riscv64 +#define mul128To256 mul128To256_riscv64 +#define mul64To128 mul64To128_riscv64 +#define muldiv64 muldiv64_riscv64 +#define neon_2rm_is_float_op neon_2rm_is_float_op_riscv64 +#define neon_2rm_sizes neon_2rm_sizes_riscv64 +#define neon_3r_sizes neon_3r_sizes_riscv64 +#define neon_get_scalar neon_get_scalar_riscv64 +#define neon_load_reg neon_load_reg_riscv64 +#define neon_load_reg64 neon_load_reg64_riscv64 +#define neon_load_scratch neon_load_scratch_riscv64 +#define neon_ls_element_type neon_ls_element_type_riscv64 +#define neon_reg_offset neon_reg_offset_riscv64 +#define neon_store_reg neon_store_reg_riscv64 +#define neon_store_reg64 neon_store_reg64_riscv64 +#define neon_store_scratch neon_store_scratch_riscv64 +#define new_ldst_label new_ldst_label_riscv64 +#define next_list next_list_riscv64 +#define normalizeFloat128Subnormal normalizeFloat128Subnormal_riscv64 +#define normalizeFloat16Subnormal normalizeFloat16Subnormal_riscv64 +#define normalizeFloat32Subnormal normalizeFloat32Subnormal_riscv64 +#define normalizeFloat64Subnormal normalizeFloat64Subnormal_riscv64 +#define normalizeFloatx80Subnormal normalizeFloatx80Subnormal_riscv64 +#define normalizeRoundAndPackFloat128 normalizeRoundAndPackFloat128_riscv64 +#define normalizeRoundAndPackFloat32 normalizeRoundAndPackFloat32_riscv64 +#define normalizeRoundAndPackFloat64 normalizeRoundAndPackFloat64_riscv64 +#define normalizeRoundAndPackFloatx80 normalizeRoundAndPackFloatx80_riscv64 +#define not_v6_cp_reginfo not_v6_cp_reginfo_riscv64 +#define not_v7_cp_reginfo not_v7_cp_reginfo_riscv64 +#define not_v8_cp_reginfo not_v8_cp_reginfo_riscv64 +#define object_child_foreach object_child_foreach_riscv64 +#define object_child_foreach_recursive object_child_foreach_recursive_riscv64 +#define object_class_foreach object_class_foreach_riscv64 +#define object_class_foreach_tramp object_class_foreach_tramp_riscv64 +#define object_class_get_list object_class_get_list_riscv64 +#define object_class_get_list_sorted object_class_get_list_sorted_riscv64 +#define object_class_get_list_tramp object_class_get_list_tramp_riscv64 +#define object_class_get_parent object_class_get_parent_riscv64 +#define object_deinit object_deinit_riscv64 +#define object_dynamic_cast object_dynamic_cast_riscv64 +#define object_finalize object_finalize_riscv64 +#define object_finalize_child_property object_finalize_child_property_riscv64 +#define object_get_child_property object_get_child_property_riscv64 +#define object_get_internal_root object_get_internal_root_riscv64 +#define object_get_link_property object_get_link_property_riscv64 +#define object_get_root object_get_root_riscv64 +#define object_init_with_type object_init_with_type_riscv64 +#define object_initialize_with_type object_initialize_with_type_riscv64 +#define object_instance_init object_instance_init_riscv64 +#define object_new_with_type object_new_with_type_riscv64 +#define object_post_init_with_type object_post_init_with_type_riscv64 +#define object_property_add_alias object_property_add_alias_riscv64 +#define object_property_add_link object_property_add_link_riscv64 +#define object_property_add_uint16_ptr object_property_add_uint16_ptr_riscv64 +#define object_property_add_uint32_ptr object_property_add_uint32_ptr_riscv64 +#define object_property_add_uint64_ptr object_property_add_uint64_ptr_riscv64 +#define object_property_add_uint8_ptr object_property_add_uint8_ptr_riscv64 +#define object_property_allow_set_link object_property_allow_set_link_riscv64 +#define object_property_del object_property_del_riscv64 +#define object_property_del_all object_property_del_all_riscv64 +#define object_property_find object_property_find_riscv64 +#define object_property_get object_property_get_riscv64 +#define object_property_get_bool object_property_get_bool_riscv64 +#define object_property_get_int object_property_get_int_riscv64 +#define object_property_get_link object_property_get_link_riscv64 +#define object_property_get_qobject object_property_get_qobject_riscv64 +#define object_property_get_str object_property_get_str_riscv64 +#define object_property_get_type object_property_get_type_riscv64 +#define object_property_is_child object_property_is_child_riscv64 +#define object_property_set object_property_set_riscv64 +#define object_property_set_description object_property_set_description_riscv64 +#define object_property_set_link object_property_set_link_riscv64 +#define object_property_set_qobject object_property_set_qobject_riscv64 +#define object_release_link_property object_release_link_property_riscv64 +#define object_resolve_abs_path object_resolve_abs_path_riscv64 +#define object_resolve_child_property object_resolve_child_property_riscv64 +#define object_resolve_link object_resolve_link_riscv64 +#define object_resolve_link_property object_resolve_link_property_riscv64 +#define object_resolve_partial_path object_resolve_partial_path_riscv64 +#define object_resolve_path object_resolve_path_riscv64 +#define object_resolve_path_component object_resolve_path_component_riscv64 +#define object_resolve_path_type object_resolve_path_type_riscv64 +#define object_set_link_property object_set_link_property_riscv64 +#define object_type_get_instance_size object_type_get_instance_size_riscv64 +#define omap_cachemaint_write omap_cachemaint_write_riscv64 +#define omap_cp_reginfo omap_cp_reginfo_riscv64 +#define omap_threadid_write omap_threadid_write_riscv64 +#define omap_ticonfig_write omap_ticonfig_write_riscv64 +#define omap_wfi_write omap_wfi_write_riscv64 +#define op_bits op_bits_riscv64 +#define op_to_mov op_to_mov_riscv64 +#define op_to_movi op_to_movi_riscv64 +#define open_modeflags open_modeflags_riscv64 +#define output_type_enum output_type_enum_riscv64 +#define packFloat128 packFloat128_riscv64 +#define packFloat16 packFloat16_riscv64 +#define packFloat32 packFloat32_riscv64 +#define packFloat64 packFloat64_riscv64 +#define packFloatx80 packFloatx80_riscv64 +#define page_find page_find_riscv64 +#define page_find_alloc page_find_alloc_riscv64 +#define page_flush_tb page_flush_tb_riscv64 +#define page_flush_tb_1 page_flush_tb_1_riscv64 +#define page_init page_init_riscv64 +#define page_size_init page_size_init_riscv64 +#define par_write par_write_riscv64 +#define parse_array parse_array_riscv64 +#define parse_cpu_model parse_cpu_model_riscv64 +#define parse_error parse_error_riscv64 +#define parse_escape parse_escape_riscv64 +#define parse_keyword parse_keyword_riscv64 +#define parse_literal parse_literal_riscv64 +#define parse_object parse_object_riscv64 +#define parse_option_bool parse_option_bool_riscv64 +#define parse_option_number parse_option_number_riscv64 +#define parse_option_size parse_option_size_riscv64 +#define parse_optional parse_optional_riscv64 +#define parse_pair parse_pair_riscv64 +#define parse_str parse_str_riscv64 +#define parse_type_bool parse_type_bool_riscv64 +#define parse_type_int parse_type_int_riscv64 +#define parse_type_number parse_type_number_riscv64 +#define parse_type_size parse_type_size_riscv64 +#define parse_type_str parse_type_str_riscv64 +#define parse_value parse_value_riscv64 +#define parser_context_free parser_context_free_riscv64 +#define parser_context_new parser_context_new_riscv64 +#define parser_context_peek_token parser_context_peek_token_riscv64 +#define parser_context_pop_token parser_context_pop_token_riscv64 +#define parser_context_restore parser_context_restore_riscv64 +#define parser_context_save parser_context_save_riscv64 +#define patch_reloc patch_reloc_riscv64 +#define phys_map_node_alloc phys_map_node_alloc_riscv64 +#define phys_map_node_reserve phys_map_node_reserve_riscv64 +#define phys_mem_alloc phys_mem_alloc_riscv64 +#define phys_mem_set_alloc phys_mem_set_alloc_riscv64 +#define phys_page_compact phys_page_compact_riscv64 +#define phys_page_compact_all phys_page_compact_all_riscv64 +#define phys_page_find phys_page_find_riscv64 +#define phys_page_set phys_page_set_riscv64 +#define phys_page_set_level phys_page_set_level_riscv64 +#define phys_section_add phys_section_add_riscv64 +#define phys_section_destroy phys_section_destroy_riscv64 +#define phys_sections_free phys_sections_free_riscv64 +#define pickNaN pickNaN_riscv64 +#define pickNaNMulAdd pickNaNMulAdd_riscv64 +#define pmccfiltr_write pmccfiltr_write_riscv64 +#define pmccntr_read pmccntr_read_riscv64 +#define pmccntr_sync pmccntr_sync_riscv64 +#define pmccntr_write pmccntr_write_riscv64 +#define pmccntr_write32 pmccntr_write32_riscv64 +#define pmcntenclr_write pmcntenclr_write_riscv64 +#define pmcntenset_write pmcntenset_write_riscv64 +#define pmcr_write pmcr_write_riscv64 +#define pmintenclr_write pmintenclr_write_riscv64 +#define pmintenset_write pmintenset_write_riscv64 +#define pmovsr_write pmovsr_write_riscv64 +#define pmreg_access pmreg_access_riscv64 +#define pmsav5_cp_reginfo pmsav5_cp_reginfo_riscv64 +#define pmsav5_data_ap_read pmsav5_data_ap_read_riscv64 +#define pmsav5_data_ap_write pmsav5_data_ap_write_riscv64 +#define pmsav5_insn_ap_read pmsav5_insn_ap_read_riscv64 +#define pmsav5_insn_ap_write pmsav5_insn_ap_write_riscv64 +#define pmuserenr_write pmuserenr_write_riscv64 +#define pmxevtyper_write pmxevtyper_write_riscv64 +#define ppc_tb_set_jmp_target ppc_tb_set_jmp_target_riscv64 +#define print_type_bool print_type_bool_riscv64 +#define print_type_int print_type_int_riscv64 +#define print_type_number print_type_number_riscv64 +#define print_type_size print_type_size_riscv64 +#define print_type_str print_type_str_riscv64 +#define probe_write probe_write_riscv64 +#define propagateFloat128NaN propagateFloat128NaN_riscv64 +#define propagateFloat32MulAddNaN propagateFloat32MulAddNaN_riscv64 +#define propagateFloat32NaN propagateFloat32NaN_riscv64 +#define propagateFloat64MulAddNaN propagateFloat64MulAddNaN_riscv64 +#define propagateFloat64NaN propagateFloat64NaN_riscv64 +#define propagateFloatx80NaN propagateFloatx80NaN_riscv64 +#define property_get_alias property_get_alias_riscv64 +#define property_get_bool property_get_bool_riscv64 +#define property_get_str property_get_str_riscv64 +#define property_get_uint16_ptr property_get_uint16_ptr_riscv64 +#define property_get_uint32_ptr property_get_uint32_ptr_riscv64 +#define property_get_uint64_ptr property_get_uint64_ptr_riscv64 +#define property_get_uint8_ptr property_get_uint8_ptr_riscv64 +#define property_release_alias property_release_alias_riscv64 +#define property_release_bool property_release_bool_riscv64 +#define property_release_str property_release_str_riscv64 +#define property_resolve_alias property_resolve_alias_riscv64 +#define property_set_alias property_set_alias_riscv64 +#define property_set_bool property_set_bool_riscv64 +#define property_set_str property_set_str_riscv64 +#define pstate_read pstate_read_riscv64 +#define pstate_write pstate_write_riscv64 +#define pxa250_initfn pxa250_initfn_riscv64 +#define pxa255_initfn pxa255_initfn_riscv64 +#define pxa260_initfn pxa260_initfn_riscv64 +#define pxa261_initfn pxa261_initfn_riscv64 +#define pxa262_initfn pxa262_initfn_riscv64 +#define pxa270a0_initfn pxa270a0_initfn_riscv64 +#define pxa270a1_initfn pxa270a1_initfn_riscv64 +#define pxa270b0_initfn pxa270b0_initfn_riscv64 +#define pxa270b1_initfn pxa270b1_initfn_riscv64 +#define pxa270c0_initfn pxa270c0_initfn_riscv64 +#define pxa270c5_initfn pxa270c5_initfn_riscv64 +#define qapi_dealloc_end_implicit_struct qapi_dealloc_end_implicit_struct_riscv64 +#define qapi_dealloc_end_list qapi_dealloc_end_list_riscv64 +#define qapi_dealloc_end_struct qapi_dealloc_end_struct_riscv64 +#define qapi_dealloc_get_visitor qapi_dealloc_get_visitor_riscv64 +#define qapi_dealloc_next_list qapi_dealloc_next_list_riscv64 +#define qapi_dealloc_pop qapi_dealloc_pop_riscv64 +#define qapi_dealloc_push qapi_dealloc_push_riscv64 +#define qapi_dealloc_start_implicit_struct qapi_dealloc_start_implicit_struct_riscv64 +#define qapi_dealloc_start_list qapi_dealloc_start_list_riscv64 +#define qapi_dealloc_start_struct qapi_dealloc_start_struct_riscv64 +#define qapi_dealloc_start_union qapi_dealloc_start_union_riscv64 +#define qapi_dealloc_type_bool qapi_dealloc_type_bool_riscv64 +#define qapi_dealloc_type_enum qapi_dealloc_type_enum_riscv64 +#define qapi_dealloc_type_int qapi_dealloc_type_int_riscv64 +#define qapi_dealloc_type_number qapi_dealloc_type_number_riscv64 +#define qapi_dealloc_type_size qapi_dealloc_type_size_riscv64 +#define qapi_dealloc_type_str qapi_dealloc_type_str_riscv64 +#define qapi_dealloc_visitor_cleanup qapi_dealloc_visitor_cleanup_riscv64 +#define qapi_dealloc_visitor_new qapi_dealloc_visitor_new_riscv64 +#define qapi_free_ErrorClassList qapi_free_ErrorClassList_riscv64 +#define qapi_free_X86CPUFeatureWordInfo qapi_free_X86CPUFeatureWordInfo_riscv64 +#define qapi_free_X86CPUFeatureWordInfoList qapi_free_X86CPUFeatureWordInfoList_riscv64 +#define qapi_free_X86CPURegister32List qapi_free_X86CPURegister32List_riscv64 +#define qapi_free_boolList qapi_free_boolList_riscv64 +#define qapi_free_int16List qapi_free_int16List_riscv64 +#define qapi_free_int32List qapi_free_int32List_riscv64 +#define qapi_free_int64List qapi_free_int64List_riscv64 +#define qapi_free_int8List qapi_free_int8List_riscv64 +#define qapi_free_intList qapi_free_intList_riscv64 +#define qapi_free_numberList qapi_free_numberList_riscv64 +#define qapi_free_strList qapi_free_strList_riscv64 +#define qapi_free_uint16List qapi_free_uint16List_riscv64 +#define qapi_free_uint32List qapi_free_uint32List_riscv64 +#define qapi_free_uint64List qapi_free_uint64List_riscv64 +#define qapi_free_uint8List qapi_free_uint8List_riscv64 +#define qbool_destroy_obj qbool_destroy_obj_riscv64 +#define qbool_from_int qbool_from_int_riscv64 +#define qbool_get_int qbool_get_int_riscv64 +#define qbool_type qbool_type_riscv64 +#define qbus_create qbus_create_riscv64 +#define qbus_create_inplace qbus_create_inplace_riscv64 +#define qbus_finalize qbus_finalize_riscv64 +#define qbus_initfn qbus_initfn_riscv64 +#define qbus_realize qbus_realize_riscv64 +#define qdev_create qdev_create_riscv64 +#define qdev_get_type qdev_get_type_riscv64 +#define qdev_register_types qdev_register_types_riscv64 +#define qdev_set_parent_bus qdev_set_parent_bus_riscv64 +#define qdev_try_create qdev_try_create_riscv64 +#define qdict_add_key qdict_add_key_riscv64 +#define qdict_array_split qdict_array_split_riscv64 +#define qdict_clone_shallow qdict_clone_shallow_riscv64 +#define qdict_del qdict_del_riscv64 +#define qdict_destroy_obj qdict_destroy_obj_riscv64 +#define qdict_entry_key qdict_entry_key_riscv64 +#define qdict_entry_value qdict_entry_value_riscv64 +#define qdict_extract_subqdict qdict_extract_subqdict_riscv64 +#define qdict_find qdict_find_riscv64 +#define qdict_first qdict_first_riscv64 +#define qdict_flatten qdict_flatten_riscv64 +#define qdict_flatten_qdict qdict_flatten_qdict_riscv64 +#define qdict_flatten_qlist qdict_flatten_qlist_riscv64 +#define qdict_get qdict_get_riscv64 +#define qdict_get_bool qdict_get_bool_riscv64 +#define qdict_get_double qdict_get_double_riscv64 +#define qdict_get_int qdict_get_int_riscv64 +#define qdict_get_obj qdict_get_obj_riscv64 +#define qdict_get_qdict qdict_get_qdict_riscv64 +#define qdict_get_qlist qdict_get_qlist_riscv64 +#define qdict_get_str qdict_get_str_riscv64 +#define qdict_get_try_bool qdict_get_try_bool_riscv64 +#define qdict_get_try_int qdict_get_try_int_riscv64 +#define qdict_get_try_str qdict_get_try_str_riscv64 +#define qdict_has_prefixed_entries qdict_has_prefixed_entries_riscv64 +#define qdict_haskey qdict_haskey_riscv64 +#define qdict_iter qdict_iter_riscv64 +#define qdict_join qdict_join_riscv64 +#define qdict_new qdict_new_riscv64 +#define qdict_next qdict_next_riscv64 +#define qdict_next_entry qdict_next_entry_riscv64 +#define qdict_put_bool qdict_put_bool_riscv64 +#define qdict_put_int qdict_put_int_riscv64 +#define qdict_put_null qdict_put_null_riscv64 +#define qdict_put_obj qdict_put_obj_riscv64 +#define qdict_put_str qdict_put_str_riscv64 +#define qdict_rename_keys qdict_rename_keys_riscv64 +#define qdict_size qdict_size_riscv64 +#define qdict_type qdict_type_riscv64 +#define qemu_clock_get_us qemu_clock_get_us_riscv64 +#define qemu_clock_ptr qemu_clock_ptr_riscv64 +#define qemu_clocks qemu_clocks_riscv64 +#define qemu_get_cpu qemu_get_cpu_riscv64 +#define qemu_get_guest_memory_mapping qemu_get_guest_memory_mapping_riscv64 +#define qemu_get_guest_simple_memory_mapping qemu_get_guest_simple_memory_mapping_riscv64 +#define qemu_get_ram_block qemu_get_ram_block_riscv64 +#define qemu_host_page_mask qemu_host_page_mask_riscv64 +#define qemu_host_page_size qemu_host_page_size_riscv64 +#define qemu_init_vcpu qemu_init_vcpu_riscv64 +#define qemu_ld_helpers qemu_ld_helpers_riscv64 +#define qemu_log_enabled qemu_log_enabled_riscv64 +#define qemu_log_vprintf qemu_log_vprintf_riscv64 +#define qemu_loglevel_mask qemu_loglevel_mask_riscv64 +#define qemu_map_ram_ptr qemu_map_ram_ptr_riscv64 +#define qemu_oom_check qemu_oom_check_riscv64 +#define qemu_parse_fd qemu_parse_fd_riscv64 +#define qemu_ram_addr_from_host qemu_ram_addr_from_host_riscv64 +#define qemu_ram_addr_from_host_nofail qemu_ram_addr_from_host_nofail_riscv64 +#define qemu_ram_alloc qemu_ram_alloc_riscv64 +#define qemu_ram_alloc_from_ptr qemu_ram_alloc_from_ptr_riscv64 +#define qemu_ram_alloc_resizeable qemu_ram_alloc_resizeable_riscv64 +#define qemu_ram_block_by_name qemu_ram_block_by_name_riscv64 +#define qemu_ram_block_from_host qemu_ram_block_from_host_riscv64 +#define qemu_ram_foreach_block qemu_ram_foreach_block_riscv64 +#define qemu_ram_free qemu_ram_free_riscv64 +#define qemu_ram_get_idstr qemu_ram_get_idstr_riscv64 +#define qemu_ram_is_shared qemu_ram_is_shared_riscv64 +#define qemu_ram_ptr_length qemu_ram_ptr_length_riscv64 +#define qemu_ram_remap qemu_ram_remap_riscv64 +#define qemu_ram_resize qemu_ram_resize_riscv64 +#define qemu_ram_setup_dump qemu_ram_setup_dump_riscv64 +#define qemu_ram_unset_idstr qemu_ram_unset_idstr_riscv64 +#define qemu_st_helpers qemu_st_helpers_riscv64 +#define qemu_strnlen qemu_strnlen_riscv64 +#define qemu_strsep qemu_strsep_riscv64 +#define qemu_tcg_configure qemu_tcg_configure_riscv64 +#define qemu_tcg_init_vcpu qemu_tcg_init_vcpu_riscv64 +#define qemu_try_memalign qemu_try_memalign_riscv64 +#define qentry_destroy qentry_destroy_riscv64 +#define qerror_human qerror_human_riscv64 +#define qerror_report qerror_report_riscv64 +#define qerror_report_err qerror_report_err_riscv64 +#define qfloat_destroy_obj qfloat_destroy_obj_riscv64 +#define qfloat_from_double qfloat_from_double_riscv64 +#define qfloat_get_double qfloat_get_double_riscv64 +#define qfloat_type qfloat_type_riscv64 +#define qint_destroy_obj qint_destroy_obj_riscv64 +#define qint_from_int qint_from_int_riscv64 +#define qint_get_int qint_get_int_riscv64 +#define qint_type qint_type_riscv64 +#define qlist_append_bool qlist_append_bool_riscv64 +#define qlist_append_int qlist_append_int_riscv64 +#define qlist_append_null qlist_append_null_riscv64 +#define qlist_append_obj qlist_append_obj_riscv64 +#define qlist_append_str qlist_append_str_riscv64 +#define qlist_copy qlist_copy_riscv64 +#define qlist_copy_elem qlist_copy_elem_riscv64 +#define qlist_destroy_obj qlist_destroy_obj_riscv64 +#define qlist_empty qlist_empty_riscv64 +#define qlist_entry_obj qlist_entry_obj_riscv64 +#define qlist_first qlist_first_riscv64 +#define qlist_iter qlist_iter_riscv64 +#define qlist_new qlist_new_riscv64 +#define qlist_next qlist_next_riscv64 +#define qlist_peek qlist_peek_riscv64 +#define qlist_pop qlist_pop_riscv64 +#define qlist_size qlist_size_riscv64 +#define qlist_size_iter qlist_size_iter_riscv64 +#define qlist_type qlist_type_riscv64 +#define qlit_equal_qobject qlit_equal_qobject_riscv64 +#define qobject_from_qlit qobject_from_qlit_riscv64 +#define qobject_get_try_str qobject_get_try_str_riscv64 +#define qobject_input_end_implicit_struct qobject_input_end_implicit_struct_riscv64 +#define qobject_input_end_list qobject_input_end_list_riscv64 +#define qobject_input_end_struct qobject_input_end_struct_riscv64 +#define qobject_input_get_next_type qobject_input_get_next_type_riscv64 +#define qobject_input_get_object qobject_input_get_object_riscv64 +#define qobject_input_get_visitor qobject_input_get_visitor_riscv64 +#define qobject_input_next_list qobject_input_next_list_riscv64 +#define qobject_input_optional qobject_input_optional_riscv64 +#define qobject_input_pop qobject_input_pop_riscv64 +#define qobject_input_push qobject_input_push_riscv64 +#define qobject_input_start_implicit_struct qobject_input_start_implicit_struct_riscv64 +#define qobject_input_start_list qobject_input_start_list_riscv64 +#define qobject_input_start_struct qobject_input_start_struct_riscv64 +#define qobject_input_type_bool qobject_input_type_bool_riscv64 +#define qobject_input_type_int qobject_input_type_int_riscv64 +#define qobject_input_type_number qobject_input_type_number_riscv64 +#define qobject_input_type_str qobject_input_type_str_riscv64 +#define qobject_input_visitor_cleanup qobject_input_visitor_cleanup_riscv64 +#define qobject_input_visitor_new qobject_input_visitor_new_riscv64 +#define qobject_input_visitor_new_strict qobject_input_visitor_new_strict_riscv64 +#define qobject_output_add_obj qobject_output_add_obj_riscv64 +#define qobject_output_end_list qobject_output_end_list_riscv64 +#define qobject_output_end_struct qobject_output_end_struct_riscv64 +#define qobject_output_first qobject_output_first_riscv64 +#define qobject_output_get_qobject qobject_output_get_qobject_riscv64 +#define qobject_output_get_visitor qobject_output_get_visitor_riscv64 +#define qobject_output_last qobject_output_last_riscv64 +#define qobject_output_next_list qobject_output_next_list_riscv64 +#define qobject_output_pop qobject_output_pop_riscv64 +#define qobject_output_push_obj qobject_output_push_obj_riscv64 +#define qobject_output_start_list qobject_output_start_list_riscv64 +#define qobject_output_start_struct qobject_output_start_struct_riscv64 +#define qobject_output_type_bool qobject_output_type_bool_riscv64 +#define qobject_output_type_int qobject_output_type_int_riscv64 +#define qobject_output_type_number qobject_output_type_number_riscv64 +#define qobject_output_type_str qobject_output_type_str_riscv64 +#define qobject_output_visitor_cleanup qobject_output_visitor_cleanup_riscv64 +#define qobject_output_visitor_new qobject_output_visitor_new_riscv64 +#define qobject_decref qobject_decref_riscv64 +#define qobject_type qobject_type_riscv64 +#define qstring_append qstring_append_riscv64 +#define qstring_append_chr qstring_append_chr_riscv64 +#define qstring_append_int qstring_append_int_riscv64 +#define qstring_destroy_obj qstring_destroy_obj_riscv64 +#define qstring_from_escaped_str qstring_from_escaped_str_riscv64 +#define qstring_from_str qstring_from_str_riscv64 +#define qstring_from_substr qstring_from_substr_riscv64 +#define qstring_get_length qstring_get_length_riscv64 +#define qstring_get_str qstring_get_str_riscv64 +#define qstring_get_try_str qstring_get_try_str_riscv64 +#define qstring_new qstring_new_riscv64 +#define qstring_type qstring_type_riscv64 +#define ram_block_add ram_block_add_riscv64 +#define ram_size ram_size_riscv64 +#define range_compare range_compare_riscv64 +#define range_covers_byte range_covers_byte_riscv64 +#define range_get_last range_get_last_riscv64 +#define range_merge range_merge_riscv64 +#define ranges_can_merge ranges_can_merge_riscv64 +#define raw_read raw_read_riscv64 +#define raw_write raw_write_riscv64 +#define rcon rcon_riscv64 +#define read_raw_cp_reg read_raw_cp_reg_riscv64 +#define recip_estimate recip_estimate_riscv64 +#define recip_sqrt_estimate recip_sqrt_estimate_riscv64 +#define register_cp_regs_for_features register_cp_regs_for_features_riscv64 +#define register_multipage register_multipage_riscv64 +#define register_subpage register_subpage_riscv64 +#define register_tm_clones register_tm_clones_riscv64 +#define register_types_object register_types_object_riscv64 +#define regnames regnames_riscv64 +#define render_memory_region render_memory_region_riscv64 +#define reset_all_temps reset_all_temps_riscv64 +#define reset_temp reset_temp_riscv64 +#define restore_state_to_opc restore_state_to_opc_riscv64 +#define resume_all_vcpus resume_all_vcpus_riscv64 +#define rol32 rol32_riscv64 +#define rol64 rol64_riscv64 +#define ror32 ror32_riscv64 +#define ror64 ror64_riscv64 +#define roundAndPackFloat128 roundAndPackFloat128_riscv64 +#define roundAndPackFloat16 roundAndPackFloat16_riscv64 +#define roundAndPackFloat32 roundAndPackFloat32_riscv64 +#define roundAndPackFloat64 roundAndPackFloat64_riscv64 +#define roundAndPackFloatx80 roundAndPackFloatx80_riscv64 +#define roundAndPackInt32 roundAndPackInt32_riscv64 +#define roundAndPackInt64 roundAndPackInt64_riscv64 +#define roundAndPackUint64 roundAndPackUint64_riscv64 +#define round_to_inf round_to_inf_riscv64 +#define run_on_cpu run_on_cpu_riscv64 +#define s0 s0_riscv64 +#define s1 s1_riscv64 +#define sa1100_initfn sa1100_initfn_riscv64 +#define sa1110_initfn sa1110_initfn_riscv64 +#define save_globals save_globals_riscv64 +#define scr_write scr_write_riscv64 +#define sctlr_write sctlr_write_riscv64 +#define set_bit set_bit_riscv64 +#define set_bits set_bits_riscv64 +#define set_default_nan_mode set_default_nan_mode_riscv64 +#define set_feature set_feature_riscv64 +#define set_float_detect_tininess set_float_detect_tininess_riscv64 +#define set_float_exception_flags set_float_exception_flags_riscv64 +#define set_float_rounding_mode set_float_rounding_mode_riscv64 +#define set_flush_inputs_to_zero set_flush_inputs_to_zero_riscv64 +#define set_flush_to_zero set_flush_to_zero_riscv64 +#define set_preferred_target_page_bits set_preferred_target_page_bits_riscv64 +#define set_swi_errno set_swi_errno_riscv64 +#define sextract32 sextract32_riscv64 +#define sextract64 sextract64_riscv64 +#define shift128ExtraRightJamming shift128ExtraRightJamming_riscv64 +#define shift128Right shift128Right_riscv64 +#define shift128RightJamming shift128RightJamming_riscv64 +#define shift32RightJamming shift32RightJamming_riscv64 +#define shift64ExtraRightJamming shift64ExtraRightJamming_riscv64 +#define shift64RightJamming shift64RightJamming_riscv64 +#define shifter_out_im shifter_out_im_riscv64 +#define shortShift128Left shortShift128Left_riscv64 +#define shortShift192Left shortShift192Left_riscv64 +#define simd_desc simd_desc_riscv64 +#define simple_mpu_ap_bits simple_mpu_ap_bits_riscv64 +#define size_code_gen_buffer size_code_gen_buffer_riscv64 +#define softmmu_lock_user softmmu_lock_user_riscv64 +#define softmmu_lock_user_string softmmu_lock_user_string_riscv64 +#define softmmu_tget32 softmmu_tget32_riscv64 +#define softmmu_tget8 softmmu_tget8_riscv64 +#define softmmu_tput32 softmmu_tput32_riscv64 +#define softmmu_unlock_user softmmu_unlock_user_riscv64 +#define sort_constraints sort_constraints_riscv64 +#define sp_el0_access sp_el0_access_riscv64 +#define spsel_read spsel_read_riscv64 +#define spsel_write spsel_write_riscv64 +#define start_list start_list_riscv64 +#define stb_p stb_p_riscv64 +#define stb_phys stb_phys_riscv64 +#define stb_phys_cached stb_phys_cached_riscv64 +#define stl_be_p stl_be_p_riscv64 +#define stl_be_phys stl_be_phys_riscv64 +#define stl_be_phys_cached stl_be_phys_cached_riscv64 +#define stl_he_p stl_he_p_riscv64 +#define stl_le_p stl_le_p_riscv64 +#define stl_le_phys stl_le_phys_riscv64 +#define stl_le_phys_cached stl_le_phys_cached_riscv64 +#define stl_phys stl_phys_riscv64 +#define stl_phys_cached stl_phys_cached_riscv64 +#define stl_phys_internal stl_phys_internal_riscv64 +#define stl_phys_notdirty stl_phys_notdirty_riscv64 +#define stl_phys_notdirty_cached stl_phys_notdirty_cached_riscv64 +#define store_cpu_offset store_cpu_offset_riscv64 +#define store_reg store_reg_riscv64 +#define store_reg_bx store_reg_bx_riscv64 +#define store_reg_from_load store_reg_from_load_riscv64 +#define stq_be_p stq_be_p_riscv64 +#define stq_be_phys stq_be_phys_riscv64 +#define stq_be_phys_cached stq_be_phys_cached_riscv64 +#define stq_he_p stq_he_p_riscv64 +#define stq_le_p stq_le_p_riscv64 +#define stq_le_phys stq_le_phys_riscv64 +#define stq_le_phys_cached stq_le_phys_cached_riscv64 +#define stq_phys stq_phys_riscv64 +#define stq_phys_cached stq_phys_cached_riscv64 +#define string_input_get_visitor string_input_get_visitor_riscv64 +#define string_input_visitor_cleanup string_input_visitor_cleanup_riscv64 +#define string_input_visitor_new string_input_visitor_new_riscv64 +#define stristart stristart_riscv64 +#define strongarm_cp_reginfo strongarm_cp_reginfo_riscv64 +#define strpadcpy strpadcpy_riscv64 +#define strstart strstart_riscv64 +#define stw_be_p stw_be_p_riscv64 +#define stw_be_phys stw_be_phys_riscv64 +#define stw_be_phys_cached stw_be_phys_cached_riscv64 +#define stw_he_p stw_he_p_riscv64 +#define stw_le_p stw_le_p_riscv64 +#define stw_le_phys stw_le_phys_riscv64 +#define stw_le_phys_cached stw_le_phys_cached_riscv64 +#define stw_phys stw_phys_riscv64 +#define stw_phys_cached stw_phys_cached_riscv64 +#define stw_phys_internal stw_phys_internal_riscv64 +#define sub128 sub128_riscv64 +#define sub16_sat sub16_sat_riscv64 +#define sub16_usat sub16_usat_riscv64 +#define sub192 sub192_riscv64 +#define sub8_sat sub8_sat_riscv64 +#define sub8_usat sub8_usat_riscv64 +#define subFloat128Sigs subFloat128Sigs_riscv64 +#define subFloat32Sigs subFloat32Sigs_riscv64 +#define subFloat64Sigs subFloat64Sigs_riscv64 +#define subFloatx80Sigs subFloatx80Sigs_riscv64 +#define subpage_accepts subpage_accepts_riscv64 +#define subpage_init subpage_init_riscv64 +#define subpage_ops subpage_ops_riscv64 +#define subpage_read subpage_read_riscv64 +#define subpage_register subpage_register_riscv64 +#define subpage_write subpage_write_riscv64 +#define suffix_mul suffix_mul_riscv64 +#define swap_commutative swap_commutative_riscv64 +#define swap_commutative2 swap_commutative2_riscv64 +#define switch_mode switch_mode_riscv64 +#define syn_aa32_bkpt syn_aa32_bkpt_riscv64 +#define syn_aa32_hvc syn_aa32_hvc_riscv64 +#define syn_aa32_smc syn_aa32_smc_riscv64 +#define syn_aa32_svc syn_aa32_svc_riscv64 +#define syn_breakpoint syn_breakpoint_riscv64 +#define syn_cp14_rrt_trap syn_cp14_rrt_trap_riscv64 +#define syn_cp14_rt_trap syn_cp14_rt_trap_riscv64 +#define syn_cp15_rrt_trap syn_cp15_rrt_trap_riscv64 +#define syn_cp15_rt_trap syn_cp15_rt_trap_riscv64 +#define syn_data_abort syn_data_abort_riscv64 +#define syn_fp_access_trap syn_fp_access_trap_riscv64 +#define syn_insn_abort syn_insn_abort_riscv64 +#define syn_swstep syn_swstep_riscv64 +#define syn_uncategorized syn_uncategorized_riscv64 +#define syn_watchpoint syn_watchpoint_riscv64 +#define sync_globals sync_globals_riscv64 +#define syscall_err syscall_err_riscv64 +#define system_bus_class_init system_bus_class_init_riscv64 +#define system_bus_info system_bus_info_riscv64 +#define t2ee_cp_reginfo t2ee_cp_reginfo_riscv64 +#define table_logic_cc table_logic_cc_riscv64 +#define target_el_table target_el_table_riscv64 +#define target_parse_constraint target_parse_constraint_riscv64 +#define target_words_bigendian target_words_bigendian_riscv64 +#define tb_alloc tb_alloc_riscv64 +#define tb_alloc_page tb_alloc_page_riscv64 +#define tb_check_watchpoint tb_check_watchpoint_riscv64 +#define tb_cleanup tb_cleanup_riscv64 +#define tb_find_fast tb_find_fast_riscv64 +#define tb_find_pc tb_find_pc_riscv64 +#define tb_find_slow tb_find_slow_riscv64 +#define tb_flush tb_flush_riscv64 +#define tb_flush_jmp_cache tb_flush_jmp_cache_riscv64 +#define tb_free tb_free_riscv64 +#define tb_gen_code tb_gen_code_riscv64 +#define tb_hash_remove tb_hash_remove_riscv64 +#define tb_htable_lookup tb_htable_lookup_riscv64 +#define tb_invalidate_phys_addr tb_invalidate_phys_addr_riscv64 +#define tb_invalidate_phys_page_fast tb_invalidate_phys_page_fast_riscv64 +#define tb_invalidate_phys_page_range tb_invalidate_phys_page_range_riscv64 +#define tb_invalidate_phys_range tb_invalidate_phys_range_riscv64 +#define tb_jmp_cache_hash_func tb_jmp_cache_hash_func_riscv64 +#define tb_jmp_cache_hash_page tb_jmp_cache_hash_page_riscv64 +#define tb_jmp_remove tb_jmp_remove_riscv64 +#define tb_link_page tb_link_page_riscv64 +#define tb_page_remove tb_page_remove_riscv64 +#define tb_phys_hash_func tb_phys_hash_func_riscv64 +#define tb_phys_invalidate tb_phys_invalidate_riscv64 +#define tb_reset_jump tb_reset_jump_riscv64 +#define tb_set_jmp_target tb_set_jmp_target_riscv64 +#define tcg_accel_class_init tcg_accel_class_init_riscv64 +#define tcg_accel_type tcg_accel_type_riscv64 +#define tcg_add_param_i32 tcg_add_param_i32_riscv64 +#define tcg_add_param_i64 tcg_add_param_i64_riscv64 +#define tcg_add_target_add_op_defs tcg_add_target_add_op_defs_riscv64 +#define tcg_allowed tcg_allowed_riscv64 +#define tcg_can_emit_vec_op tcg_can_emit_vec_op_riscv64 +#define tcg_canonicalize_memop tcg_canonicalize_memop_riscv64 +#define tcg_commit tcg_commit_riscv64 +#define tcg_cond_to_jcc tcg_cond_to_jcc_riscv64 +#define tcg_const_i32 tcg_const_i32_riscv64 +#define tcg_const_i64 tcg_const_i64_riscv64 +#define tcg_const_local_i32 tcg_const_local_i32_riscv64 +#define tcg_const_local_i64 tcg_const_local_i64_riscv64 +#define tcg_const_ones_vec tcg_const_ones_vec_riscv64 +#define tcg_const_ones_vec_matching tcg_const_ones_vec_matching_riscv64 +#define tcg_const_zeros_vec tcg_const_zeros_vec_riscv64 +#define tcg_const_zeros_vec_matching tcg_const_zeros_vec_matching_riscv64 +#define tcg_constant_folding tcg_constant_folding_riscv64 +#define tcg_context_init tcg_context_init_riscv64 +#define tcg_cpu_exec tcg_cpu_exec_riscv64 +#define tcg_current_code_size tcg_current_code_size_riscv64 +#define tcg_dump_info tcg_dump_info_riscv64 +#define tcg_dump_ops tcg_dump_ops_riscv64 +#define tcg_emit_op tcg_emit_op_riscv64 +#define tcg_enabled tcg_enabled_riscv64 +#define tcg_exec_all tcg_exec_all_riscv64 +#define tcg_exec_init tcg_exec_init_riscv64 +#define tcg_expand_vec_op tcg_expand_vec_op_riscv64 +#define tcg_find_helper tcg_find_helper_riscv64 +#define tcg_flush_softmmu_tlb tcg_flush_softmmu_tlb_riscv64 +#define tcg_func_start tcg_func_start_riscv64 +#define tcg_gen_abs_i32 tcg_gen_abs_i32_riscv64 +#define tcg_gen_add2_i32 tcg_gen_add2_i32_riscv64 +#define tcg_gen_add2_i64 tcg_gen_add2_i64_riscv64 +#define tcg_gen_add_i32 tcg_gen_add_i32_riscv64 +#define tcg_gen_add_i64 tcg_gen_add_i64_riscv64 +#define tcg_gen_add_vec tcg_gen_add_vec_riscv64 +#define tcg_gen_addi_i32 tcg_gen_addi_i32_riscv64 +#define tcg_gen_addi_i64 tcg_gen_addi_i64_riscv64 +#define tcg_gen_and_i32 tcg_gen_and_i32_riscv64 +#define tcg_gen_and_i64 tcg_gen_and_i64_riscv64 +#define tcg_gen_and_vec tcg_gen_and_vec_riscv64 +#define tcg_gen_andc_i32 tcg_gen_andc_i32_riscv64 +#define tcg_gen_andc_i64 tcg_gen_andc_i64_riscv64 +#define tcg_gen_andc_vec tcg_gen_andc_vec_riscv64 +#define tcg_gen_andi_i32 tcg_gen_andi_i32_riscv64 +#define tcg_gen_andi_i64 tcg_gen_andi_i64_riscv64 +#define tcg_gen_atomic_add_fetch_i32 tcg_gen_atomic_add_fetch_i32_riscv64 +#define tcg_gen_atomic_add_fetch_i64 tcg_gen_atomic_add_fetch_i64_riscv64 +#define tcg_gen_atomic_and_fetch_i32 tcg_gen_atomic_and_fetch_i32_riscv64 +#define tcg_gen_atomic_and_fetch_i64 tcg_gen_atomic_and_fetch_i64_riscv64 +#define tcg_gen_atomic_cmpxchg_i32 tcg_gen_atomic_cmpxchg_i32_riscv64 +#define tcg_gen_atomic_cmpxchg_i64 tcg_gen_atomic_cmpxchg_i64_riscv64 +#define tcg_gen_atomic_fetch_add_i32 tcg_gen_atomic_fetch_add_i32_riscv64 +#define tcg_gen_atomic_fetch_add_i64 tcg_gen_atomic_fetch_add_i64_riscv64 +#define tcg_gen_atomic_fetch_and_i32 tcg_gen_atomic_fetch_and_i32_riscv64 +#define tcg_gen_atomic_fetch_and_i64 tcg_gen_atomic_fetch_and_i64_riscv64 +#define tcg_gen_atomic_fetch_or_i32 tcg_gen_atomic_fetch_or_i32_riscv64 +#define tcg_gen_atomic_fetch_or_i64 tcg_gen_atomic_fetch_or_i64_riscv64 +#define tcg_gen_atomic_fetch_smax_i32 tcg_gen_atomic_fetch_smax_i32_riscv64 +#define tcg_gen_atomic_fetch_smax_i64 tcg_gen_atomic_fetch_smax_i64_riscv64 +#define tcg_gen_atomic_fetch_smin_i32 tcg_gen_atomic_fetch_smin_i32_riscv64 +#define tcg_gen_atomic_fetch_smin_i64 tcg_gen_atomic_fetch_smin_i64_riscv64 +#define tcg_gen_atomic_fetch_umax_i32 tcg_gen_atomic_fetch_umax_i32_riscv64 +#define tcg_gen_atomic_fetch_umax_i64 tcg_gen_atomic_fetch_umax_i64_riscv64 +#define tcg_gen_atomic_fetch_umin_i32 tcg_gen_atomic_fetch_umin_i32_riscv64 +#define tcg_gen_atomic_fetch_umin_i64 tcg_gen_atomic_fetch_umin_i64_riscv64 +#define tcg_gen_atomic_fetch_xor_i32 tcg_gen_atomic_fetch_xor_i32_riscv64 +#define tcg_gen_atomic_fetch_xor_i64 tcg_gen_atomic_fetch_xor_i64_riscv64 +#define tcg_gen_atomic_or_fetch_i32 tcg_gen_atomic_or_fetch_i32_riscv64 +#define tcg_gen_atomic_or_fetch_i64 tcg_gen_atomic_or_fetch_i64_riscv64 +#define tcg_gen_atomic_smax_fetch_i32 tcg_gen_atomic_smax_fetch_i32_riscv64 +#define tcg_gen_atomic_smax_fetch_i64 tcg_gen_atomic_smax_fetch_i64_riscv64 +#define tcg_gen_atomic_smin_fetch_i32 tcg_gen_atomic_smin_fetch_i32_riscv64 +#define tcg_gen_atomic_smin_fetch_i64 tcg_gen_atomic_smin_fetch_i64_riscv64 +#define tcg_gen_atomic_umax_fetch_i32 tcg_gen_atomic_umax_fetch_i32_riscv64 +#define tcg_gen_atomic_umax_fetch_i64 tcg_gen_atomic_umax_fetch_i64_riscv64 +#define tcg_gen_atomic_umin_fetch_i32 tcg_gen_atomic_umin_fetch_i32_riscv64 +#define tcg_gen_atomic_umin_fetch_i64 tcg_gen_atomic_umin_fetch_i64_riscv64 +#define tcg_gen_atomic_xchg_i32 tcg_gen_atomic_xchg_i32_riscv64 +#define tcg_gen_atomic_xchg_i64 tcg_gen_atomic_xchg_i64_riscv64 +#define tcg_gen_atomic_xor_fetch_i32 tcg_gen_atomic_xor_fetch_i32_riscv64 +#define tcg_gen_atomic_xor_fetch_i64 tcg_gen_atomic_xor_fetch_i64_riscv64 +#define tcg_gen_br tcg_gen_br_riscv64 +#define tcg_gen_brcond_i32 tcg_gen_brcond_i32_riscv64 +#define tcg_gen_brcond_i64 tcg_gen_brcond_i64_riscv64 +#define tcg_gen_brcondi_i32 tcg_gen_brcondi_i32_riscv64 +#define tcg_gen_brcondi_i64 tcg_gen_brcondi_i64_riscv64 +#define tcg_gen_bswap16_i32 tcg_gen_bswap16_i32_riscv64 +#define tcg_gen_bswap16_i64 tcg_gen_bswap16_i64_riscv64 +#define tcg_gen_bswap32_i32 tcg_gen_bswap32_i32_riscv64 +#define tcg_gen_bswap32_i64 tcg_gen_bswap32_i64_riscv64 +#define tcg_gen_bswap64_i64 tcg_gen_bswap64_i64_riscv64 +#define tcg_gen_callN tcg_gen_callN_riscv64 +#define tcg_gen_clrsb_i32 tcg_gen_clrsb_i32_riscv64 +#define tcg_gen_clrsb_i64 tcg_gen_clrsb_i64_riscv64 +#define tcg_gen_clz_i32 tcg_gen_clz_i32_riscv64 +#define tcg_gen_clz_i64 tcg_gen_clz_i64_riscv64 +#define tcg_gen_clzi_i32 tcg_gen_clzi_i32_riscv64 +#define tcg_gen_clzi_i64 tcg_gen_clzi_i64_riscv64 +#define tcg_gen_cmp_vec tcg_gen_cmp_vec_riscv64 +#define tcg_gen_ctpop_i32 tcg_gen_ctpop_i32_riscv64 +#define tcg_gen_ctpop_i64 tcg_gen_ctpop_i64_riscv64 +#define tcg_gen_ctz_i32 tcg_gen_ctz_i32_riscv64 +#define tcg_gen_ctz_i64 tcg_gen_ctz_i64_riscv64 +#define tcg_gen_ctzi_i32 tcg_gen_ctzi_i32_riscv64 +#define tcg_gen_ctzi_i64 tcg_gen_ctzi_i64_riscv64 +#define tcg_gen_code tcg_gen_code_riscv64 +#define tcg_gen_concat_i32_i64 tcg_gen_concat_i32_i64_riscv64 +#define tcg_gen_deposit_i32 tcg_gen_deposit_i32_riscv64 +#define tcg_gen_deposit_i64 tcg_gen_deposit_i64_riscv64 +#define tcg_gen_deposit_z_i32 tcg_gen_deposit_z_i32_riscv64 +#define tcg_gen_deposit_z_i64 tcg_gen_deposit_z_i64_riscv64 +#define tcg_gen_discard_i64 tcg_gen_discard_i64_riscv64 +#define tcg_gen_div_i32 tcg_gen_div_i32_riscv64 +#define tcg_gen_div_i64 tcg_gen_div_i64_riscv64 +#define tcg_gen_divu_i32 tcg_gen_divu_i32_riscv64 +#define tcg_gen_divu_i64 tcg_gen_divu_i64_riscv64 +#define tcg_gen_dup8i_vec tcg_gen_dup8i_vec_riscv64 +#define tcg_gen_dup16i_vec tcg_gen_dup16i_vec_riscv64 +#define tcg_gen_dup32i_vec tcg_gen_dup32i_vec_riscv64 +#define tcg_gen_dup64i_vec tcg_gen_dup64i_vec_riscv64 +#define tcg_gen_dupi_vec tcg_gen_dupi_vec_riscv64 +#define tcg_gen_dup_i32_vec tcg_gen_dup_i32_vec_riscv64 +#define tcg_gen_dup_i64_vec tcg_gen_dup_i64_vec_riscv64 +#define tcg_gen_eqv_i32 tcg_gen_eqv_i32_riscv64 +#define tcg_gen_eqv_i64 tcg_gen_eqv_i64_riscv64 +#define tcg_gen_exit_tb tcg_gen_exit_tb_riscv64 +#define tcg_gen_ext16s_i32 tcg_gen_ext16s_i32_riscv64 +#define tcg_gen_ext16s_i64 tcg_gen_ext16s_i64_riscv64 +#define tcg_gen_ext16u_i32 tcg_gen_ext16u_i32_riscv64 +#define tcg_gen_ext16u_i64 tcg_gen_ext16u_i64_riscv64 +#define tcg_gen_ext32s_i64 tcg_gen_ext32s_i64_riscv64 +#define tcg_gen_ext32u_i64 tcg_gen_ext32u_i64_riscv64 +#define tcg_gen_ext8s_i32 tcg_gen_ext8s_i32_riscv64 +#define tcg_gen_ext8s_i64 tcg_gen_ext8s_i64_riscv64 +#define tcg_gen_ext8u_i32 tcg_gen_ext8u_i32_riscv64 +#define tcg_gen_ext8u_i64 tcg_gen_ext8u_i64_riscv64 +#define tcg_gen_ext_i32_i64 tcg_gen_ext_i32_i64_riscv64 +#define tcg_gen_extr32_i64 tcg_gen_extr32_i64_riscv64 +#define tcg_gen_extr_i64_i32 tcg_gen_extr_i64_i32_riscv64 +#define tcg_gen_extract_i32 tcg_gen_extract_i32_riscv64 +#define tcg_gen_extract_i64 tcg_gen_extract_i64_riscv64 +#define tcg_gen_extrh_i64_i32 tcg_gen_extrh_i64_i32_riscv64 +#define tcg_gen_extrl_i64_i32 tcg_gen_extrl_i64_i32_riscv64 +#define tcg_gen_extu_i32_i64 tcg_gen_extu_i32_i64_riscv64 +#define tcg_gen_goto_tb tcg_gen_goto_tb_riscv64 +#define tcg_gen_gvec_2 tcg_gen_gvec_2_riscv64 +#define tcg_gen_gvec_2i tcg_gen_gvec_2i_riscv64 +#define tcg_gen_gvec_2i_ool tcg_gen_gvec_2i_ool_riscv64 +#define tcg_gen_gvec_2s tcg_gen_gvec_2s_riscv64 +#define tcg_gen_gvec_2_ool tcg_gen_gvec_2_ool_riscv64 +#define tcg_gen_gvec_2_ptr tcg_gen_gvec_2_ptr_riscv64 +#define tcg_gen_gvec_3 tcg_gen_gvec_3_riscv64 +#define tcg_gen_gvec_3_ool tcg_gen_gvec_3_ool_riscv64 +#define tcg_gen_gvec_3_ptr tcg_gen_gvec_3_ptr_riscv64 +#define tcg_gen_gvec_4 tcg_gen_gvec_4_riscv64 +#define tcg_gen_gvec_4_ool tcg_gen_gvec_4_ool_riscv64 +#define tcg_gen_gvec_4_ptr tcg_gen_gvec_4_ptr_riscv64 +#define tcg_gen_gvec_5_ool tcg_gen_gvec_5_ool_riscv64 +#define tcg_gen_gvec_add tcg_gen_gvec_add_riscv64 +#define tcg_gen_gvec_addi tcg_gen_gvec_addi_riscv64 +#define tcg_gen_gvec_adds tcg_gen_gvec_adds_riscv64 +#define tcg_gen_gvec_adds8 tcg_gen_gvec_adds8_riscv64 +#define tcg_gen_gvec_adds16 tcg_gen_gvec_adds16_riscv64 +#define tcg_gen_gvec_adds32 tcg_gen_gvec_adds32_riscv64 +#define tcg_gen_gvec_adds64 tcg_gen_gvec_adds64_riscv64 +#define tcg_gen_gvec_and tcg_gen_gvec_and_riscv64 +#define tcg_gen_gvec_andc tcg_gen_gvec_andc_riscv64 +#define tcg_gen_gvec_andi tcg_gen_gvec_andi_riscv64 +#define tcg_gen_gvec_ands tcg_gen_gvec_ands_riscv64 +#define tcg_gen_gvec_cmp tcg_gen_gvec_cmp_riscv64 +#define tcg_gen_gvec_dup8i tcg_gen_gvec_dup8i_riscv64 +#define tcg_gen_gvec_dup16i tcg_gen_gvec_dup16i_riscv64 +#define tcg_gen_gvec_dup32i tcg_gen_gvec_dup32i_riscv64 +#define tcg_gen_gvec_dup64i tcg_gen_gvec_dup64i_riscv64 +#define tcg_gen_gvec_dup_i32 tcg_gen_gvec_dup_i32_riscv64 +#define tcg_gen_gvec_dup_i64 tcg_gen_gvec_dup_i64_riscv64 +#define tcg_gen_gvec_dup_mem tcg_gen_gvec_dup_mem_riscv64 +#define tcg_gen_gvec_mov tcg_gen_gvec_mov_riscv64 +#define tcg_gen_gvec_mul tcg_gen_gvec_mul_riscv64 +#define tcg_gen_gvec_muli tcg_gen_gvec_muli_riscv64 +#define tcg_gen_gvec_muls tcg_gen_gvec_muls_riscv64 +#define tcg_gen_gvec_muls8 tcg_gen_gvec_muls8_riscv64 +#define tcg_gen_gvec_muls16 tcg_gen_gvec_muls16_riscv64 +#define tcg_gen_gvec_muls32 tcg_gen_gvec_muls32_riscv64 +#define tcg_gen_gvec_muls64 tcg_gen_gvec_muls64_riscv64 +#define tcg_gen_gvec_neg tcg_gen_gvec_neg_riscv64 +#define tcg_gen_gvec_not tcg_gen_gvec_not_riscv64 +#define tcg_gen_gvec_or tcg_gen_gvec_or_riscv64 +#define tcg_gen_gvec_orc tcg_gen_gvec_orc_riscv64 +#define tcg_gen_gvec_ori tcg_gen_gvec_ori_riscv64 +#define tcg_gen_gvec_ors tcg_gen_gvec_ors_riscv64 +#define tcg_gen_gvec_sari tcg_gen_gvec_sari_riscv64 +#define tcg_gen_gvec_shli tcg_gen_gvec_shli_riscv64 +#define tcg_gen_gvec_shri tcg_gen_gvec_shri_riscv64 +#define tcg_gen_gvec_ssadd tcg_gen_gvec_ssadd_riscv64 +#define tcg_gen_gvec_sssub tcg_gen_gvec_sssub_riscv64 +#define tcg_gen_gvec_sub tcg_gen_gvec_sub_riscv64 +#define tcg_gen_gvec_subs tcg_gen_gvec_subs_riscv64 +#define tcg_gen_gvec_subs8 tcg_gen_gvec_subs8_riscv64 +#define tcg_gen_gvec_subs16 tcg_gen_gvec_subs16_riscv64 +#define tcg_gen_gvec_subs32 tcg_gen_gvec_subs32_riscv64 +#define tcg_gen_gvec_subs64 tcg_gen_gvec_subs64_riscv64 +#define tcg_gen_gvec_usadd tcg_gen_gvec_usadd_riscv64 +#define tcg_gen_gvec_ussub tcg_gen_gvec_ussub_riscv64 +#define tcg_gen_gvec_xor tcg_gen_gvec_xor_riscv64 +#define tcg_gen_gvec_xori tcg_gen_gvec_xori_riscv64 +#define tcg_gen_gvec_xors tcg_gen_gvec_xors_riscv64 +#define tcg_gen_insn_start tcg_gen_insn_start_riscv64 +#define tcg_gen_ld16s_i64 tcg_gen_ld16s_i64_riscv64 +#define tcg_gen_ld16u_i64 tcg_gen_ld16u_i64_riscv64 +#define tcg_gen_ld32s_i64 tcg_gen_ld32s_i64_riscv64 +#define tcg_gen_ld32u_i64 tcg_gen_ld32u_i64_riscv64 +#define tcg_gen_ld8s_i64 tcg_gen_ld8s_i64_riscv64 +#define tcg_gen_ld8u_i64 tcg_gen_ld8u_i64_riscv64 +#define tcg_gen_ld_i32 tcg_gen_ld_i32_riscv64 +#define tcg_gen_ld_i64 tcg_gen_ld_i64_riscv64 +#define tcg_gen_ld_vec tcg_gen_ld_vec_riscv64 +#define tcg_gen_ldst_op_i32 tcg_gen_ldst_op_i32_riscv64 +#define tcg_gen_ldst_op_i64 tcg_gen_ldst_op_i64_riscv64 +#define tcg_gen_lookup_and_goto_ptr tcg_gen_lookup_and_goto_ptr_riscv64 +#define tcg_gen_mb tcg_gen_mb_riscv64 +#define tcg_gen_mov_i32 tcg_gen_mov_i32_riscv64 +#define tcg_gen_mov_i64 tcg_gen_mov_i64_riscv64 +#define tcg_gen_mov_vec tcg_gen_mov_vec_riscv64 +#define tcg_gen_movcond_i32 tcg_gen_movcond_i32_riscv64 +#define tcg_gen_movcond_i64 tcg_gen_movcond_i64_riscv64 +#define tcg_gen_movi_i32 tcg_gen_movi_i32_riscv64 +#define tcg_gen_movi_i64 tcg_gen_movi_i64_riscv64 +#define tcg_gen_mul_i32 tcg_gen_mul_i32_riscv64 +#define tcg_gen_mul_i64 tcg_gen_mul_i64_riscv64 +#define tcg_gen_mul_vec tcg_gen_mul_vec_riscv64 +#define tcg_gen_muli_i32 tcg_gen_muli_i32_riscv64 +#define tcg_gen_muli_i64 tcg_gen_muli_i64_riscv64 +#define tcg_gen_muls2_i32 tcg_gen_muls2_i32_riscv64 +#define tcg_gen_muls2_i64 tcg_gen_muls2_i64_riscv64 +#define tcg_gen_mulsu2_i32 tcg_gen_mulsu2_i32_riscv64 +#define tcg_gen_mulsu2_i64 tcg_gen_mulsu2_i64_riscv64 +#define tcg_gen_mulu2_i32 tcg_gen_mulu2_i32_riscv64 +#define tcg_gen_mulu2_i64 tcg_gen_mulu2_i64_riscv64 +#define tcg_gen_nand_i32 tcg_gen_nand_i32_riscv64 +#define tcg_gen_nand_i64 tcg_gen_nand_i64_riscv64 +#define tcg_gen_neg_i32 tcg_gen_neg_i32_riscv64 +#define tcg_gen_neg_i64 tcg_gen_neg_i64_riscv64 +#define tcg_gen_neg_vec tcg_gen_neg_vec_riscv64 +#define tcg_gen_nor_i32 tcg_gen_nor_i32_riscv64 +#define tcg_gen_nor_i64 tcg_gen_nor_i64_riscv64 +#define tcg_gen_nor_vec tcg_gen_nor_vec_riscv64 +#define tcg_gen_not_i32 tcg_gen_not_i32_riscv64 +#define tcg_gen_not_i64 tcg_gen_not_i64_riscv64 +#define tcg_gen_not_vec tcg_gen_not_vec_riscv64 +#define tcg_gen_op1 tcg_gen_op1_riscv64 +#define tcg_gen_op1i tcg_gen_op1i_riscv64 +#define tcg_gen_op2 tcg_gen_op2_riscv64 +#define tcg_gen_op2_i32 tcg_gen_op2_i32_riscv64 +#define tcg_gen_op2_i64 tcg_gen_op2_i64_riscv64 +#define tcg_gen_op2i_i32 tcg_gen_op2i_i32_riscv64 +#define tcg_gen_op2i_i64 tcg_gen_op2i_i64_riscv64 +#define tcg_gen_op3 tcg_gen_op3_riscv64 +#define tcg_gen_op3_i32 tcg_gen_op3_i32_riscv64 +#define tcg_gen_op3_i64 tcg_gen_op3_i64_riscv64 +#define tcg_gen_op4 tcg_gen_op4_riscv64 +#define tcg_gen_op4_i32 tcg_gen_op4_i32_riscv64 +#define tcg_gen_op4i_i32 tcg_gen_op4i_i32_riscv64 +#define tcg_gen_op4ii_i32 tcg_gen_op4ii_i32_riscv64 +#define tcg_gen_op4ii_i64 tcg_gen_op4ii_i64_riscv64 +#define tcg_gen_op5 tcg_gen_op5_riscv64 +#define tcg_gen_op5ii_i32 tcg_gen_op5ii_i32_riscv64 +#define tcg_gen_op6 tcg_gen_op6_riscv64 +#define tcg_gen_op6_i32 tcg_gen_op6_i32_riscv64 +#define tcg_gen_op6i_i32 tcg_gen_op6i_i32_riscv64 +#define tcg_gen_op6i_i64 tcg_gen_op6i_i64_riscv64 +#define tcg_gen_or_i32 tcg_gen_or_i32_riscv64 +#define tcg_gen_or_i64 tcg_gen_or_i64_riscv64 +#define tcg_gen_or_vec tcg_gen_or_vec_riscv64 +#define tcg_gen_orc_i32 tcg_gen_orc_i32_riscv64 +#define tcg_gen_orc_i64 tcg_gen_orc_i64_riscv64 +#define tcg_gen_orc_vec tcg_gen_orc_vec_riscv64 +#define tcg_gen_ori_i32 tcg_gen_ori_i32_riscv64 +#define tcg_gen_ori_i64 tcg_gen_ori_i64_riscv64 +#define tcg_gen_qemu_ld_i32 tcg_gen_qemu_ld_i32_riscv64 +#define tcg_gen_qemu_ld_i64 tcg_gen_qemu_ld_i64_riscv64 +#define tcg_gen_qemu_st_i32 tcg_gen_qemu_st_i32_riscv64 +#define tcg_gen_qemu_st_i64 tcg_gen_qemu_st_i64_riscv64 +#define tcg_gen_rem_i32 tcg_gen_rem_i32_riscv64 +#define tcg_gen_rem_i64 tcg_gen_rem_i64_riscv64 +#define tcg_gen_remu_i32 tcg_gen_remu_i32_riscv64 +#define tcg_gen_remu_i64 tcg_gen_remu_i64_riscv64 +#define tcg_gen_rotl_i32 tcg_gen_rotl_i32_riscv64 +#define tcg_gen_rotl_i64 tcg_gen_rotl_i64_riscv64 +#define tcg_gen_rotli_i32 tcg_gen_rotli_i32_riscv64 +#define tcg_gen_rotli_i64 tcg_gen_rotli_i64_riscv64 +#define tcg_gen_rotr_i32 tcg_gen_rotr_i32_riscv64 +#define tcg_gen_rotr_i64 tcg_gen_rotr_i64_riscv64 +#define tcg_gen_rotri_i32 tcg_gen_rotri_i32_riscv64 +#define tcg_gen_rotri_i64 tcg_gen_rotri_i64_riscv64 +#define tcg_gen_sar_i32 tcg_gen_sar_i32_riscv64 +#define tcg_gen_sar_i64 tcg_gen_sar_i64_riscv64 +#define tcg_gen_sari_i32 tcg_gen_sari_i32_riscv64 +#define tcg_gen_sari_i64 tcg_gen_sari_i64_riscv64 +#define tcg_gen_sari_vec tcg_gen_sari_vec_riscv64 +#define tcg_gen_setcond_i32 tcg_gen_setcond_i32_riscv64 +#define tcg_gen_setcond_i64 tcg_gen_setcond_i64_riscv64 +#define tcg_gen_setcondi_i32 tcg_gen_setcondi_i32_riscv64 +#define tcg_gen_setcondi_i64 tcg_gen_setcondi_i64_riscv64 +#define tcg_gen_sextract_i32 tcg_gen_sextract_i32_riscv64 +#define tcg_gen_sextract_i64 tcg_gen_sextract_i64_riscv64 +#define tcg_gen_shifti_i64 tcg_gen_shifti_i64_riscv64 +#define tcg_gen_shl_i32 tcg_gen_shl_i32_riscv64 +#define tcg_gen_shl_i64 tcg_gen_shl_i64_riscv64 +#define tcg_gen_shli_i32 tcg_gen_shli_i32_riscv64 +#define tcg_gen_shli_i64 tcg_gen_shli_i64_riscv64 +#define tcg_gen_shli_vec tcg_gen_shli_vec_riscv64 +#define tcg_gen_shr_i32 tcg_gen_shr_i32_riscv64 +#define tcg_gen_shr_i64 tcg_gen_shr_i64_riscv64 +#define tcg_gen_shri_i32 tcg_gen_shri_i32_riscv64 +#define tcg_gen_shri_i64 tcg_gen_shri_i64_riscv64 +#define tcg_gen_shri_vec tcg_gen_shri_vec_riscv64 +#define tcg_gen_smax_i32 tcg_gen_smax_i32_riscv64 +#define tcg_gen_smax_i64 tcg_gen_smax_i64_riscv64 +#define tcg_gen_smin_i32 tcg_gen_smin_i32_riscv64 +#define tcg_gen_smin_i64 tcg_gen_smin_i64_riscv64 +#define tcg_gen_st_i32 tcg_gen_st_i32_riscv64 +#define tcg_gen_st_i64 tcg_gen_st_i64_riscv64 +#define tcg_gen_st_vec tcg_gen_st_vec_riscv64 +#define tcg_gen_stl_vec tcg_gen_stl_vec_riscv64 +#define tcg_gen_sub2_i32 tcg_gen_sub2_i32_riscv64 +#define tcg_gen_sub2_i64 tcg_gen_sub2_i64_riscv64 +#define tcg_gen_sub_i32 tcg_gen_sub_i32_riscv64 +#define tcg_gen_sub_i64 tcg_gen_sub_i64_riscv64 +#define tcg_gen_sub_vec tcg_gen_sub_vec_riscv64 +#define tcg_gen_subfi_i32 tcg_gen_subfi_i32_riscv64 +#define tcg_gen_subfi_i64 tcg_gen_subfi_i64_riscv64 +#define tcg_gen_subi_i32 tcg_gen_subi_i32_riscv64 +#define tcg_gen_subi_i64 tcg_gen_subi_i64_riscv64 +#define tcg_gen_umax_i32 tcg_gen_umax_i32_riscv64 +#define tcg_gen_umax_i64 tcg_gen_umax_i64_riscv64 +#define tcg_gen_umin_i32 tcg_gen_umin_i32_riscv64 +#define tcg_gen_umin_i64 tcg_gen_umin_i64_riscv64 +#define tcg_gen_vec_add8_i64 tcg_gen_vec_add8_i64_riscv64 +#define tcg_gen_vec_add16_i64 tcg_gen_vec_add16_i64_riscv64 +#define tcg_gen_vec_add32_i64 tcg_gen_vec_add32_i64_riscv64 +#define tcg_gen_vec_neg8_i64 tcg_gen_vec_neg8_i64_riscv64 +#define tcg_gen_vec_neg16_i64 tcg_gen_vec_neg16_i64_riscv64 +#define tcg_gen_vec_neg32_i64 tcg_gen_vec_neg32_i64_riscv64 +#define tcg_gen_vec_sar8i_i64 tcg_gen_vec_sar8i_i64_riscv64 +#define tcg_gen_vec_sar16i_i64 tcg_gen_vec_sar16i_i64_riscv64 +#define tcg_gen_vec_shl8i_i64 tcg_gen_vec_shl8i_i64_riscv64 +#define tcg_gen_vec_shl16i_i64 tcg_gen_vec_shl16i_i64_riscv64 +#define tcg_gen_vec_shr8i_i64 tcg_gen_vec_shr8i_i64_riscv64 +#define tcg_gen_vec_shr16i_i64 tcg_gen_vec_shr16i_i64_riscv64 +#define tcg_gen_vec_sub8_i64 tcg_gen_vec_sub8_i64_riscv64 +#define tcg_gen_vec_sub16_i64 tcg_gen_vec_sub16_i64_riscv64 +#define tcg_gen_vec_sub32_i64 tcg_gen_vec_sub32_i64_riscv64 +#define tcg_gen_xor_i32 tcg_gen_xor_i32_riscv64 +#define tcg_gen_xor_i64 tcg_gen_xor_i64_riscv64 +#define tcg_gen_xor_vec tcg_gen_xor_vec_riscv64 +#define tcg_gen_xori_i32 tcg_gen_xori_i32_riscv64 +#define tcg_gen_xori_i64 tcg_gen_xori_i64_riscv64 +#define tcg_get_arg_str_i32 tcg_get_arg_str_i32_riscv64 +#define tcg_get_arg_str_i64 tcg_get_arg_str_i64_riscv64 +#define tcg_get_arg_str_idx tcg_get_arg_str_idx_riscv64 +#define tcg_global_mem_new_i32 tcg_global_mem_new_i32_riscv64 +#define tcg_global_mem_new_i64 tcg_global_mem_new_i64_riscv64 +#define tcg_global_mem_new_internal tcg_global_mem_new_internal_riscv64 +#define tcg_global_reg_new_i32 tcg_global_reg_new_i32_riscv64 +#define tcg_global_reg_new_i64 tcg_global_reg_new_i64_riscv64 +#define tcg_global_reg_new_internal tcg_global_reg_new_internal_riscv64 +#define tcg_handle_interrupt tcg_handle_interrupt_riscv64 +#define tcg_init tcg_init_riscv64 +#define tcg_invert_cond tcg_invert_cond_riscv64 +#define tcg_la_bb_end tcg_la_bb_end_riscv64 +#define tcg_la_br_end tcg_la_br_end_riscv64 +#define tcg_la_func_end tcg_la_func_end_riscv64 +#define tcg_liveness_analysis tcg_liveness_analysis_riscv64 +#define tcg_malloc tcg_malloc_riscv64 +#define tcg_malloc_internal tcg_malloc_internal_riscv64 +#define tcg_op_defs_org tcg_op_defs_org_riscv64 +#define tcg_op_insert_after tcg_op_insert_after_riscv64 +#define tcg_op_insert_before tcg_op_insert_before_riscv64 +#define tcg_op_remove tcg_op_remove_riscv64 +#define tcg_op_supported tcg_op_supported_riscv64 +#define tcg_opt_gen_mov tcg_opt_gen_mov_riscv64 +#define tcg_opt_gen_movi tcg_opt_gen_movi_riscv64 +#define tcg_optimize tcg_optimize_riscv64 +#define tcg_out16 tcg_out16_riscv64 +#define tcg_out32 tcg_out32_riscv64 +#define tcg_out64 tcg_out64_riscv64 +#define tcg_out8 tcg_out8_riscv64 +#define tcg_out_addi tcg_out_addi_riscv64 +#define tcg_out_branch tcg_out_branch_riscv64 +#define tcg_out_brcond32 tcg_out_brcond32_riscv64 +#define tcg_out_brcond64 tcg_out_brcond64_riscv64 +#define tcg_out_bswap32 tcg_out_bswap32_riscv64 +#define tcg_out_bswap64 tcg_out_bswap64_riscv64 +#define tcg_out_call tcg_out_call_riscv64 +#define tcg_out_cmp tcg_out_cmp_riscv64 +#define tcg_out_ext16s tcg_out_ext16s_riscv64 +#define tcg_out_ext16u tcg_out_ext16u_riscv64 +#define tcg_out_ext32s tcg_out_ext32s_riscv64 +#define tcg_out_ext32u tcg_out_ext32u_riscv64 +#define tcg_out_ext8s tcg_out_ext8s_riscv64 +#define tcg_out_ext8u tcg_out_ext8u_riscv64 +#define tcg_out_jmp tcg_out_jmp_riscv64 +#define tcg_out_jxx tcg_out_jxx_riscv64 +#define tcg_out_label tcg_out_label_riscv64 +#define tcg_out_ld tcg_out_ld_riscv64 +#define tcg_out_modrm tcg_out_modrm_riscv64 +#define tcg_out_modrm_offset tcg_out_modrm_offset_riscv64 +#define tcg_out_modrm_sib_offset tcg_out_modrm_sib_offset_riscv64 +#define tcg_out_mov tcg_out_mov_riscv64 +#define tcg_out_movcond32 tcg_out_movcond32_riscv64 +#define tcg_out_movcond64 tcg_out_movcond64_riscv64 +#define tcg_out_movi tcg_out_movi_riscv64 +#define tcg_out_op tcg_out_op_riscv64 +#define tcg_out_pop tcg_out_pop_riscv64 +#define tcg_out_push tcg_out_push_riscv64 +#define tcg_out_qemu_ld tcg_out_qemu_ld_riscv64 +#define tcg_out_qemu_ld_direct tcg_out_qemu_ld_direct_riscv64 +#define tcg_out_qemu_ld_slow_path tcg_out_qemu_ld_slow_path_riscv64 +#define tcg_out_qemu_st tcg_out_qemu_st_riscv64 +#define tcg_out_qemu_st_direct tcg_out_qemu_st_direct_riscv64 +#define tcg_out_qemu_st_slow_path tcg_out_qemu_st_slow_path_riscv64 +#define tcg_out_reloc tcg_out_reloc_riscv64 +#define tcg_out_rolw_8 tcg_out_rolw_8_riscv64 +#define tcg_out_setcond32 tcg_out_setcond32_riscv64 +#define tcg_out_setcond64 tcg_out_setcond64_riscv64 +#define tcg_out_shifti tcg_out_shifti_riscv64 +#define tcg_out_st tcg_out_st_riscv64 +#define tcg_out_tb_finalize tcg_out_tb_finalize_riscv64 +#define tcg_out_tb_init tcg_out_tb_init_riscv64 +#define tcg_out_tlb_load tcg_out_tlb_load_riscv64 +#define tcg_out_vex_modrm tcg_out_vex_modrm_riscv64 +#define tcg_patch32 tcg_patch32_riscv64 +#define tcg_patch8 tcg_patch8_riscv64 +#define tcg_pcrel_diff tcg_pcrel_diff_riscv64 +#define tcg_pool_reset tcg_pool_reset_riscv64 +#define tcg_prologue_init tcg_prologue_init_riscv64 +#define tcg_ptr_byte_diff tcg_ptr_byte_diff_riscv64 +#define tcg_reg_alloc tcg_reg_alloc_riscv64 +#define tcg_reg_alloc_bb_end tcg_reg_alloc_bb_end_riscv64 +#define tcg_reg_alloc_call tcg_reg_alloc_call_riscv64 +#define tcg_reg_alloc_mov tcg_reg_alloc_mov_riscv64 +#define tcg_reg_alloc_movi tcg_reg_alloc_movi_riscv64 +#define tcg_reg_alloc_op tcg_reg_alloc_op_riscv64 +#define tcg_reg_alloc_start tcg_reg_alloc_start_riscv64 +#define tcg_reg_free tcg_reg_free_riscv64 +#define tcg_reg_sync tcg_reg_sync_riscv64 +#define tcg_set_frame tcg_set_frame_riscv64 +#define tcg_set_nop tcg_set_nop_riscv64 +#define tcg_swap_cond tcg_swap_cond_riscv64 +#define tcg_target_call_iarg_regs tcg_target_call_iarg_regs_riscv64 +#define tcg_target_call_oarg_regs tcg_target_call_oarg_regs_riscv64 +#define tcg_target_callee_save_regs tcg_target_callee_save_regs_riscv64 +#define tcg_target_const_match tcg_target_const_match_riscv64 +#define tcg_target_deposit_valid tcg_target_deposit_valid_riscv64 +#define tcg_target_init tcg_target_init_riscv64 +#define tcg_target_qemu_prologue tcg_target_qemu_prologue_riscv64 +#define tcg_target_reg_alloc_order tcg_target_reg_alloc_order_riscv64 +#define tcg_tb_alloc tcg_tb_alloc_riscv64 +#define tcg_temp_alloc tcg_temp_alloc_riscv64 +#define tcg_temp_free_internal tcg_temp_free_internal_riscv64 +#define tcg_temp_local_new_i32 tcg_temp_local_new_i32_riscv64 +#define tcg_temp_local_new_i64 tcg_temp_local_new_i64_riscv64 +#define tcg_temp_new_i32 tcg_temp_new_i32_riscv64 +#define tcg_temp_new_i64 tcg_temp_new_i64_riscv64 +#define tcg_temp_new_internal tcg_temp_new_internal_riscv64 +#define tcg_temp_new_vec tcg_temp_new_vec_riscv64 +#define tcg_temp_new_vec_matching tcg_temp_new_vec_matching_riscv64 +#define tdb_hash tdb_hash_riscv64 +#define teecr_write teecr_write_riscv64 +#define teehbr_access teehbr_access_riscv64 +#define temp_allocate_frame temp_allocate_frame_riscv64 +#define temp_dead temp_dead_riscv64 +#define temp_save temp_save_riscv64 +#define temp_sync temp_sync_riscv64 +#define temps_are_copies temps_are_copies_riscv64 +#define tgen_arithi tgen_arithi_riscv64 +#define tgen_arithr tgen_arithr_riscv64 +#define thumb2_logic_op thumb2_logic_op_riscv64 +#define ti925t_initfn ti925t_initfn_riscv64 +#define tlb_add_large_page tlb_add_large_page_riscv64 +#define tlb_fill tlb_fill_riscv64 +#define tlb_flush tlb_flush_riscv64 +#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_riscv64 +#define tlb_flush_entry tlb_flush_entry_riscv64 +#define tlb_flush_page tlb_flush_page_riscv64 +#define tlb_flush_page_by_mmuidx tlb_flush_page_by_mmuidx_riscv64 +#define tlb_is_dirty_ram tlb_is_dirty_ram_riscv64 +#define tlb_reset_dirty tlb_reset_dirty_riscv64 +#define tlb_reset_dirty_range tlb_reset_dirty_range_riscv64 +#define tlb_set_dirty tlb_set_dirty_riscv64 +#define tlb_set_page tlb_set_page_riscv64 +#define tlb_set_page_with_attrs tlb_set_page_with_attrs_riscv64 +#define tlb_vaddr_to_host tlb_vaddr_to_host_riscv64 +#define tlbi_aa64_asid_is_write tlbi_aa64_asid_is_write_riscv64 +#define tlbi_aa64_asid_write tlbi_aa64_asid_write_riscv64 +#define tlbi_aa64_va_is_write tlbi_aa64_va_is_write_riscv64 +#define tlbi_aa64_va_write tlbi_aa64_va_write_riscv64 +#define tlbi_aa64_vaa_is_write tlbi_aa64_vaa_is_write_riscv64 +#define tlbi_aa64_vaa_write tlbi_aa64_vaa_write_riscv64 +#define tlbiall_is_write tlbiall_is_write_riscv64 +#define tlbiall_write tlbiall_write_riscv64 +#define tlbiasid_is_write tlbiasid_is_write_riscv64 +#define tlbiasid_write tlbiasid_write_riscv64 +#define tlbimva_is_write tlbimva_is_write_riscv64 +#define tlbimva_write tlbimva_write_riscv64 +#define tlbimvaa_is_write tlbimvaa_is_write_riscv64 +#define tlbimvaa_write tlbimvaa_write_riscv64 +#define to_qiv to_qiv_riscv64 +#define to_qov to_qov_riscv64 +#define token_get_type token_get_type_riscv64 +#define token_get_value token_get_value_riscv64 +#define token_is_escape token_is_escape_riscv64 +#define token_is_keyword token_is_keyword_riscv64 +#define token_is_operator token_is_operator_riscv64 +#define tokens_append_from_iter tokens_append_from_iter_riscv64 +#define tosa_init tosa_init_riscv64 +#define tosa_machine_init_register_types tosa_machine_init_register_types_riscv64 +#define translator_loop translator_loop_riscv64 +#define translator_loop_temp_check translator_loop_temp_check_riscv64 +#define tswap32 tswap32_riscv64 +#define tswap64 tswap64_riscv64 +#define type_class_get_size type_class_get_size_riscv64 +#define type_get_by_name type_get_by_name_riscv64 +#define type_get_parent type_get_parent_riscv64 +#define type_has_parent type_has_parent_riscv64 +#define type_initialize type_initialize_riscv64 +#define type_initialize_interface type_initialize_interface_riscv64 +#define type_is_ancestor type_is_ancestor_riscv64 +#define type_new type_new_riscv64 +#define type_object_get_size type_object_get_size_riscv64 +#define type_register_internal type_register_internal_riscv64 +#define type_table_add type_table_add_riscv64 +#define type_table_get type_table_get_riscv64 +#define type_table_lookup type_table_lookup_riscv64 +#define uint16_to_float16 uint16_to_float16_riscv64 +#define uint16_to_float16_scalbn uint16_to_float16_scalbn_riscv64 +#define uint16_to_float32 uint16_to_float32_riscv64 +#define uint16_to_float32_scalbn uint16_to_float32_scalbn_riscv64 +#define uint16_to_float64 uint16_to_float64_riscv64 +#define uint16_to_float64_scalbn uint16_to_float64_scalbn_riscv64 +#define uint32_to_float16 uint32_to_float16_riscv64 +#define uint32_to_float16_scalbn uint32_to_float16_scalbn_riscv64 +#define uint32_to_float32 uint32_to_float32_riscv64 +#define uint32_to_float32_scalbn uint32_to_float32_scalbn_riscv64 +#define uint32_to_float64 uint32_to_float64_riscv64 +#define uint32_to_float64_scalbn uint32_to_float64_scalbn_riscv64 +#define uint64_to_float128 uint64_to_float128_riscv64 +#define uint64_to_float16 uint64_to_float16_riscv64 +#define uint64_to_float16_scalbn uint64_to_float16_scalbn_riscv64 +#define uint64_to_float32 uint64_to_float32_riscv64 +#define uint64_to_float32_scalbn uint64_to_float32_scalbn_riscv64 +#define uint64_to_float64 uint64_to_float64_riscv64 +#define uint64_to_float64_scalbn uint64_to_float64_scalbn_riscv64 +#define unassigned_io_ops unassigned_io_ops_riscv64 +#define unassigned_io_read unassigned_io_read_riscv64 +#define unassigned_io_write unassigned_io_write_riscv64 +#define unassigned_mem_accepts unassigned_mem_accepts_riscv64 +#define unassigned_mem_ops unassigned_mem_ops_riscv64 +#define unassigned_mem_read unassigned_mem_read_riscv64 +#define unassigned_mem_write unassigned_mem_write_riscv64 +#define unicorn_free_empty_flat_view unicorn_free_empty_flat_view_riscv64 +#define update_spsel update_spsel_riscv64 +#define use_idiv_instructions_rt use_idiv_instructions_rt_riscv64 +#define v6_cp_reginfo v6_cp_reginfo_riscv64 +#define v6k_cp_reginfo v6k_cp_reginfo_riscv64 +#define v7_cp_reginfo v7_cp_reginfo_riscv64 +#define v7m_pop v7m_pop_riscv64 +#define v7m_push v7m_push_riscv64 +#define v7mp_cp_reginfo v7mp_cp_reginfo_riscv64 +#define v8_cp_reginfo v8_cp_reginfo_riscv64 +#define v8_el2_cp_reginfo v8_el2_cp_reginfo_riscv64 +#define v8_el3_cp_reginfo v8_el3_cp_reginfo_riscv64 +#define v8_el3_no_el2_cp_reginfo v8_el3_no_el2_cp_reginfo_riscv64 +#define vapa_cp_reginfo vapa_cp_reginfo_riscv64 +#define vbar_write vbar_write_riscv64 +#define vec_gen_2 vec_gen_2_riscv64 +#define vec_gen_3 vec_gen_3_riscv64 +#define vec_gen_4 vec_gen_4_riscv64 +#define vfp_exceptbits_from_host vfp_exceptbits_from_host_riscv64 +#define vfp_exceptbits_to_host vfp_exceptbits_to_host_riscv64 +#define vfp_get_fpcr vfp_get_fpcr_riscv64 +#define vfp_get_fpscr vfp_get_fpscr_riscv64 +#define vfp_get_fpsr vfp_get_fpsr_riscv64 +#define vfp_reg_offset vfp_reg_offset_riscv64 +#define vfp_set_fpcr vfp_set_fpcr_riscv64 +#define vfp_set_fpscr vfp_set_fpscr_riscv64 +#define vfp_set_fpsr vfp_set_fpsr_riscv64 +#define visit_end_implicit_struct visit_end_implicit_struct_riscv64 +#define visit_end_list visit_end_list_riscv64 +#define visit_end_struct visit_end_struct_riscv64 +#define visit_end_union visit_end_union_riscv64 +#define visit_get_next_type visit_get_next_type_riscv64 +#define visit_next_list visit_next_list_riscv64 +#define visit_optional visit_optional_riscv64 +#define visit_start_implicit_struct visit_start_implicit_struct_riscv64 +#define visit_start_list visit_start_list_riscv64 +#define visit_start_struct visit_start_struct_riscv64 +#define visit_start_union visit_start_union_riscv64 +#define vm_start vm_start_riscv64 +#define vmsa_cp_reginfo vmsa_cp_reginfo_riscv64 +#define vmsa_tcr_el1_write vmsa_tcr_el1_write_riscv64 +#define vmsa_ttbcr_raw_write vmsa_ttbcr_raw_write_riscv64 +#define vmsa_ttbcr_reset vmsa_ttbcr_reset_riscv64 +#define vmsa_ttbcr_write vmsa_ttbcr_write_riscv64 +#define vmsa_ttbr_write vmsa_ttbr_write_riscv64 +#define write_cpustate_to_list write_cpustate_to_list_riscv64 +#define write_list_to_cpustate write_list_to_cpustate_riscv64 +#define write_raw_cp_reg write_raw_cp_reg_riscv64 +#define write_v7m_exception write_v7m_exception_riscv64 +#define x86_ldl_phys x86_ldl_phys_riscv64 +#define x86_ldq_phys x86_ldq_phys_riscv64 +#define x86_ldub_phys x86_ldub_phys_riscv64 +#define x86_lduw_phys x86_lduw_phys_riscv64 +#define x86_op_defs x86_op_defs_riscv64 +#define x86_stb_phys x86_stb_phys_riscv64 +#define x86_stl_phys x86_stl_phys_riscv64 +#define x86_stl_phys_notdirty x86_stl_phys_notdirty_riscv64 +#define x86_stq_phys x86_stq_phys_riscv64 +#define x86_stw_phys x86_stw_phys_riscv64 +#define xpsr_read xpsr_read_riscv64 +#define xpsr_write xpsr_write_riscv64 +#define xscale_cp_reginfo xscale_cp_reginfo_riscv64 +#define xscale_cpar_write xscale_cpar_write_riscv64 +#define RISCV32_REGS_STORAGE_SIZE RISCV32_REGS_STORAGE_SIZE_riscv64 +#define RISCV64_REGS_STORAGE_SIZE RISCV64_REGS_STORAGE_SIZE_riscv64 +#define cpu_riscv_get_fflags cpu_riscv_get_fflags_riscv64 +#define cpu_riscv_set_fflags cpu_riscv_set_fflags_riscv64 +#define csr_read_helper csr_read_helper_riscv64 +#define csr_write_helper csr_write_helper_riscv64 +#define do_raise_exception_err do_raise_exception_err_riscv64 +#define helper_csrrc helper_csrrc_riscv64 +#define helper_csrrs helper_csrrs_riscv64 +#define helper_csrrw helper_csrrw_riscv64 +#define helper_fadd_d helper_fadd_d_riscv64 +#define helper_fadd_s helper_fadd_s_riscv64 +#define helper_fclass_d helper_fclass_d_riscv64 +#define helper_fclass_s helper_fclass_s_riscv64 +#define helper_fcvt_d_s helper_fcvt_d_s_riscv64 +#define helper_fcvt_d_w helper_fcvt_d_w_riscv64 +#define helper_fcvt_d_wu helper_fcvt_d_wu_riscv64 +#define helper_fcvt_s_d helper_fcvt_s_d_riscv64 +#define helper_fcvt_s_w helper_fcvt_s_w_riscv64 +#define helper_fcvt_s_wu helper_fcvt_s_wu_riscv64 +#define helper_fcvt_w_d helper_fcvt_w_d_riscv64 +#define helper_fcvt_w_s helper_fcvt_w_s_riscv64 +#define helper_fcvt_wu_d helper_fcvt_wu_d_riscv64 +#define helper_fcvt_wu_s helper_fcvt_wu_s_riscv64 +#define helper_fdiv_d helper_fdiv_d_riscv64 +#define helper_fdiv_s helper_fdiv_s_riscv64 +#define helper_feq_d helper_feq_d_riscv64 +#define helper_feq_s helper_feq_s_riscv64 +#define helper_fle_d helper_fle_d_riscv64 +#define helper_fle_s helper_fle_s_riscv64 +#define helper_flt_d helper_flt_d_riscv64 +#define helper_flt_s helper_flt_s_riscv64 +#define helper_fmadd_d helper_fmadd_d_riscv64 +#define helper_fmadd_s helper_fmadd_s_riscv64 +#define helper_fmsub_d helper_fmsub_d_riscv64 +#define helper_fmsub_s helper_fmsub_s_riscv64 +#define helper_fmax_d helper_fmax_d_riscv64 +#define helper_fmax_s helper_fmax_s_riscv64 +#define helper_fmin_d helper_fmin_d_riscv64 +#define helper_fmin_s helper_fmin_s_riscv64 +#define helper_fmul_d helper_fmul_d_riscv64 +#define helper_fmul_s helper_fmul_s_riscv64 +#define helper_fnmadd_d helper_fnmadd_d_riscv64 +#define helper_fnmadd_s helper_fnmadd_s_riscv64 +#define helper_fnmsub_d helper_fnmsub_d_riscv64 +#define helper_fnmsub_s helper_fnmsub_s_riscv64 +#define helper_fsqrt_d helper_fsqrt_d_riscv64 +#define helper_fsqrt_s helper_fsqrt_s_riscv64 +#define helper_fsub_d helper_fsub_d_riscv64 +#define helper_fsub_s helper_fsub_s_riscv64 +#define helper_mret helper_mret_riscv64 +#define helper_riscv_tlb_flush helper_riscv_tlb_flush_riscv64 +#define helper_set_rounding_mode helper_set_rounding_mode_riscv64 +#define helper_sret helper_sret_riscv64 +#define pmp_hart_has_privs pmp_hart_has_privs_riscv64 +#define pmpaddr_csr_read pmpaddr_csr_read_riscv64 +#define pmpaddr_csr_write pmpaddr_csr_write_riscv64 +#define pmpcfg_csr_read pmpcfg_csr_read_riscv64 +#define pmpcfg_csr_write pmpcfg_csr_write_riscv64 +#define riscv_cpu_do_interrupt riscv_cpu_do_interrupt_riscv64 +#define riscv_cpu_do_unaligned_access riscv_cpu_do_unaligned_access_riscv64 +#define riscv_cpu_exec_interrupt riscv_cpu_exec_interrupt_riscv64 +#define riscv_cpu_get_phys_page_debug riscv_cpu_get_phys_page_debug_riscv64 +#define riscv_cpu_handle_mmu_fault riscv_cpu_handle_mmu_fault_riscv64 +#define riscv_cpu_list riscv_cpu_list_riscv64 +#define riscv_cpu_mmu_index riscv_cpu_mmu_index_riscv64 +#define riscv_cpu_register_types riscv_cpu_register_types_riscv64 +#define riscv_excp_names riscv_excp_names_riscv64 +#define riscv_fpr_regnames riscv_fpr_regnames_riscv64 +#define riscv_int_regnames riscv_int_regnames_riscv64 +#define riscv_intr_names riscv_intr_names_riscv64 +#define riscv_isa_string riscv_isa_string_riscv64 +#define riscv_set_local_interrupt riscv_set_local_interrupt_riscv64 +#define riscv_set_mode riscv_set_mode_riscv64 +#define riscv_translate_init riscv_translate_init_riscv64 +#define spike_v1_10_0_machine_init_register_types spike_v1_10_0_machine_init_register_types_riscv64 +#endif diff --git a/qemu/sparc.h b/qemu/sparc.h index 5699103c..aea45035 100644 --- a/qemu/sparc.h +++ b/qemu/sparc.h @@ -217,7 +217,6 @@ #define clz32 clz32_sparc #define clz64 clz64_sparc #define cmp_flatrange_addr cmp_flatrange_addr_sparc -#define code_gen_alloc code_gen_alloc_sparc #define commonNaNToFloat128 commonNaNToFloat128_sparc #define commonNaNToFloat16 commonNaNToFloat16_sparc #define commonNaNToFloat32 commonNaNToFloat32_sparc @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_sparc #define cpu_exec_step_atomic cpu_exec_step_atomic_sparc #define cpu_flush_icache_range cpu_flush_icache_range_sparc -#define cpu_gen_init cpu_gen_init_sparc #define cpu_get_address_space cpu_get_address_space_sparc #define cpu_get_clock cpu_get_clock_sparc #define cpu_get_real_ticks cpu_get_real_ticks_sparc diff --git a/qemu/sparc64.h b/qemu/sparc64.h index 9f3bec1e..d7277d90 100644 --- a/qemu/sparc64.h +++ b/qemu/sparc64.h @@ -217,7 +217,6 @@ #define clz32 clz32_sparc64 #define clz64 clz64_sparc64 #define cmp_flatrange_addr cmp_flatrange_addr_sparc64 -#define code_gen_alloc code_gen_alloc_sparc64 #define commonNaNToFloat128 commonNaNToFloat128_sparc64 #define commonNaNToFloat16 commonNaNToFloat16_sparc64 #define commonNaNToFloat32 commonNaNToFloat32_sparc64 @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_sparc64 #define cpu_exec_step_atomic cpu_exec_step_atomic_sparc64 #define cpu_flush_icache_range cpu_flush_icache_range_sparc64 -#define cpu_gen_init cpu_gen_init_sparc64 #define cpu_get_address_space cpu_get_address_space_sparc64 #define cpu_get_clock cpu_get_clock_sparc64 #define cpu_get_real_ticks cpu_get_real_ticks_sparc64 diff --git a/qemu/target/riscv/Makefile.objs b/qemu/target/riscv/Makefile.objs new file mode 100644 index 00000000..cbe112a8 --- /dev/null +++ b/qemu/target/riscv/Makefile.objs @@ -0,0 +1,2 @@ +obj-y += translate.o op_helper.o helper.o cpu.o fpu_helper.o pmp.o +obj-y += unicorn.o diff --git a/qemu/target/riscv/cpu.c b/qemu/target/riscv/cpu.c new file mode 100644 index 00000000..ccf1ac7f --- /dev/null +++ b/qemu/target/riscv/cpu.c @@ -0,0 +1,441 @@ +/* + * QEMU RISC-V CPU + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "qapi/error.h" + +#include "hw/riscv/spike.h" +#include "uc_priv.h" + +/* RISC-V CPU definitions */ + +static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; + +const char * const riscv_int_regnames[] = { + "zero", "ra ", "sp ", "gp ", "tp ", "t0 ", "t1 ", "t2 ", + "s0 ", "s1 ", "a0 ", "a1 ", "a2 ", "a3 ", "a4 ", "a5 ", + "a6 ", "a7 ", "s2 ", "s3 ", "s4 ", "s5 ", "s6 ", "s7 ", + "s8 ", "s9 ", "s10 ", "s11 ", "t3 ", "t4 ", "t5 ", "t6 " +}; + +const char * const riscv_fpr_regnames[] = { + "ft0 ", "ft1 ", "ft2 ", "ft3 ", "ft4 ", "ft5 ", "ft6 ", "ft7 ", + "fs0 ", "fs1 ", "fa0 ", "fa1 ", "fa2 ", "fa3 ", "fa4 ", "fa5 ", + "fa6 ", "fa7 ", "fs2 ", "fs3 ", "fs4 ", "fs5 ", "fs6 ", "fs7 ", + "fs8 ", "fs9 ", "fs10", "fs11", "ft8 ", "ft9 ", "ft10", "ft11" +}; + +const char * const riscv_excp_names[] = { + "misaligned_fetch", + "fault_fetch", + "illegal_instruction", + "breakpoint", + "misaligned_load", + "fault_load", + "misaligned_store", + "fault_store", + "user_ecall", + "supervisor_ecall", + "hypervisor_ecall", + "machine_ecall", + "exec_page_fault", + "load_page_fault", + "reserved", + "store_page_fault" +}; + +const char * const riscv_intr_names[] = { + "u_software", + "s_software", + "h_software", + "m_software", + "u_timer", + "s_timer", + "h_timer", + "m_timer", + "u_external", + "s_external", + "h_external", + "m_external", + "coprocessor", + "host" +}; + +typedef struct RISCVCPUInfo { + const int bit_widths; + const char *name; + void (*initfn)(Object *obj); +} RISCVCPUInfo; + +static void set_misa(CPURISCVState *env, target_ulong misa) +{ + env->misa = misa; +} + +static void set_versions(CPURISCVState *env, int user_ver, int priv_ver) +{ + env->user_ver = user_ver; + env->priv_ver = priv_ver; +} + +static void set_feature(CPURISCVState *env, int feature) +{ + env->features |= (1ULL << feature); +} + +static void set_resetvec(CPURISCVState *env, int resetvec) +{ +#ifndef CONFIG_USER_ONLY + env->resetvec = resetvec; +#endif +} + +static void riscv_any_cpu_init(struct uc_struct *uc, Object *obj, void *data) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); +} + +#if defined(TARGET_RISCV32) + +static void rv32gcsu_priv1_09_1_cpu_init(struct uc_struct *uc, Object *obj, void *data) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_MMU); +} + +static void rv32gcsu_priv1_10_0_cpu_init(struct uc_struct *uc, Object *obj, void *data) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_MMU); +} + +static void rv32imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *data) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); +} + +#elif defined(TARGET_RISCV64) + +static void rv64gcsu_priv1_09_1_cpu_init(struct uc_struct *uc, Object *obj, void *data) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_MMU); +} + +static void rv64gcsu_priv1_10_0_cpu_init(struct uc_struct *uc, Object *obj, void *data) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); + set_feature(env, RISCV_FEATURE_MMU); +} + +static void rv64imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *data) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU); + set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0); + set_resetvec(env, DEFAULT_RSTVEC); +} + +#endif + +static ObjectClass *riscv_cpu_class_by_name(struct uc_struct *uc, const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + char **cpuname; + + cpuname = g_strsplit(cpu_model, ",", 1); + typename = g_strdup_printf(RISCV_CPU_TYPE_NAME("%s"), cpuname[0]); + oc = object_class_by_name(uc, typename); + g_strfreev(cpuname); + g_free(typename); + if (!oc || !object_class_dynamic_cast(uc, oc, TYPE_RISCV_CPU) || + object_class_is_abstract(oc)) { + return NULL; + } + return oc; +} + +static void riscv_cpu_dump_state(CPUState *cs, FILE *f, + fprintf_function cpu_fprintf, int flags) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + int i; + + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "pc ", env->pc); +#ifndef CONFIG_USER_ONLY + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mhartid ", env->mhartid); + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mstatus ", env->mstatus); + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mip ", + (target_ulong)atomic_read(&env->mip)); + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mie ", env->mie); + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mideleg ", env->mideleg); + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "medeleg ", env->medeleg); + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mtvec ", env->mtvec); + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mepc ", env->mepc); + cpu_fprintf(f, " %s " TARGET_FMT_lx "\n", "mcause ", env->mcause); +#endif + + for (i = 0; i < 32; i++) { + cpu_fprintf(f, " %s " TARGET_FMT_lx, + riscv_int_regnames[i], env->gpr[i]); + if ((i & 3) == 3) { + cpu_fprintf(f, "\n"); + } + } + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < 32; i++) { + cpu_fprintf(f, " %s %016" PRIx64, + riscv_fpr_regnames[i], env->fpr[i]); + if ((i & 3) == 3) { + cpu_fprintf(f, "\n"); + } + } + } +} + +static void riscv_cpu_set_pc(CPUState *cs, vaddr value) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + env->pc = value; +} + +static void riscv_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + env->pc = tb->pc; +} + +static bool riscv_cpu_has_work(CPUState *cs) +{ +#ifndef CONFIG_USER_ONLY + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + /* + * Definition of the WFI instruction requires it to ignore the privilege + * mode and delegation registers, but respect individual enables + */ + return (atomic_read(&env->mip) & env->mie) != 0; +#else + return true; +#endif +} + +void restore_state_to_opc(CPURISCVState *env, TranslationBlock *tb, + target_ulong *data) +{ + env->pc = data[0]; +} + +static void riscv_cpu_reset(CPUState *cs) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cpu->env.uc, cpu); + CPURISCVState *env = &cpu->env; + + mcc->parent_reset(cs); +#ifndef CONFIG_USER_ONLY + env->priv = PRV_M; + env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); + env->mcause = 0; + env->pc = env->resetvec; +#endif + cs->exception_index = EXCP_NONE; + set_default_nan_mode(1, &env->fp_status); +} + +static int riscv_cpu_realize(struct uc_struct *uc, DeviceState *dev, Error **errp) +{ + CPUState *cs = CPU(dev); + RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(uc, dev); + + qemu_init_vcpu(cs); + cpu_reset(cs); + + mcc->parent_realize(uc, dev, errp); + return 0; +} + +static void riscv_cpu_init(struct uc_struct *uc, Object *obj, void *opaque) +{ + CPUState *cs = CPU(obj); + RISCVCPU *cpu = RISCV_CPU(obj); + + cs->env_ptr = &cpu->env; + cpu_exec_init(cs, &error_abort, opaque); +} + +static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data) +{ + RISCVCPUClass *mcc = RISCV_CPU_CLASS(uc, c); + CPUClass *cc = CPU_CLASS(uc, c); + DeviceClass *dc = DEVICE_CLASS(uc, c); + + mcc->parent_realize = dc->realize; + dc->realize = riscv_cpu_realize; + + mcc->parent_reset = cc->reset; + cc->reset = riscv_cpu_reset; + + cc->class_by_name = riscv_cpu_class_by_name; + cc->has_work = riscv_cpu_has_work; + cc->do_interrupt = riscv_cpu_do_interrupt; + cc->cpu_exec_interrupt = riscv_cpu_exec_interrupt; + cc->dump_state = riscv_cpu_dump_state; + cc->set_pc = riscv_cpu_set_pc; + cc->synchronize_from_tb = riscv_cpu_synchronize_from_tb; +#ifdef CONFIG_USER_ONLY + cc->handle_mmu_fault = riscv_cpu_handle_mmu_fault; +#else + cc->do_unaligned_access = riscv_cpu_do_unaligned_access; + cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; +#endif +#ifdef CONFIG_TCG + cc->tcg_initialize = riscv_translate_init; +#endif +} + +char *riscv_isa_string(RISCVCPU *cpu) +{ + int i; + const size_t maxlen = sizeof("rv128") + sizeof(riscv_exts) + 1; + char *isa_str = g_new(char, maxlen); + char *p = isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BITS); + for (i = 0; i < sizeof(riscv_exts); i++) { + if (cpu->env.misa & RV(riscv_exts[i])) { + *p++ = qemu_tolower(riscv_exts[i]); + } + } + *p = '\0'; + return isa_str; +} + +/* Unicorn: commented out +typedef struct RISCVCPUListState { + fprintf_function cpu_fprintf; + FILE *file; +} RISCVCPUListState; + +static gint riscv_cpu_list_compare(gconstpointer a, gconstpointer b) +{ + ObjectClass *class_a = (ObjectClass *)a; + ObjectClass *class_b = (ObjectClass *)b; + const char *name_a, *name_b; + + name_a = object_class_get_name(class_a); + name_b = object_class_get_name(class_b); + return strcmp(name_a, name_b); +} + +static void riscv_cpu_list_entry(gpointer data, gpointer user_data) +{ + RISCVCPUListState *s = user_data; + const char *typename = object_class_get_name(OBJECT_CLASS(data)); + int len = strlen(typename) - strlen(RISCV_CPU_TYPE_SUFFIX); + + (*s->cpu_fprintf)(s->file, "%.*s\n", len, typename); +} +*/ + +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf) +{ + /* Unicorn: Commented out + RISCVCPUListState s = { + .cpu_fprintf = cpu_fprintf, + .file = f, + }; + GSList *list; + + list = object_class_get_list(TYPE_RISCV_CPU, false); + list = g_slist_sort(list, riscv_cpu_list_compare); + g_slist_foreach(list, riscv_cpu_list_entry, &s); + g_slist_free(list);*/ +} + +#define DEFINE_CPU(type_name, initfn) \ + { \ + .name = type_name, \ + .parent = TYPE_RISCV_CPU, \ + .instance_init = initfn \ + } + +static const TypeInfo riscv_cpu_type_infos[] = { + { + .name = TYPE_RISCV_CPU, + .parent = TYPE_CPU, + .instance_size = sizeof(RISCVCPU), + .instance_init = riscv_cpu_init, + .abstract = true, + .class_size = sizeof(RISCVCPUClass), + .class_init = riscv_cpu_class_init, + }, + DEFINE_CPU(TYPE_RISCV_CPU_ANY, riscv_any_cpu_init), +#if defined(TARGET_RISCV32) + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init) +#elif defined(TARGET_RISCV64) + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), + DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init) +#endif +}; + +// Unicorn: Commented out to manually initialize types with the function below it. +//DEFINE_TYPES(riscv_cpu_type_infos) + +void riscv_cpu_register_types(void *opaque) +{ + TypeInfo riscv_cpu_type_info = riscv_cpu_type_infos[0]; + riscv_cpu_type_info.instance_userdata = opaque, + + type_register(opaque, &riscv_cpu_type_info); + + for (int i = 1; i < ARRAY_SIZE(riscv_cpu_type_infos); i++) { + type_register(opaque, &riscv_cpu_type_infos[i]); + } +} diff --git a/qemu/target/riscv/cpu.h b/qemu/target/riscv/cpu.h new file mode 100644 index 00000000..7b577ce3 --- /dev/null +++ b/qemu/target/riscv/cpu.h @@ -0,0 +1,300 @@ +/* + * QEMU RISC-V CPU + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef RISCV_CPU_H +#define RISCV_CPU_H + +/* QEMU addressing/paging config */ +#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */ +#if defined(TARGET_RISCV64) +#define TARGET_LONG_BITS 64 +#define TARGET_PHYS_ADDR_SPACE_BITS 56 /* 44-bit PPN */ +#define TARGET_VIRT_ADDR_SPACE_BITS 48 /* sv48 */ +#elif defined(TARGET_RISCV32) +#define TARGET_LONG_BITS 32 +#define TARGET_PHYS_ADDR_SPACE_BITS 34 /* 22-bit PPN */ +#define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */ +#endif + +#define TCG_GUEST_DEFAULT_MO 0 + +#define CPUArchState struct CPURISCVState + +#include "config.h" +#include "qemu-common.h" +#include "qom/cpu.h" +#include "exec/cpu-defs.h" +#include "fpu/softfloat.h" + +#define TYPE_RISCV_CPU "riscv-cpu" + +#define RISCV_CPU_TYPE_SUFFIX "-" TYPE_RISCV_CPU +#define RISCV_CPU_TYPE_NAME(name) (name RISCV_CPU_TYPE_SUFFIX) +#define CPU_RESOLVING_TYPE TYPE_RISCV_CPU + +#define TYPE_RISCV_CPU_ANY RISCV_CPU_TYPE_NAME("any") +#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1") +#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0") +#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu") +#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1") +#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0") +#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu") +#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31") +#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") +#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") +#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") + +#define RV32 ((target_ulong)1 << (TARGET_LONG_BITS - 2)) +#define RV64 ((target_ulong)2 << (TARGET_LONG_BITS - 2)) + +#if defined(TARGET_RISCV32) +#define RVXLEN RV32 +#elif defined(TARGET_RISCV64) +#define RVXLEN RV64 +#endif + +#define RV(x) ((target_ulong)1 << (x - 'A')) + +#define RVI RV('I') +#define RVE RV('E') /* E and I are mutually exclusive */ +#define RVM RV('M') +#define RVA RV('A') +#define RVF RV('F') +#define RVD RV('D') +#define RVC RV('C') +#define RVS RV('S') +#define RVU RV('U') + +/* S extension denotes that Supervisor mode exists, however it is possible + to have a core that support S mode but does not have an MMU and there + is currently no bit in misa to indicate whether an MMU exists or not + so a cpu features bitfield is required */ +enum { + RISCV_FEATURE_MMU +}; + +#define USER_VERSION_2_02_0 0x00020200 +#define PRIV_VERSION_1_09_1 0x00010901 +#define PRIV_VERSION_1_10_0 0x00011000 + +#define TRANSLATE_FAIL 1 +#define TRANSLATE_SUCCESS 0 +#define NB_MMU_MODES 4 +#define MMU_USER_IDX 3 + +#define MAX_RISCV_PMPS (16) + +typedef struct CPURISCVState CPURISCVState; + +#include "pmp.h" + +struct CPURISCVState { + target_ulong gpr[32]; + uint64_t fpr[32]; /* assume both F and D extensions */ + target_ulong pc; + target_ulong load_res; + target_ulong load_val; + + target_ulong frm; + + target_ulong badaddr; + + target_ulong user_ver; + target_ulong priv_ver; + target_ulong misa; + + uint32_t features; + +#ifndef CONFIG_USER_ONLY + target_ulong priv; + target_ulong resetvec; + + target_ulong mhartid; + target_ulong mstatus; + /* + * CAUTION! Unlike the rest of this struct, mip is accessed asynchonously + * by I/O threads and other vCPUs, so hold the iothread mutex before + * operating on it. CPU_INTERRUPT_HARD should be in effect iff this is + * non-zero. Use riscv_cpu_set_local_interrupt. + */ + uint32_t mip; /* allow atomic_read for >= 32-bit hosts */ + target_ulong mie; + target_ulong mideleg; + + target_ulong sptbr; /* until: priv-1.9.1 */ + target_ulong satp; /* since: priv-1.10.0 */ + target_ulong sbadaddr; + target_ulong mbadaddr; + target_ulong medeleg; + + target_ulong stvec; + target_ulong sepc; + target_ulong scause; + + target_ulong mtvec; + target_ulong mepc; + target_ulong mcause; + target_ulong mtval; /* since: priv-1.10.0 */ + + target_ulong scounteren; + target_ulong mcounteren; + + target_ulong sscratch; + target_ulong mscratch; + + /* temporary htif regs */ + uint64_t mfromhost; + uint64_t mtohost; + uint64_t timecmp; + + /* physical memory protection */ + pmp_table_t pmp_state; +#endif + + float_status fp_status; + + /* QEMU */ + CPU_COMMON + + /* Fields from here on are preserved across CPU reset. */ + QEMUTimer *timer; /* Internal timer */ + + // Unicorn engine + struct uc_struct *uc; +}; + +#define RISCV_CPU_CLASS(uc, klass) \ + OBJECT_CLASS_CHECK(uc, RISCVCPUClass, (klass), TYPE_RISCV_CPU) +#define RISCV_CPU(obj) ((RISCVCPU *)obj) +#define RISCV_CPU_GET_CLASS(uc, obj) \ + OBJECT_GET_CLASS(uc, RISCVCPUClass, (obj), TYPE_RISCV_CPU) + +/** + * RISCVCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * + * A RISCV CPU model. + */ +typedef struct RISCVCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + DeviceRealize parent_realize; + void (*parent_reset)(CPUState *cpu); +} RISCVCPUClass; + +/** + * RISCVCPU: + * @env: #CPURISCVState + * + * A RISCV CPU. + */ +typedef struct RISCVCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + CPURISCVState env; +} RISCVCPU; + +static inline RISCVCPU *riscv_env_get_cpu(CPURISCVState *env) +{ + return container_of(env, RISCVCPU, env); +} + +static inline int riscv_has_ext(CPURISCVState *env, target_ulong ext) +{ + return (env->misa & ext) != 0; +} + +static inline bool riscv_feature(CPURISCVState *env, int feature) +{ + return env->features & (1ULL << feature); +} + +#include "cpu_user.h" +#include "cpu_bits.h" + +extern const char * const riscv_int_regnames[]; +extern const char * const riscv_fpr_regnames[]; +extern const char * const riscv_excp_names[]; +extern const char * const riscv_intr_names[]; + +#define ENV_GET_CPU(e) CPU(riscv_env_get_cpu(e)) +#define ENV_OFFSET offsetof(RISCVCPU, env) + +void riscv_cpu_do_interrupt(CPUState *cpu); +int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); +hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); +void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr); +int riscv_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int size, + int rw, int mmu_idx); + +char *riscv_isa_string(RISCVCPU *cpu); +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf); + +#define cpu_signal_handler cpu_riscv_signal_handler +#define cpu_list riscv_cpu_list +// Unicorn: Converted into a function to avoid preprocessor redefinition warnings. +static inline int cpu_mmu_index(CPURISCVState *env, bool ifetch) { + return riscv_cpu_mmu_index(env, ifetch); +} + +void riscv_set_mode(CPURISCVState *env, target_ulong newpriv); + +void riscv_translate_init(struct uc_struct *uc); +RISCVCPU *cpu_riscv_init(const char *cpu_model); +int cpu_riscv_signal_handler(int host_signum, void *pinfo, void *puc); +void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, + uint32_t exception, uintptr_t pc); + +target_ulong cpu_riscv_get_fflags(CPURISCVState *env); +void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong); + +#define TB_FLAGS_MMU_MASK 3 +#define TB_FLAGS_FP_ENABLE MSTATUS_FS + +static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags) +{ + *pc = env->pc; + *cs_base = 0; +#ifdef CONFIG_USER_ONLY + *flags = TB_FLAGS_FP_ENABLE; +#else + *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); +#endif +} + +void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, + target_ulong csrno); +target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno); + +#ifndef CONFIG_USER_ONLY +void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value); +#endif + +#include "exec/cpu-all.h" + +#endif /* RISCV_CPU_H */ diff --git a/qemu/target/riscv/cpu_bits.h b/qemu/target/riscv/cpu_bits.h new file mode 100644 index 00000000..12b47570 --- /dev/null +++ b/qemu/target/riscv/cpu_bits.h @@ -0,0 +1,409 @@ +/* RISC-V ISA constants */ + +#define get_field(reg, mask) (((reg) & \ + (target_ulong)(mask)) / ((mask) & ~((mask) << 1))) +#define set_field(reg, mask, val) (((reg) & ~(target_ulong)(mask)) | \ + (((target_ulong)(val) * ((mask) & ~((mask) << 1))) & \ + (target_ulong)(mask))) + +#define PGSHIFT 12 + +#define FSR_RD_SHIFT 5 +#define FSR_RD (0x7 << FSR_RD_SHIFT) + +#define FPEXC_NX 0x01 +#define FPEXC_UF 0x02 +#define FPEXC_OF 0x04 +#define FPEXC_DZ 0x08 +#define FPEXC_NV 0x10 + +#define FSR_AEXC_SHIFT 0 +#define FSR_NVA (FPEXC_NV << FSR_AEXC_SHIFT) +#define FSR_OFA (FPEXC_OF << FSR_AEXC_SHIFT) +#define FSR_UFA (FPEXC_UF << FSR_AEXC_SHIFT) +#define FSR_DZA (FPEXC_DZ << FSR_AEXC_SHIFT) +#define FSR_NXA (FPEXC_NX << FSR_AEXC_SHIFT) +#define FSR_AEXC (FSR_NVA | FSR_OFA | FSR_UFA | FSR_DZA | FSR_NXA) + +/* CSR numbers */ +#define CSR_FFLAGS 0x1 +#define CSR_FRM 0x2 +#define CSR_FCSR 0x3 +#define CSR_CYCLE 0xc00 +#define CSR_TIME 0xc01 +#define CSR_INSTRET 0xc02 +#define CSR_HPMCOUNTER3 0xc03 +#define CSR_HPMCOUNTER4 0xc04 +#define CSR_HPMCOUNTER5 0xc05 +#define CSR_HPMCOUNTER6 0xc06 +#define CSR_HPMCOUNTER7 0xc07 +#define CSR_HPMCOUNTER8 0xc08 +#define CSR_HPMCOUNTER9 0xc09 +#define CSR_HPMCOUNTER10 0xc0a +#define CSR_HPMCOUNTER11 0xc0b +#define CSR_HPMCOUNTER12 0xc0c +#define CSR_HPMCOUNTER13 0xc0d +#define CSR_HPMCOUNTER14 0xc0e +#define CSR_HPMCOUNTER15 0xc0f +#define CSR_HPMCOUNTER16 0xc10 +#define CSR_HPMCOUNTER17 0xc11 +#define CSR_HPMCOUNTER18 0xc12 +#define CSR_HPMCOUNTER19 0xc13 +#define CSR_HPMCOUNTER20 0xc14 +#define CSR_HPMCOUNTER21 0xc15 +#define CSR_HPMCOUNTER22 0xc16 +#define CSR_HPMCOUNTER23 0xc17 +#define CSR_HPMCOUNTER24 0xc18 +#define CSR_HPMCOUNTER25 0xc19 +#define CSR_HPMCOUNTER26 0xc1a +#define CSR_HPMCOUNTER27 0xc1b +#define CSR_HPMCOUNTER28 0xc1c +#define CSR_HPMCOUNTER29 0xc1d +#define CSR_HPMCOUNTER30 0xc1e +#define CSR_HPMCOUNTER31 0xc1f +#define CSR_SSTATUS 0x100 +#define CSR_SIE 0x104 +#define CSR_STVEC 0x105 +#define CSR_SCOUNTEREN 0x106 +#define CSR_SSCRATCH 0x140 +#define CSR_SEPC 0x141 +#define CSR_SCAUSE 0x142 +#define CSR_SBADADDR 0x143 +#define CSR_SIP 0x144 +#define CSR_SPTBR 0x180 +#define CSR_SATP 0x180 +#define CSR_MSTATUS 0x300 +#define CSR_MISA 0x301 +#define CSR_MEDELEG 0x302 +#define CSR_MIDELEG 0x303 +#define CSR_MIE 0x304 +#define CSR_MTVEC 0x305 +#define CSR_MCOUNTEREN 0x306 +#define CSR_MSCRATCH 0x340 +#define CSR_MEPC 0x341 +#define CSR_MCAUSE 0x342 +#define CSR_MBADADDR 0x343 +#define CSR_MIP 0x344 +#define CSR_PMPCFG0 0x3a0 +#define CSR_PMPCFG1 0x3a1 +#define CSR_PMPCFG2 0x3a2 +#define CSR_PMPCFG3 0x3a3 +#define CSR_PMPADDR0 0x3b0 +#define CSR_PMPADDR1 0x3b1 +#define CSR_PMPADDR2 0x3b2 +#define CSR_PMPADDR3 0x3b3 +#define CSR_PMPADDR4 0x3b4 +#define CSR_PMPADDR5 0x3b5 +#define CSR_PMPADDR6 0x3b6 +#define CSR_PMPADDR7 0x3b7 +#define CSR_PMPADDR8 0x3b8 +#define CSR_PMPADDR9 0x3b9 +#define CSR_PMPADDR10 0x3ba +#define CSR_PMPADDR11 0x3bb +#define CSR_PMPADDR12 0x3bc +#define CSR_PMPADDR13 0x3bd +#define CSR_PMPADDR14 0x3be +#define CSR_PMPADDR15 0x3bf +#define CSR_TSELECT 0x7a0 +#define CSR_TDATA1 0x7a1 +#define CSR_TDATA2 0x7a2 +#define CSR_TDATA3 0x7a3 +#define CSR_DCSR 0x7b0 +#define CSR_DPC 0x7b1 +#define CSR_DSCRATCH 0x7b2 +#define CSR_MCYCLE 0xb00 +#define CSR_MINSTRET 0xb02 +#define CSR_MHPMCOUNTER3 0xb03 +#define CSR_MHPMCOUNTER4 0xb04 +#define CSR_MHPMCOUNTER5 0xb05 +#define CSR_MHPMCOUNTER6 0xb06 +#define CSR_MHPMCOUNTER7 0xb07 +#define CSR_MHPMCOUNTER8 0xb08 +#define CSR_MHPMCOUNTER9 0xb09 +#define CSR_MHPMCOUNTER10 0xb0a +#define CSR_MHPMCOUNTER11 0xb0b +#define CSR_MHPMCOUNTER12 0xb0c +#define CSR_MHPMCOUNTER13 0xb0d +#define CSR_MHPMCOUNTER14 0xb0e +#define CSR_MHPMCOUNTER15 0xb0f +#define CSR_MHPMCOUNTER16 0xb10 +#define CSR_MHPMCOUNTER17 0xb11 +#define CSR_MHPMCOUNTER18 0xb12 +#define CSR_MHPMCOUNTER19 0xb13 +#define CSR_MHPMCOUNTER20 0xb14 +#define CSR_MHPMCOUNTER21 0xb15 +#define CSR_MHPMCOUNTER22 0xb16 +#define CSR_MHPMCOUNTER23 0xb17 +#define CSR_MHPMCOUNTER24 0xb18 +#define CSR_MHPMCOUNTER25 0xb19 +#define CSR_MHPMCOUNTER26 0xb1a +#define CSR_MHPMCOUNTER27 0xb1b +#define CSR_MHPMCOUNTER28 0xb1c +#define CSR_MHPMCOUNTER29 0xb1d +#define CSR_MHPMCOUNTER30 0xb1e +#define CSR_MHPMCOUNTER31 0xb1f +#define CSR_MUCOUNTEREN 0x320 +#define CSR_MSCOUNTEREN 0x321 +#define CSR_MHPMEVENT3 0x323 +#define CSR_MHPMEVENT4 0x324 +#define CSR_MHPMEVENT5 0x325 +#define CSR_MHPMEVENT6 0x326 +#define CSR_MHPMEVENT7 0x327 +#define CSR_MHPMEVENT8 0x328 +#define CSR_MHPMEVENT9 0x329 +#define CSR_MHPMEVENT10 0x32a +#define CSR_MHPMEVENT11 0x32b +#define CSR_MHPMEVENT12 0x32c +#define CSR_MHPMEVENT13 0x32d +#define CSR_MHPMEVENT14 0x32e +#define CSR_MHPMEVENT15 0x32f +#define CSR_MHPMEVENT16 0x330 +#define CSR_MHPMEVENT17 0x331 +#define CSR_MHPMEVENT18 0x332 +#define CSR_MHPMEVENT19 0x333 +#define CSR_MHPMEVENT20 0x334 +#define CSR_MHPMEVENT21 0x335 +#define CSR_MHPMEVENT22 0x336 +#define CSR_MHPMEVENT23 0x337 +#define CSR_MHPMEVENT24 0x338 +#define CSR_MHPMEVENT25 0x339 +#define CSR_MHPMEVENT26 0x33a +#define CSR_MHPMEVENT27 0x33b +#define CSR_MHPMEVENT28 0x33c +#define CSR_MHPMEVENT29 0x33d +#define CSR_MHPMEVENT30 0x33e +#define CSR_MHPMEVENT31 0x33f +#define CSR_MVENDORID 0xf11 +#define CSR_MARCHID 0xf12 +#define CSR_MIMPID 0xf13 +#define CSR_MHARTID 0xf14 +#define CSR_CYCLEH 0xc80 +#define CSR_TIMEH 0xc81 +#define CSR_INSTRETH 0xc82 +#define CSR_HPMCOUNTER3H 0xc83 +#define CSR_HPMCOUNTER4H 0xc84 +#define CSR_HPMCOUNTER5H 0xc85 +#define CSR_HPMCOUNTER6H 0xc86 +#define CSR_HPMCOUNTER7H 0xc87 +#define CSR_HPMCOUNTER8H 0xc88 +#define CSR_HPMCOUNTER9H 0xc89 +#define CSR_HPMCOUNTER10H 0xc8a +#define CSR_HPMCOUNTER11H 0xc8b +#define CSR_HPMCOUNTER12H 0xc8c +#define CSR_HPMCOUNTER13H 0xc8d +#define CSR_HPMCOUNTER14H 0xc8e +#define CSR_HPMCOUNTER15H 0xc8f +#define CSR_HPMCOUNTER16H 0xc90 +#define CSR_HPMCOUNTER17H 0xc91 +#define CSR_HPMCOUNTER18H 0xc92 +#define CSR_HPMCOUNTER19H 0xc93 +#define CSR_HPMCOUNTER20H 0xc94 +#define CSR_HPMCOUNTER21H 0xc95 +#define CSR_HPMCOUNTER22H 0xc96 +#define CSR_HPMCOUNTER23H 0xc97 +#define CSR_HPMCOUNTER24H 0xc98 +#define CSR_HPMCOUNTER25H 0xc99 +#define CSR_HPMCOUNTER26H 0xc9a +#define CSR_HPMCOUNTER27H 0xc9b +#define CSR_HPMCOUNTER28H 0xc9c +#define CSR_HPMCOUNTER29H 0xc9d +#define CSR_HPMCOUNTER30H 0xc9e +#define CSR_HPMCOUNTER31H 0xc9f +#define CSR_MCYCLEH 0xb80 +#define CSR_MINSTRETH 0xb82 +#define CSR_MHPMCOUNTER3H 0xb83 +#define CSR_MHPMCOUNTER4H 0xb84 +#define CSR_MHPMCOUNTER5H 0xb85 +#define CSR_MHPMCOUNTER6H 0xb86 +#define CSR_MHPMCOUNTER7H 0xb87 +#define CSR_MHPMCOUNTER8H 0xb88 +#define CSR_MHPMCOUNTER9H 0xb89 +#define CSR_MHPMCOUNTER10H 0xb8a +#define CSR_MHPMCOUNTER11H 0xb8b +#define CSR_MHPMCOUNTER12H 0xb8c +#define CSR_MHPMCOUNTER13H 0xb8d +#define CSR_MHPMCOUNTER14H 0xb8e +#define CSR_MHPMCOUNTER15H 0xb8f +#define CSR_MHPMCOUNTER16H 0xb90 +#define CSR_MHPMCOUNTER17H 0xb91 +#define CSR_MHPMCOUNTER18H 0xb92 +#define CSR_MHPMCOUNTER19H 0xb93 +#define CSR_MHPMCOUNTER20H 0xb94 +#define CSR_MHPMCOUNTER21H 0xb95 +#define CSR_MHPMCOUNTER22H 0xb96 +#define CSR_MHPMCOUNTER23H 0xb97 +#define CSR_MHPMCOUNTER24H 0xb98 +#define CSR_MHPMCOUNTER25H 0xb99 +#define CSR_MHPMCOUNTER26H 0xb9a +#define CSR_MHPMCOUNTER27H 0xb9b +#define CSR_MHPMCOUNTER28H 0xb9c +#define CSR_MHPMCOUNTER29H 0xb9d +#define CSR_MHPMCOUNTER30H 0xb9e +#define CSR_MHPMCOUNTER31H 0xb9f + +/* mstatus bits */ +#define MSTATUS_UIE 0x00000001 +#define MSTATUS_SIE 0x00000002 +#define MSTATUS_HIE 0x00000004 +#define MSTATUS_MIE 0x00000008 +#define MSTATUS_UPIE 0x00000010 +#define MSTATUS_SPIE 0x00000020 +#define MSTATUS_HPIE 0x00000040 +#define MSTATUS_MPIE 0x00000080 +#define MSTATUS_SPP 0x00000100 +#define MSTATUS_HPP 0x00000600 +#define MSTATUS_MPP 0x00001800 +#define MSTATUS_FS 0x00006000 +#define MSTATUS_XS 0x00018000 +#define MSTATUS_MPRV 0x00020000 +#define MSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ +#define MSTATUS_SUM 0x00040000 /* since: priv-1.10 */ +#define MSTATUS_MXR 0x00080000 +#define MSTATUS_VM 0x1F000000 /* until: priv-1.9.1 */ +#define MSTATUS_TVM 0x00100000 /* since: priv-1.10 */ +#define MSTATUS_TW 0x20000000 /* since: priv-1.10 */ +#define MSTATUS_TSR 0x40000000 /* since: priv-1.10 */ + +#define MSTATUS64_UXL 0x0000000300000000ULL +#define MSTATUS64_SXL 0x0000000C00000000ULL + +#define MSTATUS32_SD 0x80000000 +#define MSTATUS64_SD 0x8000000000000000ULL + +#if defined(TARGET_RISCV32) +#define MSTATUS_SD MSTATUS32_SD +#elif defined(TARGET_RISCV64) +#define MSTATUS_SD MSTATUS64_SD +#endif + +/* sstatus bits */ +#define SSTATUS_UIE 0x00000001 +#define SSTATUS_SIE 0x00000002 +#define SSTATUS_UPIE 0x00000010 +#define SSTATUS_SPIE 0x00000020 +#define SSTATUS_SPP 0x00000100 +#define SSTATUS_FS 0x00006000 +#define SSTATUS_XS 0x00018000 +#define SSTATUS_PUM 0x00040000 /* until: priv-1.9.1 */ +#define SSTATUS_SUM 0x00040000 /* since: priv-1.10 */ +#define SSTATUS_MXR 0x00080000 + +#define SSTATUS32_SD 0x80000000 +#define SSTATUS64_SD 0x8000000000000000ULL + +#if defined(TARGET_RISCV32) +#define SSTATUS_SD SSTATUS32_SD +#elif defined(TARGET_RISCV64) +#define SSTATUS_SD SSTATUS64_SD +#endif + +/* irqs */ +#define MIP_SSIP (1 << IRQ_S_SOFT) +#define MIP_HSIP (1 << IRQ_H_SOFT) +#define MIP_MSIP (1 << IRQ_M_SOFT) +#define MIP_STIP (1 << IRQ_S_TIMER) +#define MIP_HTIP (1 << IRQ_H_TIMER) +#define MIP_MTIP (1 << IRQ_M_TIMER) +#define MIP_SEIP (1 << IRQ_S_EXT) +#define MIP_HEIP (1 << IRQ_H_EXT) +#define MIP_MEIP (1 << IRQ_M_EXT) + +#define SIP_SSIP MIP_SSIP +#define SIP_STIP MIP_STIP +#define SIP_SEIP MIP_SEIP + +#define PRV_U 0 +#define PRV_S 1 +#define PRV_H 2 +#define PRV_M 3 + +/* privileged ISA 1.9.1 VM modes (mstatus.vm) */ +#define VM_1_09_MBARE 0 +#define VM_1_09_MBB 1 +#define VM_1_09_MBBID 2 +#define VM_1_09_SV32 8 +#define VM_1_09_SV39 9 +#define VM_1_09_SV48 10 + +/* privileged ISA 1.10.0 VM modes (satp.mode) */ +#define VM_1_10_MBARE 0 +#define VM_1_10_SV32 1 +#define VM_1_10_SV39 8 +#define VM_1_10_SV48 9 +#define VM_1_10_SV57 10 +#define VM_1_10_SV64 11 + +/* privileged ISA interrupt causes */ +#define IRQ_U_SOFT 0 /* since: priv-1.10 */ +#define IRQ_S_SOFT 1 +#define IRQ_H_SOFT 2 /* until: priv-1.9.1 */ +#define IRQ_M_SOFT 3 /* until: priv-1.9.1 */ +#define IRQ_U_TIMER 4 /* since: priv-1.10 */ +#define IRQ_S_TIMER 5 +#define IRQ_H_TIMER 6 /* until: priv-1.9.1 */ +#define IRQ_M_TIMER 7 /* until: priv-1.9.1 */ +#define IRQ_U_EXT 8 /* since: priv-1.10 */ +#define IRQ_S_EXT 9 +#define IRQ_H_EXT 10 /* until: priv-1.9.1 */ +#define IRQ_M_EXT 11 /* until: priv-1.9.1 */ +#define IRQ_X_COP 12 /* non-standard */ + +/* Default addresses */ +#define DEFAULT_RSTVEC 0x00001000 + +/* RV32 satp field masks */ +#define SATP32_MODE 0x80000000 +#define SATP32_ASID 0x7fc00000 +#define SATP32_PPN 0x003fffff + +/* RV64 satp field masks */ +#define SATP64_MODE 0xF000000000000000ULL +#define SATP64_ASID 0x0FFFF00000000000ULL +#define SATP64_PPN 0x00000FFFFFFFFFFFULL + +#if defined(TARGET_RISCV32) +#define SATP_MODE SATP32_MODE +#define SATP_ASID SATP32_ASID +#define SATP_PPN SATP32_PPN +#endif +#if defined(TARGET_RISCV64) +#define SATP_MODE SATP64_MODE +#define SATP_ASID SATP64_ASID +#define SATP_PPN SATP64_PPN +#endif + +/* RISCV Exception Codes */ +#define EXCP_NONE -1 /* not a real RISCV exception code */ +#define RISCV_EXCP_INST_ADDR_MIS 0x0 +#define RISCV_EXCP_INST_ACCESS_FAULT 0x1 +#define RISCV_EXCP_ILLEGAL_INST 0x2 +#define RISCV_EXCP_BREAKPOINT 0x3 +#define RISCV_EXCP_LOAD_ADDR_MIS 0x4 +#define RISCV_EXCP_LOAD_ACCESS_FAULT 0x5 +#define RISCV_EXCP_STORE_AMO_ADDR_MIS 0x6 +#define RISCV_EXCP_STORE_AMO_ACCESS_FAULT 0x7 +#define RISCV_EXCP_U_ECALL 0x8 /* for convenience, report all + ECALLs as this, handler + fixes */ +#define RISCV_EXCP_S_ECALL 0x9 +#define RISCV_EXCP_H_ECALL 0xa +#define RISCV_EXCP_M_ECALL 0xb +#define RISCV_EXCP_INST_PAGE_FAULT 0xc /* since: priv-1.10.0 */ +#define RISCV_EXCP_LOAD_PAGE_FAULT 0xd /* since: priv-1.10.0 */ +#define RISCV_EXCP_STORE_PAGE_FAULT 0xf /* since: priv-1.10.0 */ + +#define RISCV_EXCP_INT_FLAG 0x80000000 +#define RISCV_EXCP_INT_MASK 0x7fffffff + +/* page table entry (PTE) fields */ +#define PTE_V 0x001 /* Valid */ +#define PTE_R 0x002 /* Read */ +#define PTE_W 0x004 /* Write */ +#define PTE_X 0x008 /* Execute */ +#define PTE_U 0x010 /* User */ +#define PTE_G 0x020 /* Global */ +#define PTE_A 0x040 /* Accessed */ +#define PTE_D 0x080 /* Dirty */ +#define PTE_SOFT 0x300 /* Reserved for Software */ + +#define PTE_PPN_SHIFT 10 diff --git a/qemu/target/riscv/cpu_user.h b/qemu/target/riscv/cpu_user.h new file mode 100644 index 00000000..c2199610 --- /dev/null +++ b/qemu/target/riscv/cpu_user.h @@ -0,0 +1,13 @@ +#define xRA 1 /* return address (aka link register) */ +#define xSP 2 /* stack pointer */ +#define xGP 3 /* global pointer */ +#define xTP 4 /* thread pointer */ + +#define xA0 10 /* gpr[10-17] are syscall arguments */ +#define xA1 11 +#define xA2 12 +#define xA3 13 +#define xA4 14 +#define xA5 15 +#define xA6 16 +#define xA7 17 /* syscall number goes here */ diff --git a/qemu/target/riscv/fpu_helper.c b/qemu/target/riscv/fpu_helper.c new file mode 100644 index 00000000..fdb87d8d --- /dev/null +++ b/qemu/target/riscv/fpu_helper.c @@ -0,0 +1,371 @@ +/* + * RISC-V FPU Emulation Helpers for QEMU. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include +#include "cpu.h" +#include "qemu/host-utils.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" + +target_ulong cpu_riscv_get_fflags(CPURISCVState *env) +{ + int soft = get_float_exception_flags(&env->fp_status); + target_ulong hard = 0; + + hard |= (soft & float_flag_inexact) ? FPEXC_NX : 0; + hard |= (soft & float_flag_underflow) ? FPEXC_UF : 0; + hard |= (soft & float_flag_overflow) ? FPEXC_OF : 0; + hard |= (soft & float_flag_divbyzero) ? FPEXC_DZ : 0; + hard |= (soft & float_flag_invalid) ? FPEXC_NV : 0; + + return hard; +} + +void cpu_riscv_set_fflags(CPURISCVState *env, target_ulong hard) +{ + int soft = 0; + + soft |= (hard & FPEXC_NX) ? float_flag_inexact : 0; + soft |= (hard & FPEXC_UF) ? float_flag_underflow : 0; + soft |= (hard & FPEXC_OF) ? float_flag_overflow : 0; + soft |= (hard & FPEXC_DZ) ? float_flag_divbyzero : 0; + soft |= (hard & FPEXC_NV) ? float_flag_invalid : 0; + + set_float_exception_flags(soft, &env->fp_status); +} + +void helper_set_rounding_mode(CPURISCVState *env, uint32_t rm) +{ + int softrm; + + if (rm == 7) { + rm = env->frm; + } + switch (rm) { + case 0: + softrm = float_round_nearest_even; + break; + case 1: + softrm = float_round_to_zero; + break; + case 2: + softrm = float_round_down; + break; + case 3: + softrm = float_round_up; + break; + case 4: + softrm = float_round_ties_away; + break; + default: + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + set_float_rounding_mode(softrm, &env->fp_status); +} + +uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return float32_muladd(frs1, frs2, frs3, 0, &env->fp_status); +} + +uint64_t helper_fmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return float64_muladd(frs1, frs2, frs3, 0, &env->fp_status); +} + +uint64_t helper_fmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c, + &env->fp_status); +} + +uint64_t helper_fmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c, + &env->fp_status); +} + +uint64_t helper_fnmsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return float32_muladd(frs1, frs2, frs3, float_muladd_negate_product, + &env->fp_status); +} + +uint64_t helper_fnmsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return float64_muladd(frs1, frs2, frs3, float_muladd_negate_product, + &env->fp_status); +} + +uint64_t helper_fnmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return float32_muladd(frs1, frs2, frs3, float_muladd_negate_c | + float_muladd_negate_product, &env->fp_status); +} + +uint64_t helper_fnmadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2, + uint64_t frs3) +{ + return float64_muladd(frs1, frs2, frs3, float_muladd_negate_c | + float_muladd_negate_product, &env->fp_status); +} + +uint64_t helper_fadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_add(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fsub_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_sub(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fmul_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_mul(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_div(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fmin_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_minnum(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fmax_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_maxnum(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t frs1) +{ + return float32_sqrt(frs1, &env->fp_status); +} + +target_ulong helper_fle_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_le(frs1, frs2, &env->fp_status); +} + +target_ulong helper_flt_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_lt(frs1, frs2, &env->fp_status); +} + +target_ulong helper_feq_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float32_eq_quiet(frs1, frs2, &env->fp_status); +} + +target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t frs1) +{ + return float32_to_int32(frs1, &env->fp_status); +} + +target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t frs1) +{ + return (int32_t)float32_to_uint32(frs1, &env->fp_status); +} + +#if defined(TARGET_RISCV64) +uint64_t helper_fcvt_l_s(CPURISCVState *env, uint64_t frs1) +{ + return float32_to_int64(frs1, &env->fp_status); +} + +uint64_t helper_fcvt_lu_s(CPURISCVState *env, uint64_t frs1) +{ + return float32_to_uint64(frs1, &env->fp_status); +} +#endif + +uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1) +{ + return int32_to_float32((int32_t)rs1, &env->fp_status); +} + +uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1) +{ + return uint32_to_float32((uint32_t)rs1, &env->fp_status); +} + +#if defined(TARGET_RISCV64) +uint64_t helper_fcvt_s_l(CPURISCVState *env, uint64_t rs1) +{ + return int64_to_float32(rs1, &env->fp_status); +} + +uint64_t helper_fcvt_s_lu(CPURISCVState *env, uint64_t rs1) +{ + return uint64_to_float32(rs1, &env->fp_status); +} +#endif + +target_ulong helper_fclass_s(uint64_t frs1) +{ + float32 f = frs1; + bool sign = float32_is_neg(f); + + if (float32_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (float32_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (float32_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (float32_is_any_nan(f)) { + float_status s = { }; /* for snan_bit_is_one */ + return float32_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} + +uint64_t helper_fadd_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_add(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fsub_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_sub(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fmul_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_mul(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fdiv_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_div(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fmin_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_minnum(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fmax_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_maxnum(frs1, frs2, &env->fp_status); +} + +uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) +{ + return float64_to_float32(rs1, &env->fp_status); +} + +uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) +{ + return float32_to_float64(rs1, &env->fp_status); +} + +uint64_t helper_fsqrt_d(CPURISCVState *env, uint64_t frs1) +{ + return float64_sqrt(frs1, &env->fp_status); +} + +target_ulong helper_fle_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_le(frs1, frs2, &env->fp_status); +} + +target_ulong helper_flt_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_lt(frs1, frs2, &env->fp_status); +} + +target_ulong helper_feq_d(CPURISCVState *env, uint64_t frs1, uint64_t frs2) +{ + return float64_eq_quiet(frs1, frs2, &env->fp_status); +} + +target_ulong helper_fcvt_w_d(CPURISCVState *env, uint64_t frs1) +{ + return float64_to_int32(frs1, &env->fp_status); +} + +target_ulong helper_fcvt_wu_d(CPURISCVState *env, uint64_t frs1) +{ + return (int32_t)float64_to_uint32(frs1, &env->fp_status); +} + +#if defined(TARGET_RISCV64) +uint64_t helper_fcvt_l_d(CPURISCVState *env, uint64_t frs1) +{ + return float64_to_int64(frs1, &env->fp_status); +} + +uint64_t helper_fcvt_lu_d(CPURISCVState *env, uint64_t frs1) +{ + return float64_to_uint64(frs1, &env->fp_status); +} +#endif + +uint64_t helper_fcvt_d_w(CPURISCVState *env, target_ulong rs1) +{ + return int32_to_float64((int32_t)rs1, &env->fp_status); +} + +uint64_t helper_fcvt_d_wu(CPURISCVState *env, target_ulong rs1) +{ + return uint32_to_float64((uint32_t)rs1, &env->fp_status); +} + +#if defined(TARGET_RISCV64) +uint64_t helper_fcvt_d_l(CPURISCVState *env, uint64_t rs1) +{ + return int64_to_float64(rs1, &env->fp_status); +} + +uint64_t helper_fcvt_d_lu(CPURISCVState *env, uint64_t rs1) +{ + return uint64_to_float64(rs1, &env->fp_status); +} +#endif + +target_ulong helper_fclass_d(uint64_t frs1) +{ + float64 f = frs1; + bool sign = float64_is_neg(f); + + if (float64_is_infinity(f)) { + return sign ? 1 << 0 : 1 << 7; + } else if (float64_is_zero(f)) { + return sign ? 1 << 3 : 1 << 4; + } else if (float64_is_zero_or_denormal(f)) { + return sign ? 1 << 2 : 1 << 5; + } else if (float64_is_any_nan(f)) { + float_status s = { }; /* for snan_bit_is_one */ + return float64_is_quiet_nan(f, &s) ? 1 << 9 : 1 << 8; + } else { + return sign ? 1 << 1 : 1 << 6; + } +} diff --git a/qemu/target/riscv/helper.c b/qemu/target/riscv/helper.c new file mode 100644 index 00000000..31d68ac1 --- /dev/null +++ b/qemu/target/riscv/helper.c @@ -0,0 +1,526 @@ +/* + * RISC-V emulation helpers for qemu. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "tcg-op.h" + +#define RISCV_DEBUG_INTERRUPT 0 + +int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch) +{ +#ifdef CONFIG_USER_ONLY + return 0; +#else + return env->priv; +#endif +} + +#ifndef CONFIG_USER_ONLY +static int riscv_cpu_local_irq_pending(CPURISCVState *env) +{ + target_ulong mstatus_mie = get_field(env->mstatus, MSTATUS_MIE); + target_ulong mstatus_sie = get_field(env->mstatus, MSTATUS_SIE); + target_ulong pending = atomic_read(&env->mip) & env->mie; + target_ulong mie = env->priv < PRV_M || (env->priv == PRV_M && mstatus_mie); + target_ulong sie = env->priv < PRV_S || (env->priv == PRV_S && mstatus_sie); + target_ulong irqs = (pending & ~env->mideleg & -mie) | + (pending & env->mideleg & -sie); + + if (irqs) { + return ctz64(irqs); /* since non-zero */ + } else { + return EXCP_NONE; /* indicates no pending interrupt */ + } +} +#endif + +bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ +#if !defined(CONFIG_USER_ONLY) + if (interrupt_request & CPU_INTERRUPT_HARD) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + int interruptno = riscv_cpu_local_irq_pending(env); + if (interruptno >= 0) { + cs->exception_index = RISCV_EXCP_INT_FLAG | interruptno; + riscv_cpu_do_interrupt(cs); + return true; + } + } +#endif + return false; +} + +#if !defined(CONFIG_USER_ONLY) + +/* get_physical_address - get the physical address for this virtual address + * + * Do a page table walk to obtain the physical address corresponding to a + * virtual address. Returns 0 if the translation was successful + * + * Adapted from Spike's mmu_t::translate and mmu_t::walk + * + */ +static int get_physical_address(CPURISCVState *env, hwaddr *physical, + int *prot, target_ulong addr, + int access_type, int mmu_idx) +{ + /* NOTE: the env->pc value visible here will not be + * correct, but the value visible to the exception handler + * (riscv_cpu_do_interrupt) is correct */ + + int mode = mmu_idx; + + if (mode == PRV_M && access_type != MMU_INST_FETCH) { + if (get_field(env->mstatus, MSTATUS_MPRV)) { + mode = get_field(env->mstatus, MSTATUS_MPP); + } + } + + if (mode == PRV_M || !riscv_feature(env, RISCV_FEATURE_MMU)) { + *physical = addr; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + } + + *prot = 0; + + target_ulong base; + int levels, ptidxbits, ptesize, vm, sum; + int mxr = get_field(env->mstatus, MSTATUS_MXR); + + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + base = get_field(env->satp, SATP_PPN) << PGSHIFT; + sum = get_field(env->mstatus, MSTATUS_SUM); + vm = get_field(env->satp, SATP_MODE); + switch (vm) { + case VM_1_10_SV32: + levels = 2; ptidxbits = 10; ptesize = 4; break; + case VM_1_10_SV39: + levels = 3; ptidxbits = 9; ptesize = 8; break; + case VM_1_10_SV48: + levels = 4; ptidxbits = 9; ptesize = 8; break; + case VM_1_10_SV57: + levels = 5; ptidxbits = 9; ptesize = 8; break; + case VM_1_10_MBARE: + *physical = addr; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + default: + g_assert_not_reached(); + } + } else { + base = env->sptbr << PGSHIFT; + sum = !get_field(env->mstatus, MSTATUS_PUM); + vm = get_field(env->mstatus, MSTATUS_VM); + switch (vm) { + case VM_1_09_SV32: + levels = 2; ptidxbits = 10; ptesize = 4; break; + case VM_1_09_SV39: + levels = 3; ptidxbits = 9; ptesize = 8; break; + case VM_1_09_SV48: + levels = 4; ptidxbits = 9; ptesize = 8; break; + case VM_1_09_MBARE: + *physical = addr; + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TRANSLATE_SUCCESS; + default: + g_assert_not_reached(); + } + } + + CPUState *cs = CPU(riscv_env_get_cpu(env)); + int va_bits = PGSHIFT + levels * ptidxbits; + target_ulong mask = (1L << (TARGET_LONG_BITS - (va_bits - 1))) - 1; + target_ulong masked_msbs = (addr >> (va_bits - 1)) & mask; + if (masked_msbs != 0 && masked_msbs != mask) { + return TRANSLATE_FAIL; + } + + int ptshift = (levels - 1) * ptidxbits; + int i; + +#if !TCG_OVERSIZED_GUEST +restart: +#endif + for (i = 0; i < levels; i++, ptshift -= ptidxbits) { + target_ulong idx = (addr >> (PGSHIFT + ptshift)) & + ((1 << ptidxbits) - 1); + + /* check that physical address of PTE is legal */ + target_ulong pte_addr = base + idx * ptesize; +#if defined(TARGET_RISCV32) + target_ulong pte = ldl_phys(cs->as, pte_addr); +#elif defined(TARGET_RISCV64) + target_ulong pte = ldq_phys(cs->as, pte_addr); +#endif + target_ulong ppn = pte >> PTE_PPN_SHIFT; + + if (!(pte & PTE_V)) { + /* Invalid PTE */ + return TRANSLATE_FAIL; + } else if (!(pte & (PTE_R | PTE_W | PTE_X))) { + /* Inner PTE, continue walking */ + base = ppn << PGSHIFT; + } else if ((pte & (PTE_R | PTE_W | PTE_X)) == PTE_W) { + /* Reserved leaf PTE flags: PTE_W */ + return TRANSLATE_FAIL; + } else if ((pte & (PTE_R | PTE_W | PTE_X)) == (PTE_W | PTE_X)) { + /* Reserved leaf PTE flags: PTE_W + PTE_X */ + return TRANSLATE_FAIL; + } else if ((pte & PTE_U) && ((mode != PRV_U) && + (!sum || access_type == MMU_INST_FETCH))) { + /* User PTE flags when not U mode and mstatus.SUM is not set, + or the access type is an instruction fetch */ + return TRANSLATE_FAIL; + } else if (!(pte & PTE_U) && (mode != PRV_S)) { + /* Supervisor PTE flags when not S mode */ + return TRANSLATE_FAIL; + } else if (ppn & ((1ULL << ptshift) - 1)) { + /* Misaligned PPN */ + return TRANSLATE_FAIL; + } else if (access_type == MMU_DATA_LOAD && !((pte & PTE_R) || + ((pte & PTE_X) && mxr))) { + /* Read access check failed */ + return TRANSLATE_FAIL; + } else if (access_type == MMU_DATA_STORE && !(pte & PTE_W)) { + /* Write access check failed */ + return TRANSLATE_FAIL; + } else if (access_type == MMU_INST_FETCH && !(pte & PTE_X)) { + /* Fetch access check failed */ + return TRANSLATE_FAIL; + } else { + /* if necessary, set accessed and dirty bits. */ + target_ulong updated_pte = pte | PTE_A | + (access_type == MMU_DATA_STORE ? PTE_D : 0); + + /* Page table updates need to be atomic with MTTCG enabled */ + if (updated_pte != pte) { + /* + * - if accessed or dirty bits need updating, and the PTE is + * in RAM, then we do so atomically with a compare and swap. + * - if the PTE is in IO space or ROM, then it can't be updated + * and we return TRANSLATE_FAIL. + * - if the PTE changed by the time we went to update it, then + * it is no longer valid and we must re-walk the page table. + */ + MemoryRegion *mr; + hwaddr l = sizeof(target_ulong), addr1; + mr = address_space_translate(cs->as, pte_addr, &addr1, &l, false); + if (memory_region_is_ram(mr)) { + target_ulong *pte_pa = + qemu_map_ram_ptr(env->uc, mr->ram_block, addr1); +#if TCG_OVERSIZED_GUEST + /* MTTCG is not enabled on oversized TCG guests so + * page table updates do not need to be atomic */ + *pte_pa = pte = updated_pte; +#else + target_ulong old_pte = + atomic_cmpxchg(pte_pa, pte, updated_pte); + if (old_pte != pte) { + goto restart; + } else { + pte = updated_pte; + } +#endif + } else { + /* misconfigured PTE in ROM (AD bits are not preset) or + * PTE is in IO space and can't be updated atomically */ + return TRANSLATE_FAIL; + } + } + + /* for superpage mappings, make a fake leaf PTE for the TLB's + benefit. */ + target_ulong vpn = addr >> PGSHIFT; + *physical = (ppn | (vpn & ((1L << ptshift) - 1))) << PGSHIFT; + + /* set permissions on the TLB entry */ + if ((pte & PTE_R) || ((pte & PTE_X) && mxr)) { + *prot |= PAGE_READ; + } + if ((pte & PTE_X)) { + *prot |= PAGE_EXEC; + } + /* add write permission on stores or if the page is already dirty, + so that we TLB miss on later writes to update the dirty bit */ + if ((pte & PTE_W) && + (access_type == MMU_DATA_STORE || (pte & PTE_D))) { + *prot |= PAGE_WRITE; + } + return TRANSLATE_SUCCESS; + } + } + return TRANSLATE_FAIL; +} + +static void raise_mmu_exception(CPURISCVState *env, target_ulong address, + MMUAccessType access_type) +{ + CPUState *cs = CPU(riscv_env_get_cpu(env)); + int page_fault_exceptions = + (env->priv_ver >= PRIV_VERSION_1_10_0) && + get_field(env->satp, SATP_MODE) != VM_1_10_MBARE; + switch (access_type) { + case MMU_INST_FETCH: + cs->exception_index = page_fault_exceptions ? + RISCV_EXCP_INST_PAGE_FAULT : RISCV_EXCP_INST_ACCESS_FAULT; + break; + case MMU_DATA_LOAD: + cs->exception_index = page_fault_exceptions ? + RISCV_EXCP_LOAD_PAGE_FAULT : RISCV_EXCP_LOAD_ACCESS_FAULT; + break; + case MMU_DATA_STORE: + cs->exception_index = page_fault_exceptions ? + RISCV_EXCP_STORE_PAGE_FAULT : RISCV_EXCP_STORE_AMO_ACCESS_FAULT; + break; + default: + g_assert_not_reached(); + } + env->badaddr = address; +} + +hwaddr riscv_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + hwaddr phys_addr; + int prot; + int mmu_idx = cpu_mmu_index(&cpu->env, false); + + if (get_physical_address(&cpu->env, &phys_addr, &prot, addr, 0, mmu_idx)) { + return -1; + } + return phys_addr; +} + +void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + switch (access_type) { + case MMU_INST_FETCH: + cs->exception_index = RISCV_EXCP_INST_ADDR_MIS; + break; + case MMU_DATA_LOAD: + cs->exception_index = RISCV_EXCP_LOAD_ADDR_MIS; + break; + case MMU_DATA_STORE: + cs->exception_index = RISCV_EXCP_STORE_AMO_ADDR_MIS; + break; + default: + g_assert_not_reached(); + } + env->badaddr = addr; + do_raise_exception_err(env, cs->exception_index, retaddr); +} + +/* called by qemu's softmmu to fill the qemu tlb */ +void tlb_fill(CPUState *cs, target_ulong addr, int size, + MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) +{ + int ret; + ret = riscv_cpu_handle_mmu_fault(cs, addr, size, access_type, mmu_idx); + if (ret == TRANSLATE_FAIL) { + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + do_raise_exception_err(env, cs->exception_index, retaddr); + } +} + +#endif + +int riscv_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int size, + int rw, int mmu_idx) +{ + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; +#if !defined(CONFIG_USER_ONLY) + hwaddr pa = 0; + int prot; +#endif + int ret = TRANSLATE_FAIL; + + qemu_log_mask(CPU_LOG_MMU, + "%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx \ + %d\n", __func__, env->pc, address, rw, mmu_idx); + +#if !defined(CONFIG_USER_ONLY) + ret = get_physical_address(env, &pa, &prot, address, rw, mmu_idx); + qemu_log_mask(CPU_LOG_MMU, + "%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx + " prot %d\n", __func__, address, ret, pa, prot); + if (!pmp_hart_has_privs(env, pa, TARGET_PAGE_SIZE, 1 << rw)) { + ret = TRANSLATE_FAIL; + } + if (ret == TRANSLATE_SUCCESS) { + tlb_set_page(cs, address & TARGET_PAGE_MASK, pa & TARGET_PAGE_MASK, + prot, mmu_idx, TARGET_PAGE_SIZE); + } else if (ret == TRANSLATE_FAIL) { + raise_mmu_exception(env, address, rw); + } +#else + switch (rw) { + case MMU_INST_FETCH: + cs->exception_index = RISCV_EXCP_INST_PAGE_FAULT; + break; + case MMU_DATA_LOAD: + cs->exception_index = RISCV_EXCP_LOAD_PAGE_FAULT; + break; + case MMU_DATA_STORE: + cs->exception_index = RISCV_EXCP_STORE_PAGE_FAULT; + break; + } +#endif + return ret; +} + +/* + * Handle Traps + * + * Adapted from Spike's processor_t::take_trap. + * + */ +void riscv_cpu_do_interrupt(CPUState *cs) +{ +#if !defined(CONFIG_USER_ONLY) + + RISCVCPU *cpu = RISCV_CPU(cs); + CPURISCVState *env = &cpu->env; + + if (RISCV_DEBUG_INTERRUPT) { + int log_cause = cs->exception_index & RISCV_EXCP_INT_MASK; + if (cs->exception_index & RISCV_EXCP_INT_FLAG) { + qemu_log_mask(LOG_TRACE, "core 0: trap %s, epc 0x" TARGET_FMT_lx, + riscv_intr_names[log_cause], env->pc); + } else { + qemu_log_mask(LOG_TRACE, "core 0: intr %s, epc 0x" TARGET_FMT_lx, + riscv_excp_names[log_cause], env->pc); + } + } + + target_ulong fixed_cause = 0; + if (cs->exception_index & (RISCV_EXCP_INT_FLAG)) { + /* hacky for now. the MSB (bit 63) indicates interrupt but cs->exception + index is only 32 bits wide */ + fixed_cause = cs->exception_index & RISCV_EXCP_INT_MASK; + fixed_cause |= ((target_ulong)1) << (TARGET_LONG_BITS - 1); + } else { + /* fixup User ECALL -> correct priv ECALL */ + if (cs->exception_index == RISCV_EXCP_U_ECALL) { + switch (env->priv) { + case PRV_U: + fixed_cause = RISCV_EXCP_U_ECALL; + break; + case PRV_S: + fixed_cause = RISCV_EXCP_S_ECALL; + break; + case PRV_H: + fixed_cause = RISCV_EXCP_H_ECALL; + break; + case PRV_M: + fixed_cause = RISCV_EXCP_M_ECALL; + break; + } + } else { + fixed_cause = cs->exception_index; + } + } + + target_ulong backup_epc = env->pc; + + target_ulong bit = fixed_cause; + target_ulong deleg = env->medeleg; + + int hasbadaddr = + (fixed_cause == RISCV_EXCP_INST_ADDR_MIS) || + (fixed_cause == RISCV_EXCP_INST_ACCESS_FAULT) || + (fixed_cause == RISCV_EXCP_LOAD_ADDR_MIS) || + (fixed_cause == RISCV_EXCP_STORE_AMO_ADDR_MIS) || + (fixed_cause == RISCV_EXCP_LOAD_ACCESS_FAULT) || + (fixed_cause == RISCV_EXCP_STORE_AMO_ACCESS_FAULT) || + (fixed_cause == RISCV_EXCP_INST_PAGE_FAULT) || + (fixed_cause == RISCV_EXCP_LOAD_PAGE_FAULT) || + (fixed_cause == RISCV_EXCP_STORE_PAGE_FAULT); + + if (bit & ((target_ulong)1 << (TARGET_LONG_BITS - 1))) { + deleg = env->mideleg; + bit &= ~((target_ulong)1 << (TARGET_LONG_BITS - 1)); + } + + if (env->priv <= PRV_S && bit < 64 && ((deleg >> bit) & 1)) { + /* handle the trap in S-mode */ + /* No need to check STVEC for misaligned - lower 2 bits cannot be set */ + env->pc = env->stvec; + env->scause = fixed_cause; + env->sepc = backup_epc; + + if (hasbadaddr) { + if (RISCV_DEBUG_INTERRUPT) { + qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld + ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); + } + env->sbadaddr = env->badaddr; + } else { + /* otherwise we must clear sbadaddr/stval + * todo: support populating stval on illegal instructions */ + env->sbadaddr = 0; + } + + target_ulong s = env->mstatus; + s = set_field(s, MSTATUS_SPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? + get_field(s, MSTATUS_SIE) : get_field(s, MSTATUS_UIE << env->priv)); + s = set_field(s, MSTATUS_SPP, env->priv); + s = set_field(s, MSTATUS_SIE, 0); + csr_write_helper(env, s, CSR_MSTATUS); + riscv_set_mode(env, PRV_S); + } else { + /* No need to check MTVEC for misaligned - lower 2 bits cannot be set */ + env->pc = env->mtvec; + env->mepc = backup_epc; + env->mcause = fixed_cause; + + if (hasbadaddr) { + if (RISCV_DEBUG_INTERRUPT) { + qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld + ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); + } + env->mbadaddr = env->badaddr; + } else { + /* otherwise we must clear mbadaddr/mtval + * todo: support populating mtval on illegal instructions */ + env->mbadaddr = 0; + } + + target_ulong s = env->mstatus; + s = set_field(s, MSTATUS_MPIE, env->priv_ver >= PRIV_VERSION_1_10_0 ? + get_field(s, MSTATUS_MIE) : get_field(s, MSTATUS_UIE << env->priv)); + s = set_field(s, MSTATUS_MPP, env->priv); + s = set_field(s, MSTATUS_MIE, 0); + csr_write_helper(env, s, CSR_MSTATUS); + riscv_set_mode(env, PRV_M); + } + /* TODO yield load reservation */ +#endif + cs->exception_index = EXCP_NONE; /* mark handled to qemu */ +} diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h new file mode 100644 index 00000000..76bdb044 --- /dev/null +++ b/qemu/target/riscv/helper.h @@ -0,0 +1,82 @@ +// Unicorn +DEF_HELPER_4(uc_tracecode, void, i32, i32, ptr, i64) + +/* Exceptions */ +DEF_HELPER_2(raise_exception, noreturn, env, i32) + +/* Floating Point - rounding mode */ +DEF_HELPER_FLAGS_2(set_rounding_mode, TCG_CALL_NO_WG, void, env, i32) + +/* Floating Point - fused */ +DEF_HELPER_FLAGS_4(fmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fnmsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fnmsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fnmadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) +DEF_HELPER_FLAGS_4(fnmadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64, i64) + +/* Floating Point - Single Precision */ +DEF_HELPER_FLAGS_3(fadd_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fsub_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmul_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fdiv_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmin_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmax_s, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_2(fsqrt_s, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_3(fle_s, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(flt_s, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(feq_s, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_2(fcvt_w_s, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_wu_s, TCG_CALL_NO_RWG, tl, env, i64) +#if defined(TARGET_RISCV64) +DEF_HELPER_FLAGS_2(fcvt_l_s, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_lu_s, TCG_CALL_NO_RWG, tl, env, i64) +#endif +DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl) +#if defined(TARGET_RISCV64) +DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl) +#endif +DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64) + +/* Floating Point - Double Precision */ +DEF_HELPER_FLAGS_3(fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fsub_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmul_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fdiv_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmin_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_3(fmax_d, TCG_CALL_NO_RWG, i64, env, i64, i64) +DEF_HELPER_FLAGS_2(fcvt_s_d, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fcvt_d_s, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_2(fsqrt_d, TCG_CALL_NO_RWG, i64, env, i64) +DEF_HELPER_FLAGS_3(fle_d, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(flt_d, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_3(feq_d, TCG_CALL_NO_RWG, tl, env, i64, i64) +DEF_HELPER_FLAGS_2(fcvt_w_d, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_wu_d, TCG_CALL_NO_RWG, tl, env, i64) +#if defined(TARGET_RISCV64) +DEF_HELPER_FLAGS_2(fcvt_l_d, TCG_CALL_NO_RWG, tl, env, i64) +DEF_HELPER_FLAGS_2(fcvt_lu_d, TCG_CALL_NO_RWG, tl, env, i64) +#endif +DEF_HELPER_FLAGS_2(fcvt_d_w, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_d_wu, TCG_CALL_NO_RWG, i64, env, tl) +#if defined(TARGET_RISCV64) +DEF_HELPER_FLAGS_2(fcvt_d_l, TCG_CALL_NO_RWG, i64, env, tl) +DEF_HELPER_FLAGS_2(fcvt_d_lu, TCG_CALL_NO_RWG, i64, env, tl) +#endif +DEF_HELPER_FLAGS_1(fclass_d, TCG_CALL_NO_RWG_SE, tl, i64) + +/* Special functions */ +DEF_HELPER_3(csrrw, tl, env, tl, tl) +DEF_HELPER_4(csrrs, tl, env, tl, tl, tl) +DEF_HELPER_4(csrrc, tl, env, tl, tl, tl) +#ifndef CONFIG_USER_ONLY +DEF_HELPER_2(sret, tl, env, tl) +DEF_HELPER_2(mret, tl, env, tl) +DEF_HELPER_1(wfi, void, env) +// Unicorn: Renamed from tlb_flush to avoid clashing with the preprocessor redefinitions Unicorn uses. +DEF_HELPER_1(riscv_tlb_flush, void, env) +#endif diff --git a/qemu/target/riscv/instmap.h b/qemu/target/riscv/instmap.h new file mode 100644 index 00000000..58baa1ba --- /dev/null +++ b/qemu/target/riscv/instmap.h @@ -0,0 +1,364 @@ +/* + * RISC-V emulation for qemu: Instruction decode helpers + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#define MASK_OP_MAJOR(op) (op & 0x7F) +enum { + /* rv32i, rv64i, rv32m */ + OPC_RISC_LUI = (0x37), + OPC_RISC_AUIPC = (0x17), + OPC_RISC_JAL = (0x6F), + OPC_RISC_JALR = (0x67), + OPC_RISC_BRANCH = (0x63), + OPC_RISC_LOAD = (0x03), + OPC_RISC_STORE = (0x23), + OPC_RISC_ARITH_IMM = (0x13), + OPC_RISC_ARITH = (0x33), + OPC_RISC_FENCE = (0x0F), + OPC_RISC_SYSTEM = (0x73), + + /* rv64i, rv64m */ + OPC_RISC_ARITH_IMM_W = (0x1B), + OPC_RISC_ARITH_W = (0x3B), + + /* rv32a, rv64a */ + OPC_RISC_ATOMIC = (0x2F), + + /* floating point */ + OPC_RISC_FP_LOAD = (0x7), + OPC_RISC_FP_STORE = (0x27), + + OPC_RISC_FMADD = (0x43), + OPC_RISC_FMSUB = (0x47), + OPC_RISC_FNMSUB = (0x4B), + OPC_RISC_FNMADD = (0x4F), + + OPC_RISC_FP_ARITH = (0x53), +}; + +#define MASK_OP_ARITH(op) (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | \ + (0x7F << 25)))) +enum { + OPC_RISC_ADD = OPC_RISC_ARITH | (0x0 << 12) | (0x00 << 25), + OPC_RISC_SUB = OPC_RISC_ARITH | (0x0 << 12) | (0x20 << 25), + OPC_RISC_SLL = OPC_RISC_ARITH | (0x1 << 12) | (0x00 << 25), + OPC_RISC_SLT = OPC_RISC_ARITH | (0x2 << 12) | (0x00 << 25), + OPC_RISC_SLTU = OPC_RISC_ARITH | (0x3 << 12) | (0x00 << 25), + OPC_RISC_XOR = OPC_RISC_ARITH | (0x4 << 12) | (0x00 << 25), + OPC_RISC_SRL = OPC_RISC_ARITH | (0x5 << 12) | (0x00 << 25), + OPC_RISC_SRA = OPC_RISC_ARITH | (0x5 << 12) | (0x20 << 25), + OPC_RISC_OR = OPC_RISC_ARITH | (0x6 << 12) | (0x00 << 25), + OPC_RISC_AND = OPC_RISC_ARITH | (0x7 << 12) | (0x00 << 25), + + /* RV64M */ + OPC_RISC_MUL = OPC_RISC_ARITH | (0x0 << 12) | (0x01 << 25), + OPC_RISC_MULH = OPC_RISC_ARITH | (0x1 << 12) | (0x01 << 25), + OPC_RISC_MULHSU = OPC_RISC_ARITH | (0x2 << 12) | (0x01 << 25), + OPC_RISC_MULHU = OPC_RISC_ARITH | (0x3 << 12) | (0x01 << 25), + + OPC_RISC_DIV = OPC_RISC_ARITH | (0x4 << 12) | (0x01 << 25), + OPC_RISC_DIVU = OPC_RISC_ARITH | (0x5 << 12) | (0x01 << 25), + OPC_RISC_REM = OPC_RISC_ARITH | (0x6 << 12) | (0x01 << 25), + OPC_RISC_REMU = OPC_RISC_ARITH | (0x7 << 12) | (0x01 << 25), +}; + + +#define MASK_OP_ARITH_IMM(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) +enum { + OPC_RISC_ADDI = OPC_RISC_ARITH_IMM | (0x0 << 12), + OPC_RISC_SLTI = OPC_RISC_ARITH_IMM | (0x2 << 12), + OPC_RISC_SLTIU = OPC_RISC_ARITH_IMM | (0x3 << 12), + OPC_RISC_XORI = OPC_RISC_ARITH_IMM | (0x4 << 12), + OPC_RISC_ORI = OPC_RISC_ARITH_IMM | (0x6 << 12), + OPC_RISC_ANDI = OPC_RISC_ARITH_IMM | (0x7 << 12), + OPC_RISC_SLLI = OPC_RISC_ARITH_IMM | (0x1 << 12), /* additional part of + IMM */ + OPC_RISC_SHIFT_RIGHT_I = OPC_RISC_ARITH_IMM | (0x5 << 12) /* SRAI, SRLI */ +}; + +#define MASK_OP_BRANCH(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) +enum { + OPC_RISC_BEQ = OPC_RISC_BRANCH | (0x0 << 12), + OPC_RISC_BNE = OPC_RISC_BRANCH | (0x1 << 12), + OPC_RISC_BLT = OPC_RISC_BRANCH | (0x4 << 12), + OPC_RISC_BGE = OPC_RISC_BRANCH | (0x5 << 12), + OPC_RISC_BLTU = OPC_RISC_BRANCH | (0x6 << 12), + OPC_RISC_BGEU = OPC_RISC_BRANCH | (0x7 << 12) +}; + +enum { + OPC_RISC_ADDIW = OPC_RISC_ARITH_IMM_W | (0x0 << 12), + OPC_RISC_SLLIW = OPC_RISC_ARITH_IMM_W | (0x1 << 12), /* additional part of + IMM */ + OPC_RISC_SHIFT_RIGHT_IW = OPC_RISC_ARITH_IMM_W | (0x5 << 12) /* SRAI, SRLI + */ +}; + +enum { + OPC_RISC_ADDW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x00 << 25), + OPC_RISC_SUBW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x20 << 25), + OPC_RISC_SLLW = OPC_RISC_ARITH_W | (0x1 << 12) | (0x00 << 25), + OPC_RISC_SRLW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x00 << 25), + OPC_RISC_SRAW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x20 << 25), + + /* RV64M */ + OPC_RISC_MULW = OPC_RISC_ARITH_W | (0x0 << 12) | (0x01 << 25), + OPC_RISC_DIVW = OPC_RISC_ARITH_W | (0x4 << 12) | (0x01 << 25), + OPC_RISC_DIVUW = OPC_RISC_ARITH_W | (0x5 << 12) | (0x01 << 25), + OPC_RISC_REMW = OPC_RISC_ARITH_W | (0x6 << 12) | (0x01 << 25), + OPC_RISC_REMUW = OPC_RISC_ARITH_W | (0x7 << 12) | (0x01 << 25), +}; + +#define MASK_OP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) +enum { + OPC_RISC_LB = OPC_RISC_LOAD | (0x0 << 12), + OPC_RISC_LH = OPC_RISC_LOAD | (0x1 << 12), + OPC_RISC_LW = OPC_RISC_LOAD | (0x2 << 12), + OPC_RISC_LD = OPC_RISC_LOAD | (0x3 << 12), + OPC_RISC_LBU = OPC_RISC_LOAD | (0x4 << 12), + OPC_RISC_LHU = OPC_RISC_LOAD | (0x5 << 12), + OPC_RISC_LWU = OPC_RISC_LOAD | (0x6 << 12), +}; + +#define MASK_OP_STORE(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) +enum { + OPC_RISC_SB = OPC_RISC_STORE | (0x0 << 12), + OPC_RISC_SH = OPC_RISC_STORE | (0x1 << 12), + OPC_RISC_SW = OPC_RISC_STORE | (0x2 << 12), + OPC_RISC_SD = OPC_RISC_STORE | (0x3 << 12), +}; + +#define MASK_OP_JALR(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) +/* no enum since OPC_RISC_JALR is the actual value */ + +#define MASK_OP_ATOMIC(op) \ + (MASK_OP_MAJOR(op) | (op & ((0x7 << 12) | (0x7F << 25)))) +#define MASK_OP_ATOMIC_NO_AQ_RL_SZ(op) \ + (MASK_OP_MAJOR(op) | (op & (0x1F << 27))) + +enum { + OPC_RISC_LR = OPC_RISC_ATOMIC | (0x02 << 27), + OPC_RISC_SC = OPC_RISC_ATOMIC | (0x03 << 27), + OPC_RISC_AMOSWAP = OPC_RISC_ATOMIC | (0x01 << 27), + OPC_RISC_AMOADD = OPC_RISC_ATOMIC | (0x00 << 27), + OPC_RISC_AMOXOR = OPC_RISC_ATOMIC | (0x04 << 27), + OPC_RISC_AMOAND = OPC_RISC_ATOMIC | (0x0C << 27), + OPC_RISC_AMOOR = OPC_RISC_ATOMIC | (0x08 << 27), + OPC_RISC_AMOMIN = OPC_RISC_ATOMIC | (0x10 << 27), + OPC_RISC_AMOMAX = OPC_RISC_ATOMIC | (0x14 << 27), + OPC_RISC_AMOMINU = OPC_RISC_ATOMIC | (0x18 << 27), + OPC_RISC_AMOMAXU = OPC_RISC_ATOMIC | (0x1C << 27), +}; + +#define MASK_OP_SYSTEM(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) +enum { + OPC_RISC_ECALL = OPC_RISC_SYSTEM | (0x0 << 12), + OPC_RISC_EBREAK = OPC_RISC_SYSTEM | (0x0 << 12), + OPC_RISC_ERET = OPC_RISC_SYSTEM | (0x0 << 12), + OPC_RISC_MRTS = OPC_RISC_SYSTEM | (0x0 << 12), + OPC_RISC_MRTH = OPC_RISC_SYSTEM | (0x0 << 12), + OPC_RISC_HRTS = OPC_RISC_SYSTEM | (0x0 << 12), + OPC_RISC_WFI = OPC_RISC_SYSTEM | (0x0 << 12), + OPC_RISC_SFENCEVM = OPC_RISC_SYSTEM | (0x0 << 12), + + OPC_RISC_CSRRW = OPC_RISC_SYSTEM | (0x1 << 12), + OPC_RISC_CSRRS = OPC_RISC_SYSTEM | (0x2 << 12), + OPC_RISC_CSRRC = OPC_RISC_SYSTEM | (0x3 << 12), + OPC_RISC_CSRRWI = OPC_RISC_SYSTEM | (0x5 << 12), + OPC_RISC_CSRRSI = OPC_RISC_SYSTEM | (0x6 << 12), + OPC_RISC_CSRRCI = OPC_RISC_SYSTEM | (0x7 << 12), +}; + +#define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) +enum { + OPC_RISC_FLW = OPC_RISC_FP_LOAD | (0x2 << 12), + OPC_RISC_FLD = OPC_RISC_FP_LOAD | (0x3 << 12), +}; + +#define MASK_OP_FP_STORE(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) +enum { + OPC_RISC_FSW = OPC_RISC_FP_STORE | (0x2 << 12), + OPC_RISC_FSD = OPC_RISC_FP_STORE | (0x3 << 12), +}; + +#define MASK_OP_FP_FMADD(op) (MASK_OP_MAJOR(op) | (op & (0x3 << 25))) +enum { + OPC_RISC_FMADD_S = OPC_RISC_FMADD | (0x0 << 25), + OPC_RISC_FMADD_D = OPC_RISC_FMADD | (0x1 << 25), +}; + +#define MASK_OP_FP_FMSUB(op) (MASK_OP_MAJOR(op) | (op & (0x3 << 25))) +enum { + OPC_RISC_FMSUB_S = OPC_RISC_FMSUB | (0x0 << 25), + OPC_RISC_FMSUB_D = OPC_RISC_FMSUB | (0x1 << 25), +}; + +#define MASK_OP_FP_FNMADD(op) (MASK_OP_MAJOR(op) | (op & (0x3 << 25))) +enum { + OPC_RISC_FNMADD_S = OPC_RISC_FNMADD | (0x0 << 25), + OPC_RISC_FNMADD_D = OPC_RISC_FNMADD | (0x1 << 25), +}; + +#define MASK_OP_FP_FNMSUB(op) (MASK_OP_MAJOR(op) | (op & (0x3 << 25))) +enum { + OPC_RISC_FNMSUB_S = OPC_RISC_FNMSUB | (0x0 << 25), + OPC_RISC_FNMSUB_D = OPC_RISC_FNMSUB | (0x1 << 25), +}; + +#define MASK_OP_FP_ARITH(op) (MASK_OP_MAJOR(op) | (op & (0x7F << 25))) +enum { + /* float */ + OPC_RISC_FADD_S = OPC_RISC_FP_ARITH | (0x0 << 25), + OPC_RISC_FSUB_S = OPC_RISC_FP_ARITH | (0x4 << 25), + OPC_RISC_FMUL_S = OPC_RISC_FP_ARITH | (0x8 << 25), + OPC_RISC_FDIV_S = OPC_RISC_FP_ARITH | (0xC << 25), + + OPC_RISC_FSGNJ_S = OPC_RISC_FP_ARITH | (0x10 << 25), + OPC_RISC_FSGNJN_S = OPC_RISC_FP_ARITH | (0x10 << 25), + OPC_RISC_FSGNJX_S = OPC_RISC_FP_ARITH | (0x10 << 25), + + OPC_RISC_FMIN_S = OPC_RISC_FP_ARITH | (0x14 << 25), + OPC_RISC_FMAX_S = OPC_RISC_FP_ARITH | (0x14 << 25), + + OPC_RISC_FSQRT_S = OPC_RISC_FP_ARITH | (0x2C << 25), + + OPC_RISC_FEQ_S = OPC_RISC_FP_ARITH | (0x50 << 25), + OPC_RISC_FLT_S = OPC_RISC_FP_ARITH | (0x50 << 25), + OPC_RISC_FLE_S = OPC_RISC_FP_ARITH | (0x50 << 25), + + OPC_RISC_FCVT_W_S = OPC_RISC_FP_ARITH | (0x60 << 25), + OPC_RISC_FCVT_WU_S = OPC_RISC_FP_ARITH | (0x60 << 25), + OPC_RISC_FCVT_L_S = OPC_RISC_FP_ARITH | (0x60 << 25), + OPC_RISC_FCVT_LU_S = OPC_RISC_FP_ARITH | (0x60 << 25), + + OPC_RISC_FCVT_S_W = OPC_RISC_FP_ARITH | (0x68 << 25), + OPC_RISC_FCVT_S_WU = OPC_RISC_FP_ARITH | (0x68 << 25), + OPC_RISC_FCVT_S_L = OPC_RISC_FP_ARITH | (0x68 << 25), + OPC_RISC_FCVT_S_LU = OPC_RISC_FP_ARITH | (0x68 << 25), + + OPC_RISC_FMV_X_S = OPC_RISC_FP_ARITH | (0x70 << 25), + OPC_RISC_FCLASS_S = OPC_RISC_FP_ARITH | (0x70 << 25), + + OPC_RISC_FMV_S_X = OPC_RISC_FP_ARITH | (0x78 << 25), + + /* double */ + OPC_RISC_FADD_D = OPC_RISC_FP_ARITH | (0x1 << 25), + OPC_RISC_FSUB_D = OPC_RISC_FP_ARITH | (0x5 << 25), + OPC_RISC_FMUL_D = OPC_RISC_FP_ARITH | (0x9 << 25), + OPC_RISC_FDIV_D = OPC_RISC_FP_ARITH | (0xD << 25), + + OPC_RISC_FSGNJ_D = OPC_RISC_FP_ARITH | (0x11 << 25), + OPC_RISC_FSGNJN_D = OPC_RISC_FP_ARITH | (0x11 << 25), + OPC_RISC_FSGNJX_D = OPC_RISC_FP_ARITH | (0x11 << 25), + + OPC_RISC_FMIN_D = OPC_RISC_FP_ARITH | (0x15 << 25), + OPC_RISC_FMAX_D = OPC_RISC_FP_ARITH | (0x15 << 25), + + OPC_RISC_FCVT_S_D = OPC_RISC_FP_ARITH | (0x20 << 25), + + OPC_RISC_FCVT_D_S = OPC_RISC_FP_ARITH | (0x21 << 25), + + OPC_RISC_FSQRT_D = OPC_RISC_FP_ARITH | (0x2D << 25), + + OPC_RISC_FEQ_D = OPC_RISC_FP_ARITH | (0x51 << 25), + OPC_RISC_FLT_D = OPC_RISC_FP_ARITH | (0x51 << 25), + OPC_RISC_FLE_D = OPC_RISC_FP_ARITH | (0x51 << 25), + + OPC_RISC_FCVT_W_D = OPC_RISC_FP_ARITH | (0x61 << 25), + OPC_RISC_FCVT_WU_D = OPC_RISC_FP_ARITH | (0x61 << 25), + OPC_RISC_FCVT_L_D = OPC_RISC_FP_ARITH | (0x61 << 25), + OPC_RISC_FCVT_LU_D = OPC_RISC_FP_ARITH | (0x61 << 25), + + OPC_RISC_FCVT_D_W = OPC_RISC_FP_ARITH | (0x69 << 25), + OPC_RISC_FCVT_D_WU = OPC_RISC_FP_ARITH | (0x69 << 25), + OPC_RISC_FCVT_D_L = OPC_RISC_FP_ARITH | (0x69 << 25), + OPC_RISC_FCVT_D_LU = OPC_RISC_FP_ARITH | (0x69 << 25), + + OPC_RISC_FMV_X_D = OPC_RISC_FP_ARITH | (0x71 << 25), + OPC_RISC_FCLASS_D = OPC_RISC_FP_ARITH | (0x71 << 25), + + OPC_RISC_FMV_D_X = OPC_RISC_FP_ARITH | (0x79 << 25), +}; + +#define GET_B_IMM(inst) ((extract32(inst, 8, 4) << 1) \ + | (extract32(inst, 25, 6) << 5) \ + | (extract32(inst, 7, 1) << 11) \ + | (sextract64(inst, 31, 1) << 12)) + +#define GET_STORE_IMM(inst) ((extract32(inst, 7, 5)) \ + | (sextract64(inst, 25, 7) << 5)) + +#define GET_JAL_IMM(inst) ((extract32(inst, 21, 10) << 1) \ + | (extract32(inst, 20, 1) << 11) \ + | (extract32(inst, 12, 8) << 12) \ + | (sextract64(inst, 31, 1) << 20)) + +#define GET_RM(inst) extract32(inst, 12, 3) +#define GET_RS3(inst) extract32(inst, 27, 5) +#define GET_RS1(inst) extract32(inst, 15, 5) +#define GET_RS2(inst) extract32(inst, 20, 5) +#define GET_RD(inst) extract32(inst, 7, 5) +#define GET_IMM(inst) sextract64(inst, 20, 12) + +/* RVC decoding macros */ +#define GET_C_IMM(inst) (extract32(inst, 2, 5) \ + | (sextract64(inst, 12, 1) << 5)) +#define GET_C_ZIMM(inst) (extract32(inst, 2, 5) \ + | (extract32(inst, 12, 1) << 5)) +#define GET_C_ADDI4SPN_IMM(inst) ((extract32(inst, 6, 1) << 2) \ + | (extract32(inst, 5, 1) << 3) \ + | (extract32(inst, 11, 2) << 4) \ + | (extract32(inst, 7, 4) << 6)) +#define GET_C_ADDI16SP_IMM(inst) ((extract32(inst, 6, 1) << 4) \ + | (extract32(inst, 2, 1) << 5) \ + | (extract32(inst, 5, 1) << 6) \ + | (extract32(inst, 3, 2) << 7) \ + | (sextract64(inst, 12, 1) << 9)) +#define GET_C_LWSP_IMM(inst) ((extract32(inst, 4, 3) << 2) \ + | (extract32(inst, 12, 1) << 5) \ + | (extract32(inst, 2, 2) << 6)) +#define GET_C_LDSP_IMM(inst) ((extract32(inst, 5, 2) << 3) \ + | (extract32(inst, 12, 1) << 5) \ + | (extract32(inst, 2, 3) << 6)) +#define GET_C_SWSP_IMM(inst) ((extract32(inst, 9, 4) << 2) \ + | (extract32(inst, 7, 2) << 6)) +#define GET_C_SDSP_IMM(inst) ((extract32(inst, 10, 3) << 3) \ + | (extract32(inst, 7, 3) << 6)) +#define GET_C_LW_IMM(inst) ((extract32(inst, 6, 1) << 2) \ + | (extract32(inst, 10, 3) << 3) \ + | (extract32(inst, 5, 1) << 6)) +#define GET_C_LD_IMM(inst) ((extract32(inst, 10, 3) << 3) \ + | (extract32(inst, 5, 2) << 6)) +#define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ + | (extract32(inst, 11, 1) << 4) \ + | (extract32(inst, 2, 1) << 5) \ + | (extract32(inst, 7, 1) << 6) \ + | (extract32(inst, 6, 1) << 7) \ + | (extract32(inst, 9, 2) << 8) \ + | (extract32(inst, 8, 1) << 10) \ + | (sextract64(inst, 12, 1) << 11)) +#define GET_C_B_IMM(inst) ((extract32(inst, 3, 2) << 1) \ + | (extract32(inst, 10, 2) << 3) \ + | (extract32(inst, 2, 1) << 5) \ + | (extract32(inst, 5, 2) << 6) \ + | (sextract64(inst, 12, 1) << 8)) +#define GET_C_SIMM3(inst) extract32(inst, 10, 3) +#define GET_C_RD(inst) GET_RD(inst) +#define GET_C_RS1(inst) GET_RD(inst) +#define GET_C_RS2(inst) extract32(inst, 2, 5) +#define GET_C_RS1S(inst) (8 + extract32(inst, 7, 3)) +#define GET_C_RS2S(inst) (8 + extract32(inst, 2, 3)) diff --git a/qemu/target/riscv/op_helper.c b/qemu/target/riscv/op_helper.c new file mode 100644 index 00000000..d73f5de2 --- /dev/null +++ b/qemu/target/riscv/op_helper.c @@ -0,0 +1,782 @@ +/* + * RISC-V Emulation Helpers for QEMU. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * Copyright (c) 2017-2018 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" + +#ifndef CONFIG_USER_ONLY + +#if defined(TARGET_RISCV32) +static const char valid_vm_1_09[16] = { + [VM_1_09_MBARE] = 1, + [VM_1_09_SV32] = 1, +}; +static const char valid_vm_1_10[16] = { + [VM_1_10_MBARE] = 1, + [VM_1_10_SV32] = 1 +}; +#elif defined(TARGET_RISCV64) +static const char valid_vm_1_09[16] = { + [VM_1_09_MBARE] = 1, + [VM_1_09_SV39] = 1, + [VM_1_09_SV48] = 1, +}; +static const char valid_vm_1_10[16] = { + [VM_1_10_MBARE] = 1, + [VM_1_10_SV39] = 1, + [VM_1_10_SV48] = 1, + [VM_1_10_SV57] = 1 +}; +#endif + +static int validate_vm(CPURISCVState *env, target_ulong vm) +{ + return (env->priv_ver >= PRIV_VERSION_1_10_0) ? + valid_vm_1_10[vm & 0xf] : valid_vm_1_09[vm & 0xf]; +} + +#endif + +/* Exceptions processing helpers */ +void QEMU_NORETURN do_raise_exception_err(CPURISCVState *env, + uint32_t exception, uintptr_t pc) +{ + CPUState *cs = CPU(riscv_env_get_cpu(env)); + qemu_log_mask(CPU_LOG_INT, "%s: %d\n", __func__, exception); + cs->exception_index = exception; + cpu_loop_exit_restore(cs, pc); +} + +void helper_raise_exception(CPURISCVState *env, uint32_t exception) +{ + do_raise_exception_err(env, exception, 0); +} + +static void validate_mstatus_fs(CPURISCVState *env, uintptr_t ra) +{ +#ifndef CONFIG_USER_ONLY + if (!(env->mstatus & MSTATUS_FS)) { + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, ra); + } +#endif +} + +/* + * Handle writes to CSRs and any resulting special behavior + * + * Adapted from Spike's processor_t::set_csr + */ +void csr_write_helper(CPURISCVState *env, target_ulong val_to_write, + target_ulong csrno) +{ +#ifndef CONFIG_USER_ONLY + uint64_t delegable_ints = MIP_SSIP | MIP_STIP | MIP_SEIP | (1 << IRQ_X_COP); + uint64_t all_ints = delegable_ints | MIP_MSIP | MIP_MTIP; +#endif + + switch (csrno) { + case CSR_FFLAGS: + validate_mstatus_fs(env, GETPC()); + cpu_riscv_set_fflags(env, val_to_write & (FSR_AEXC >> FSR_AEXC_SHIFT)); + break; + case CSR_FRM: + validate_mstatus_fs(env, GETPC()); + env->frm = val_to_write & (FSR_RD >> FSR_RD_SHIFT); + break; + case CSR_FCSR: + validate_mstatus_fs(env, GETPC()); + env->frm = (val_to_write & FSR_RD) >> FSR_RD_SHIFT; + cpu_riscv_set_fflags(env, (val_to_write & FSR_AEXC) >> FSR_AEXC_SHIFT); + break; +#ifndef CONFIG_USER_ONLY + case CSR_MSTATUS: { + target_ulong mstatus = env->mstatus; + target_ulong mask = 0; + target_ulong mpp = get_field(val_to_write, MSTATUS_MPP); + + /* flush tlb on mstatus fields that affect VM */ + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + if ((val_to_write ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | + MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_VM)) { + helper_riscv_tlb_flush(env); + } + mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | + MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | + MSTATUS_MPP | MSTATUS_MXR | + (validate_vm(env, get_field(val_to_write, MSTATUS_VM)) ? + MSTATUS_VM : 0); + } + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + if ((val_to_write ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | + MSTATUS_MPRV | MSTATUS_SUM)) { + helper_riscv_tlb_flush(env); + } + mask = MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | + MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | + MSTATUS_MPP | MSTATUS_MXR; + } + + /* silenty discard mstatus.mpp writes for unsupported modes */ + if (mpp == PRV_H || + (!riscv_has_ext(env, RVS) && mpp == PRV_S) || + (!riscv_has_ext(env, RVU) && mpp == PRV_U)) { + mask &= ~MSTATUS_MPP; + } + + mstatus = (mstatus & ~mask) | (val_to_write & mask); + + /* Note: this is a workaround for an issue where mstatus.FS + does not report dirty after floating point operations + that modify floating point state. This workaround is + technically compliant with the RISC-V Privileged + specification as it is legal to return only off, or dirty. + at the expense of extra floating point save/restore. */ + + /* FP is always dirty or off */ + if (mstatus & MSTATUS_FS) { + mstatus |= MSTATUS_FS; + } + + int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | + ((mstatus & MSTATUS_XS) == MSTATUS_XS); + mstatus = set_field(mstatus, MSTATUS_SD, dirty); + env->mstatus = mstatus; + break; + } + case CSR_MIP: { + /* + * Since the writeable bits in MIP are not set asynchrously by the + * CLINT, no additional locking is needed for read-modifiy-write + * CSR operations + */ + // Unicorn: commented out + //qemu_mutex_lock_iothread(); + RISCVCPU *cpu = riscv_env_get_cpu(env); + riscv_set_local_interrupt(cpu, MIP_SSIP, + (val_to_write & MIP_SSIP) != 0); + riscv_set_local_interrupt(cpu, MIP_STIP, + (val_to_write & MIP_STIP) != 0); + /* + * csrs, csrc on mip.SEIP is not decomposable into separate read and + * write steps, so a different implementation is needed + */ + // Unicorn: commented out + //qemu_mutex_unlock_iothread(); + break; + } + case CSR_MIE: { + env->mie = (env->mie & ~all_ints) | + (val_to_write & all_ints); + break; + } + case CSR_MIDELEG: + env->mideleg = (env->mideleg & ~delegable_ints) + | (val_to_write & delegable_ints); + break; + case CSR_MEDELEG: { + target_ulong mask = 0; + mask |= 1ULL << (RISCV_EXCP_INST_ADDR_MIS); + mask |= 1ULL << (RISCV_EXCP_INST_ACCESS_FAULT); + mask |= 1ULL << (RISCV_EXCP_ILLEGAL_INST); + mask |= 1ULL << (RISCV_EXCP_BREAKPOINT); + mask |= 1ULL << (RISCV_EXCP_LOAD_ADDR_MIS); + mask |= 1ULL << (RISCV_EXCP_LOAD_ACCESS_FAULT); + mask |= 1ULL << (RISCV_EXCP_STORE_AMO_ADDR_MIS); + mask |= 1ULL << (RISCV_EXCP_STORE_AMO_ACCESS_FAULT); + mask |= 1ULL << (RISCV_EXCP_U_ECALL); + mask |= 1ULL << (RISCV_EXCP_S_ECALL); + mask |= 1ULL << (RISCV_EXCP_H_ECALL); + mask |= 1ULL << (RISCV_EXCP_M_ECALL); + mask |= 1ULL << (RISCV_EXCP_INST_PAGE_FAULT); + mask |= 1ULL << (RISCV_EXCP_LOAD_PAGE_FAULT); + mask |= 1ULL << (RISCV_EXCP_STORE_PAGE_FAULT); + env->medeleg = (env->medeleg & ~mask) + | (val_to_write & mask); + break; + } + case CSR_MINSTRET: + /* minstret is WARL so unsupported writes are ignored */ + break; + case CSR_MCYCLE: + /* mcycle is WARL so unsupported writes are ignored */ + break; +#if defined(TARGET_RISCV32) + case CSR_MINSTRETH: + /* minstreth is WARL so unsupported writes are ignored */ + break; + case CSR_MCYCLEH: + /* mcycleh is WARL so unsupported writes are ignored */ + break; +#endif + case CSR_MUCOUNTEREN: + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + env->scounteren = val_to_write; + break; + } else { + goto do_illegal; + } + case CSR_MSCOUNTEREN: + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + env->mcounteren = val_to_write; + break; + } else { + goto do_illegal; + } + case CSR_SSTATUS: { + target_ulong ms = env->mstatus; + target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE + | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS + | SSTATUS_SUM | SSTATUS_SD; + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + mask |= SSTATUS_MXR; + } + ms = (ms & ~mask) | (val_to_write & mask); + csr_write_helper(env, ms, CSR_MSTATUS); + break; + } + case CSR_SIP: { + // Unicorn: commented out + //qemu_mutex_lock_iothread(); + target_ulong next_mip = (env->mip & ~env->mideleg) + | (val_to_write & env->mideleg); + // Unicorn: commented out + //qemu_mutex_unlock_iothread(); + csr_write_helper(env, next_mip, CSR_MIP); + break; + } + case CSR_SIE: { + target_ulong next_mie = (env->mie & ~env->mideleg) + | (val_to_write & env->mideleg); + csr_write_helper(env, next_mie, CSR_MIE); + break; + } + case CSR_SATP: /* CSR_SPTBR */ { + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + break; + } + if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val_to_write ^ env->sptbr)) + { + helper_riscv_tlb_flush(env); + env->sptbr = val_to_write & (((target_ulong) + 1 << (TARGET_PHYS_ADDR_SPACE_BITS - PGSHIFT)) - 1); + } + if (env->priv_ver >= PRIV_VERSION_1_10_0 && + validate_vm(env, get_field(val_to_write, SATP_MODE)) && + ((val_to_write ^ env->satp) & (SATP_MODE | SATP_ASID | SATP_PPN))) + { + helper_riscv_tlb_flush(env); + env->satp = val_to_write; + } + break; + } + case CSR_SEPC: + env->sepc = val_to_write; + break; + case CSR_STVEC: + /* bits [1:0] encode mode; 0 = direct, 1 = vectored, 2 >= reserved */ + if ((val_to_write & 3) == 0) { + env->stvec = val_to_write >> 2 << 2; + } else { + qemu_log_mask(LOG_UNIMP, + "CSR_STVEC: vectored traps not supported\n"); + } + break; + case CSR_SCOUNTEREN: + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + env->scounteren = val_to_write; + break; + } else { + goto do_illegal; + } + case CSR_SSCRATCH: + env->sscratch = val_to_write; + break; + case CSR_SCAUSE: + env->scause = val_to_write; + break; + case CSR_SBADADDR: + env->sbadaddr = val_to_write; + break; + case CSR_MEPC: + env->mepc = val_to_write; + break; + case CSR_MTVEC: + /* bits [1:0] indicate mode; 0 = direct, 1 = vectored, 2 >= reserved */ + if ((val_to_write & 3) == 0) { + env->mtvec = val_to_write >> 2 << 2; + } else { + qemu_log_mask(LOG_UNIMP, + "CSR_MTVEC: vectored traps not supported\n"); + } + break; + case CSR_MCOUNTEREN: + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + env->mcounteren = val_to_write; + break; + } else { + goto do_illegal; + } + case CSR_MSCRATCH: + env->mscratch = val_to_write; + break; + case CSR_MCAUSE: + env->mcause = val_to_write; + break; + case CSR_MBADADDR: + env->mbadaddr = val_to_write; + break; + case CSR_MISA: + /* misa is WARL so unsupported writes are ignored */ + break; + case CSR_PMPCFG0: + case CSR_PMPCFG1: + case CSR_PMPCFG2: + case CSR_PMPCFG3: + pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val_to_write); + break; + case CSR_PMPADDR0: + case CSR_PMPADDR1: + case CSR_PMPADDR2: + case CSR_PMPADDR3: + case CSR_PMPADDR4: + case CSR_PMPADDR5: + case CSR_PMPADDR6: + case CSR_PMPADDR7: + case CSR_PMPADDR8: + case CSR_PMPADDR9: + case CSR_PMPADDR10: + case CSR_PMPADDR11: + case CSR_PMPADDR12: + case CSR_PMPADDR13: + case CSR_PMPADDR14: + case CSR_PMPADDR15: + pmpaddr_csr_write(env, csrno - CSR_PMPADDR0, val_to_write); + break; +#endif +#if !defined(CONFIG_USER_ONLY) + do_illegal: +#endif + default: + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } +} + +/* + * Handle reads to CSRs and any resulting special behavior + * + * Adapted from Spike's processor_t::get_csr + */ +target_ulong csr_read_helper(CPURISCVState *env, target_ulong csrno) +{ +#ifndef CONFIG_USER_ONLY + target_ulong ctr_en = env->priv == PRV_U ? env->scounteren : + env->priv == PRV_S ? env->mcounteren : -1U; +#else + target_ulong ctr_en = -1; +#endif + target_ulong ctr_ok = (ctr_en >> (csrno & 31)) & 1; + + if (csrno >= CSR_HPMCOUNTER3 && csrno <= CSR_HPMCOUNTER31) { + if (ctr_ok) { + return 0; + } + } +#if defined(TARGET_RISCV32) + if (csrno >= CSR_HPMCOUNTER3H && csrno <= CSR_HPMCOUNTER31H) { + if (ctr_ok) { + return 0; + } + } +#endif + if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) { + return 0; + } +#if defined(TARGET_RISCV32) + if (csrno >= CSR_MHPMCOUNTER3 && csrno <= CSR_MHPMCOUNTER31) { + return 0; + } +#endif + if (csrno >= CSR_MHPMEVENT3 && csrno <= CSR_MHPMEVENT31) { + return 0; + } + + switch (csrno) { + case CSR_FFLAGS: + validate_mstatus_fs(env, GETPC()); + return cpu_riscv_get_fflags(env); + case CSR_FRM: + validate_mstatus_fs(env, GETPC()); + return env->frm; + case CSR_FCSR: + validate_mstatus_fs(env, GETPC()); + return (cpu_riscv_get_fflags(env) << FSR_AEXC_SHIFT) + | (env->frm << FSR_RD_SHIFT); + /* rdtime/rdtimeh is trapped and emulated by bbl in system mode */ +#ifdef CONFIG_USER_ONLY + case CSR_TIME: + // Unicorn: Commented out + //return cpu_get_host_ticks(); + // Unicorn: Default value: + return 0; +#if defined(TARGET_RISCV32) + case CSR_TIMEH: + // Unicorn: Commented out + //return cpu_get_host_ticks() >> 32; + // Unicorn: Default value + return 0; +#endif +#endif + case CSR_INSTRET: + case CSR_CYCLE: + if (ctr_ok) { +#if !defined(CONFIG_USER_ONLY) + // Unicorn: commented out + /*if (use_icount) { + return cpu_get_icount(); + } else { + return cpu_get_host_ticks(); + }*/ + // Unicorn: Default value: + return 0; +#else + // Unicorn: Default value + //return cpu_get_host_ticks(); + return 0; +#endif + } + break; +#if defined(TARGET_RISCV32) + case CSR_INSTRETH: + case CSR_CYCLEH: + if (ctr_ok) { +#if !defined(CONFIG_USER_ONLY) + // Unicorn commented out + /*if (use_icount) { + return cpu_get_icount() >> 32; + } else { + return cpu_get_host_ticks() >> 32; + } + */ + // Unicorn: default value + return 0; +#else + // Unicorn: default value + // return cpu_get_host_ticks() >> 32; + return 0; +#endif + } + break; +#endif +#ifndef CONFIG_USER_ONLY + case CSR_MINSTRET: + case CSR_MCYCLE: + // Unicorn: Commented out + /*if (use_icount) { + return cpu_get_icount(); + } else { + return cpu_get_host_ticks(); + } + */ + // Unicorn: default value + return 0; + case CSR_MINSTRETH: + case CSR_MCYCLEH: +#if defined(TARGET_RISCV32) + // Unicorn commented out + /*if (use_icount) { + return cpu_get_icount() >> 32; + } else { + return cpu_get_host_ticks() >> 32; + }*/ + // Unicorn: default value + return 0; +#endif + break; + case CSR_MUCOUNTEREN: + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + return env->scounteren; + } else { + break; /* illegal instruction */ + } + case CSR_MSCOUNTEREN: + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + return env->mcounteren; + } else { + break; /* illegal instruction */ + } + case CSR_SSTATUS: { + target_ulong mask = SSTATUS_SIE | SSTATUS_SPIE | SSTATUS_UIE + | SSTATUS_UPIE | SSTATUS_SPP | SSTATUS_FS | SSTATUS_XS + | SSTATUS_SUM | SSTATUS_SD; + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + mask |= SSTATUS_MXR; + } + return env->mstatus & mask; + } + case CSR_SIP: { + // Unicorn: commented out + //qemu_mutex_lock_iothread(); + target_ulong tmp = env->mip & env->mideleg; + // Unicorn: commented out + //qemu_mutex_unlock_iothread(); + return tmp; + } + case CSR_SIE: + return env->mie & env->mideleg; + case CSR_SEPC: + return env->sepc; + case CSR_SBADADDR: + return env->sbadaddr; + case CSR_STVEC: + return env->stvec; + case CSR_SCOUNTEREN: + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + return env->scounteren; + } else { + break; /* illegal instruction */ + } + case CSR_SCAUSE: + return env->scause; + case CSR_SATP: /* CSR_SPTBR */ + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + return 0; + } + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + return env->satp; + } else { + return env->sptbr; + } + case CSR_SSCRATCH: + return env->sscratch; + case CSR_MSTATUS: + return env->mstatus; + case CSR_MIP: { + // Unicorn: commented out + //qemu_mutex_lock_iothread(); + target_ulong tmp = env->mip; + // Unicorn: commented out + //qemu_mutex_unlock_iothread(); + return tmp; + } + case CSR_MIE: + return env->mie; + case CSR_MEPC: + return env->mepc; + case CSR_MSCRATCH: + return env->mscratch; + case CSR_MCAUSE: + return env->mcause; + case CSR_MBADADDR: + return env->mbadaddr; + case CSR_MISA: + return env->misa; + case CSR_MARCHID: + return 0; /* as spike does */ + case CSR_MIMPID: + return 0; /* as spike does */ + case CSR_MVENDORID: + return 0; /* as spike does */ + case CSR_MHARTID: + return env->mhartid; + case CSR_MTVEC: + return env->mtvec; + case CSR_MCOUNTEREN: + if (env->priv_ver >= PRIV_VERSION_1_10_0) { + return env->mcounteren; + } else { + break; /* illegal instruction */ + } + case CSR_MEDELEG: + return env->medeleg; + case CSR_MIDELEG: + return env->mideleg; + case CSR_PMPCFG0: + case CSR_PMPCFG1: + case CSR_PMPCFG2: + case CSR_PMPCFG3: + return pmpcfg_csr_read(env, csrno - CSR_PMPCFG0); + case CSR_PMPADDR0: + case CSR_PMPADDR1: + case CSR_PMPADDR2: + case CSR_PMPADDR3: + case CSR_PMPADDR4: + case CSR_PMPADDR5: + case CSR_PMPADDR6: + case CSR_PMPADDR7: + case CSR_PMPADDR8: + case CSR_PMPADDR9: + case CSR_PMPADDR10: + case CSR_PMPADDR11: + case CSR_PMPADDR12: + case CSR_PMPADDR13: + case CSR_PMPADDR14: + case CSR_PMPADDR15: + return pmpaddr_csr_read(env, csrno - CSR_PMPADDR0); +#endif + } + /* used by e.g. MTIME read */ + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); +} + +/* + * Check that CSR access is allowed. + * + * Adapted from Spike's decode.h:validate_csr + */ +static void validate_csr(CPURISCVState *env, uint64_t which, + uint64_t write, uintptr_t ra) +{ +#ifndef CONFIG_USER_ONLY + unsigned csr_priv = get_field((which), 0x300); + unsigned csr_read_only = get_field((which), 0xC00) == 3; + if (((write) && csr_read_only) || (env->priv < csr_priv)) { + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, ra); + } +#endif +} + +target_ulong helper_csrrw(CPURISCVState *env, target_ulong src, + target_ulong csr) +{ + validate_csr(env, csr, 1, GETPC()); + uint64_t csr_backup = csr_read_helper(env, csr); + csr_write_helper(env, src, csr); + return csr_backup; +} + +target_ulong helper_csrrs(CPURISCVState *env, target_ulong src, + target_ulong csr, target_ulong rs1_pass) +{ + validate_csr(env, csr, rs1_pass != 0, GETPC()); + uint64_t csr_backup = csr_read_helper(env, csr); + if (rs1_pass != 0) { + csr_write_helper(env, src | csr_backup, csr); + } + return csr_backup; +} + +target_ulong helper_csrrc(CPURISCVState *env, target_ulong src, + target_ulong csr, target_ulong rs1_pass) +{ + validate_csr(env, csr, rs1_pass != 0, GETPC()); + uint64_t csr_backup = csr_read_helper(env, csr); + if (rs1_pass != 0) { + csr_write_helper(env, (~src) & csr_backup, csr); + } + return csr_backup; +} + +#ifndef CONFIG_USER_ONLY + +/* iothread_mutex must be held */ +void riscv_set_local_interrupt(RISCVCPU *cpu, target_ulong mask, int value) +{ + target_ulong old_mip = cpu->env.mip; + cpu->env.mip = (old_mip & ~mask) | (value ? mask : 0); + + if (cpu->env.mip && !old_mip) { + cpu_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + } else if (!cpu->env.mip && old_mip) { + cpu_reset_interrupt(CPU(cpu), CPU_INTERRUPT_HARD); + } +} + +void riscv_set_mode(CPURISCVState *env, target_ulong newpriv) +{ + if (newpriv > PRV_M) { + g_assert_not_reached(); + } + if (newpriv == PRV_H) { + newpriv = PRV_U; + } + /* tlb_flush is unnecessary as mode is contained in mmu_idx */ + env->priv = newpriv; +} + +target_ulong helper_sret(CPURISCVState *env, target_ulong cpu_pc_deb) +{ + if (!(env->priv >= PRV_S)) { + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + target_ulong retpc = env->sepc; + if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { + do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + } + + target_ulong mstatus = env->mstatus; + target_ulong prev_priv = get_field(mstatus, MSTATUS_SPP); + mstatus = set_field(mstatus, + env->priv_ver >= PRIV_VERSION_1_10_0 ? + MSTATUS_SIE : MSTATUS_UIE << prev_priv, + get_field(mstatus, MSTATUS_SPIE)); + mstatus = set_field(mstatus, MSTATUS_SPIE, 0); + mstatus = set_field(mstatus, MSTATUS_SPP, PRV_U); + riscv_set_mode(env, prev_priv); + csr_write_helper(env, mstatus, CSR_MSTATUS); + + return retpc; +} + +target_ulong helper_mret(CPURISCVState *env, target_ulong cpu_pc_deb) +{ + if (!(env->priv >= PRV_M)) { + do_raise_exception_err(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); + } + + target_ulong retpc = env->mepc; + if (!riscv_has_ext(env, RVC) && (retpc & 0x3)) { + do_raise_exception_err(env, RISCV_EXCP_INST_ADDR_MIS, GETPC()); + } + + target_ulong mstatus = env->mstatus; + target_ulong prev_priv = get_field(mstatus, MSTATUS_MPP); + mstatus = set_field(mstatus, + env->priv_ver >= PRIV_VERSION_1_10_0 ? + MSTATUS_MIE : MSTATUS_UIE << prev_priv, + get_field(mstatus, MSTATUS_MPIE)); + mstatus = set_field(mstatus, MSTATUS_MPIE, 0); + mstatus = set_field(mstatus, MSTATUS_MPP, PRV_U); + riscv_set_mode(env, prev_priv); + csr_write_helper(env, mstatus, CSR_MSTATUS); + + return retpc; +} + + +void helper_wfi(CPURISCVState *env) +{ + CPUState *cs = CPU(riscv_env_get_cpu(env)); + + cs->halted = 1; + cs->exception_index = EXCP_HLT; + cpu_loop_exit(cs); +} + +void helper_riscv_tlb_flush(CPURISCVState *env) +{ + RISCVCPU *cpu = riscv_env_get_cpu(env); + CPUState *cs = CPU(cpu); + tlb_flush(cs); +} + +#endif /* !CONFIG_USER_ONLY */ diff --git a/qemu/target/riscv/pmp.c b/qemu/target/riscv/pmp.c new file mode 100644 index 00000000..f432f3b7 --- /dev/null +++ b/qemu/target/riscv/pmp.c @@ -0,0 +1,380 @@ +/* + * QEMU RISC-V PMP (Physical Memory Protection) + * + * Author: Daire McNamara, daire.mcnamara@emdalo.com + * Ivan Griffin, ivan.griffin@emdalo.com + * + * This provides a RISC-V Physical Memory Protection implementation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +/* + * PMP (Physical Memory Protection) is as-of-yet unused and needs testing. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "cpu.h" +#include "qemu-common.h" + +#ifndef CONFIG_USER_ONLY + +#define RISCV_DEBUG_PMP 0 +#define PMP_DEBUG(fmt, ...) \ + do { \ + if (RISCV_DEBUG_PMP) { \ + qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\ + } \ + } while (0) + +static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, + uint8_t val); +static uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t addr_index); +static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index); + +/* + * Accessor method to extract address matching type 'a field' from cfg reg + */ +static inline uint8_t pmp_get_a_field(uint8_t cfg) +{ + uint8_t a = cfg >> 3; + return a & 0x3; +} + +/* + * Check whether a PMP is locked or not. + */ +static inline int pmp_is_locked(CPURISCVState *env, uint32_t pmp_index) +{ + + if (env->pmp_state.pmp[pmp_index].cfg_reg & PMP_LOCK) { + return 1; + } + + /* Top PMP has no 'next' to check */ + if ((pmp_index + 1u) >= MAX_RISCV_PMPS) { + return 0; + } + + /* In TOR mode, need to check the lock bit of the next pmp + * (if there is a next) + */ + const uint8_t a_field = + pmp_get_a_field(env->pmp_state.pmp[pmp_index + 1].cfg_reg); + if ((env->pmp_state.pmp[pmp_index + 1u].cfg_reg & PMP_LOCK) && + (PMP_AMATCH_TOR == a_field)) { + return 1; + } + + return 0; +} + +/* + * Count the number of active rules. + */ +static inline uint32_t pmp_get_num_rules(CPURISCVState *env) +{ + return env->pmp_state.num_rules; +} + +/* + * Accessor to get the cfg reg for a specific PMP/HART + */ +static inline uint8_t pmp_read_cfg(CPURISCVState *env, uint32_t pmp_index) +{ + if (pmp_index < MAX_RISCV_PMPS) { + return env->pmp_state.pmp[pmp_index].cfg_reg; + } + + return 0; +} + + +/* + * Accessor to set the cfg reg for a specific PMP/HART + * Bounds checks and relevant lock bit. + */ +static void pmp_write_cfg(CPURISCVState *env, uint32_t pmp_index, uint8_t val) +{ + if (pmp_index < MAX_RISCV_PMPS) { + if (!pmp_is_locked(env, pmp_index)) { + env->pmp_state.pmp[pmp_index].cfg_reg = val; + pmp_update_rule(env, pmp_index); + } else { + PMP_DEBUG("ignoring write - locked"); + } + } else { + PMP_DEBUG("ignoring write - out of bounds"); + } +} + +static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) +{ + /* + aaaa...aaa0 8-byte NAPOT range + aaaa...aa01 16-byte NAPOT range + aaaa...a011 32-byte NAPOT range + ... + aa01...1111 2^XLEN-byte NAPOT range + a011...1111 2^(XLEN+1)-byte NAPOT range + 0111...1111 2^(XLEN+2)-byte NAPOT range + 1111...1111 Reserved + */ + if (a == -1) { + *sa = 0u; + *ea = -1; + return; + } else { + target_ulong t1 = ctz64(~a); + target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 3; + target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1; + *sa = base; + *ea = base + range; + } +} + + +/* Convert cfg/addr reg values here into simple 'sa' --> start address and 'ea' + * end address values. + * This function is called relatively infrequently whereas the check that + * an address is within a pmp rule is called often, so optimise that one + */ +static void pmp_update_rule(CPURISCVState *env, uint32_t pmp_index) +{ + int i; + + env->pmp_state.num_rules = 0; + + uint8_t this_cfg = env->pmp_state.pmp[pmp_index].cfg_reg; + target_ulong this_addr = env->pmp_state.pmp[pmp_index].addr_reg; + target_ulong prev_addr = 0u; + target_ulong sa = 0u; + target_ulong ea = 0u; + + if (pmp_index >= 1u) { + prev_addr = env->pmp_state.pmp[pmp_index - 1].addr_reg; + } + + switch (pmp_get_a_field(this_cfg)) { + case PMP_AMATCH_OFF: + sa = 0u; + ea = -1; + break; + + case PMP_AMATCH_TOR: + sa = prev_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ + ea = (this_addr << 2) - 1u; + break; + + case PMP_AMATCH_NA4: + sa = this_addr << 2; /* shift up from [xx:0] to [xx+2:2] */ + ea = (this_addr + 4u) - 1u; + break; + + case PMP_AMATCH_NAPOT: + pmp_decode_napot(this_addr, &sa, &ea); + break; + + default: + sa = 0u; + ea = 0u; + break; + } + + env->pmp_state.addr[pmp_index].sa = sa; + env->pmp_state.addr[pmp_index].ea = ea; + + for (i = 0; i < MAX_RISCV_PMPS; i++) { + const uint8_t a_field = + pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); + if (PMP_AMATCH_OFF != a_field) { + env->pmp_state.num_rules++; + } + } +} + +static int pmp_is_in_range(CPURISCVState *env, int pmp_index, target_ulong addr) +{ + int result = 0; + + if ((addr >= env->pmp_state.addr[pmp_index].sa) + && (addr <= env->pmp_state.addr[pmp_index].ea)) { + result = 1; + } else { + result = 0; + } + + return result; +} + + +/* + * Public Interface + */ + +/* + * Check if the address has required RWX privs to complete desired operation + */ +bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, + target_ulong size, pmp_priv_t privs) +{ + int i = 0; + int ret = -1; + target_ulong s = 0; + target_ulong e = 0; + pmp_priv_t allowed_privs = 0; + + /* Short cut if no rules */ + if (0 == pmp_get_num_rules(env)) { + return true; + } + + /* 1.10 draft priv spec states there is an implicit order + from low to high */ + for (i = 0; i < MAX_RISCV_PMPS; i++) { + s = pmp_is_in_range(env, i, addr); + e = pmp_is_in_range(env, i, addr + size); + + /* partially inside */ + if ((s + e) == 1) { + PMP_DEBUG("pmp violation - access is partially inside"); + ret = 0; + break; + } + + /* fully inside */ + const uint8_t a_field = + pmp_get_a_field(env->pmp_state.pmp[i].cfg_reg); + if ((s + e) == 2) { + if (PMP_AMATCH_OFF == a_field) { + return 1; + } + + allowed_privs = PMP_READ | PMP_WRITE | PMP_EXEC; + if ((env->priv != PRV_M) || pmp_is_locked(env, i)) { + allowed_privs &= env->pmp_state.pmp[i].cfg_reg; + } + + if ((privs & allowed_privs) == privs) { + ret = 1; + break; + } else { + ret = 0; + break; + } + } + } + + /* No rule matched */ + if (ret == -1) { + if (env->priv == PRV_M) { + ret = 1; /* Privileged spec v1.10 states if no PMP entry matches an + * M-Mode access, the access succeeds */ + } else { + ret = 0; /* Other modes are not allowed to succeed if they don't + * match a rule, but there are rules. We've checked for + * no rule earlier in this function. */ + } + } + + return ret == 1 ? true : false; +} + + +/* + * Handle a write to a pmpcfg CSP + */ +void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, + target_ulong val) +{ + int i; + uint8_t cfg_val; + + PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, + env->mhartid, reg_index, val); + + if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { + PMP_DEBUG("ignoring write - incorrect address"); + return; + } + + for (i = 0; i < sizeof(target_ulong); i++) { + cfg_val = (val >> 8 * i) & 0xff; + pmp_write_cfg(env, (reg_index * sizeof(target_ulong)) + i, + cfg_val); + } +} + + +/* + * Handle a read from a pmpcfg CSP + */ +target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) +{ + int i; + target_ulong cfg_val = 0; + uint8_t val = 0; + + for (i = 0; i < sizeof(target_ulong); i++) { + val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); + cfg_val |= (val << (i * 8)); + } + + PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, + env->mhartid, reg_index, cfg_val); + + return cfg_val; +} + + +/* + * Handle a write to a pmpaddr CSP + */ +void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, + target_ulong val) +{ + PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, + env->mhartid, addr_index, val); + + if (addr_index < MAX_RISCV_PMPS) { + if (!pmp_is_locked(env, addr_index)) { + env->pmp_state.pmp[addr_index].addr_reg = val; + pmp_update_rule(env, addr_index); + } else { + PMP_DEBUG("ignoring write - locked"); + } + } else { + PMP_DEBUG("ignoring write - out of bounds"); + } +} + + +/* + * Handle a read from a pmpaddr CSP + */ +target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) +{ + PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, + env->mhartid, addr_index, + env->pmp_state.pmp[addr_index].addr_reg); + if (addr_index < MAX_RISCV_PMPS) { + return env->pmp_state.pmp[addr_index].addr_reg; + } else { + PMP_DEBUG("ignoring read - out of bounds"); + return 0; + } +} + +#endif diff --git a/qemu/target/riscv/pmp.h b/qemu/target/riscv/pmp.h new file mode 100644 index 00000000..e3953c88 --- /dev/null +++ b/qemu/target/riscv/pmp.h @@ -0,0 +1,64 @@ +/* + * QEMU RISC-V PMP (Physical Memory Protection) + * + * Author: Daire McNamara, daire.mcnamara@emdalo.com + * Ivan Griffin, ivan.griffin@emdalo.com + * + * This provides a RISC-V Physical Memory Protection interface + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#ifndef _RISCV_PMP_H_ +#define _RISCV_PMP_H_ + +typedef enum { + PMP_READ = 1 << 0, + PMP_WRITE = 1 << 1, + PMP_EXEC = 1 << 2, + PMP_LOCK = 1 << 7 +} pmp_priv_t; + +typedef enum { + PMP_AMATCH_OFF, /* Null (off) */ + PMP_AMATCH_TOR, /* Top of Range */ + PMP_AMATCH_NA4, /* Naturally aligned four-byte region */ + PMP_AMATCH_NAPOT /* Naturally aligned power-of-two region */ +} pmp_am_t; + +typedef struct { + target_ulong addr_reg; + uint8_t cfg_reg; +} pmp_entry_t; + +typedef struct { + target_ulong sa; + target_ulong ea; +} pmp_addr_t; + +typedef struct { + pmp_entry_t pmp[MAX_RISCV_PMPS]; + pmp_addr_t addr[MAX_RISCV_PMPS]; + uint32_t num_rules; +} pmp_table_t; + +void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, + target_ulong val); +target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index); +void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, + target_ulong val); +target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index); +bool pmp_hart_has_privs(CPURISCVState *env, target_ulong addr, + target_ulong size, pmp_priv_t priv); + +#endif diff --git a/qemu/target/riscv/translate.c b/qemu/target/riscv/translate.c new file mode 100644 index 00000000..f69e7f15 --- /dev/null +++ b/qemu/target/riscv/translate.c @@ -0,0 +1,1974 @@ +/* + * RISC-V emulation for qemu: main translation routines. + * + * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "unicorn/platform.h" + +#include "qemu/log.h" +#include "cpu.h" +#include "tcg-op.h" +#include "exec/cpu_ldst.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" + +#include "exec/translator.h" + +#include "instmap.h" + +#include "exec/gen-icount.h" + +#include "uc_priv.h" + +typedef struct DisasContext { + DisasContextBase base; + /* pc_succ_insn points to the instruction following base.pc_next */ + target_ulong pc_succ_insn; + uint32_t opcode; + uint32_t flags; + uint32_t mem_idx; + /* Remember the rounding mode encoded in the previous fp instruction, + which we have already installed into env->fp_status. Or -1 for + no previous fp instruction. Note that we exit the TB when writing + to any system register, which includes CSR_FRM, so we do not have + to reset this known value. */ + int frm; + + // Unicorn engine. + struct uc_struct *uc; +} DisasContext; + +/* convert riscv funct3 to qemu memop for load/store */ +static const int tcg_memop_lookup[8] = { + [0 ... 7] = -1, + [0] = MO_SB, + [1] = MO_TESW, + [2] = MO_TESL, + [4] = MO_UB, + [5] = MO_TEUW, +#ifdef TARGET_RISCV64 + [3] = MO_TEQ, + [6] = MO_TEUL, +#endif +}; + +#ifdef TARGET_RISCV64 +#define CASE_OP_32_64(X) case X: case glue(X, W) +#else +#define CASE_OP_32_64(X) case X +#endif + +static void generate_exception(DisasContext *ctx, int excp) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, ctx->base.pc_next); + TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, excp); + gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, helper_tmp); + tcg_temp_free_i32(tcg_ctx, helper_tmp); + ctx->base.is_jmp = DISAS_NORETURN; +} + +static void generate_exception_mbadaddr(DisasContext *ctx, int excp) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, ctx->base.pc_next); + tcg_gen_st_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, tcg_ctx->cpu_env, offsetof(CPURISCVState, badaddr)); + TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, excp); + gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, helper_tmp); + tcg_temp_free_i32(tcg_ctx, helper_tmp); + ctx->base.is_jmp = DISAS_NORETURN; +} + +static void gen_exception_debug(DisasContext *ctx) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, EXCP_DEBUG); + gen_helper_raise_exception(tcg_ctx, tcg_ctx->cpu_env, helper_tmp); + tcg_temp_free_i32(tcg_ctx, helper_tmp); +} + +static void gen_exception_illegal(DisasContext *ctx) +{ + generate_exception(ctx, RISCV_EXCP_ILLEGAL_INST); +} + +static void gen_exception_inst_addr_mis(DisasContext *ctx) +{ + generate_exception_mbadaddr(ctx, RISCV_EXCP_INST_ADDR_MIS); +} + +static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) +{ + if (unlikely(ctx->base.singlestep_enabled)) { + return false; + } + +#ifndef CONFIG_USER_ONLY + return (ctx->base.tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK); +#else + return true; +#endif +} + +static void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + if (use_goto_tb(ctx, dest)) { + /* chaining is only allowed when the jump is to the same page */ + tcg_gen_goto_tb(tcg_ctx, n); + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, dest); + tcg_gen_exit_tb(tcg_ctx, ctx->base.tb, n); + } else { + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, dest); + if (ctx->base.singlestep_enabled) { + gen_exception_debug(ctx); + } else { + tcg_gen_lookup_and_goto_ptr(tcg_ctx); + } + } +} + +/* Wrapper for getting reg values - need to check of reg is zero since + * cpu_gpr[0] is not actually allocated + */ +static inline void gen_get_gpr(DisasContext *ctx, TCGv t, int reg_num) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + if (reg_num == 0) { + tcg_gen_movi_tl(tcg_ctx, t, 0); + } else { + tcg_gen_mov_tl(tcg_ctx, t, tcg_ctx->riscv_cpu_gpr[reg_num]); + } +} + +/* Wrapper for setting reg values - need to check of reg is zero since + * cpu_gpr[0] is not actually allocated. this is more for safety purposes, + * since we usually avoid calling the OP_TYPE_gen function if we see a write to + * $zero + */ +static inline void gen_set_gpr(DisasContext *ctx, int reg_num_dst, TCGv t) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + if (reg_num_dst != 0) { + tcg_gen_mov_tl(tcg_ctx, tcg_ctx->riscv_cpu_gpr[reg_num_dst], t); + } +} + +static void gen_mulhsu(DisasContext *ctx, TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv rl = tcg_temp_new(tcg_ctx); + TCGv rh = tcg_temp_new(tcg_ctx); + + tcg_gen_mulu2_tl(tcg_ctx, rl, rh, arg1, arg2); + /* fix up for one negative */ + tcg_gen_sari_tl(tcg_ctx, rl, arg1, TARGET_LONG_BITS - 1); + tcg_gen_and_tl(tcg_ctx, rl, rl, arg2); + tcg_gen_sub_tl(tcg_ctx, ret, rh, rl); + + tcg_temp_free(tcg_ctx, rl); + tcg_temp_free(tcg_ctx, rh); +} + +static void gen_fsgnj(DisasContext *ctx, uint32_t rd, uint32_t rs1, + uint32_t rs2, int rm, uint64_t min) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + switch (rm) { + case 0: /* fsgnj */ + if (rs1 == rs2) { /* FMOV */ + tcg_gen_mov_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->riscv_cpu_fpr[rs1]); + } else { + tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs1], + 0, min == INT32_MIN ? 31 : 63); + } + break; + case 1: /* fsgnjn */ + if (rs1 == rs2) { /* FNEG */ + tcg_gen_xori_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->riscv_cpu_fpr[rs1], min); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(tcg_ctx); + tcg_gen_not_i64(tcg_ctx, t0, tcg_ctx->riscv_cpu_fpr[rs2]); + tcg_gen_deposit_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], t0, tcg_ctx->riscv_cpu_fpr[rs1], + 0, min == INT32_MIN ? 31 : 63); + tcg_temp_free_i64(tcg_ctx, t0); + } + break; + case 2: /* fsgnjx */ + if (rs1 == rs2) { /* FABS */ + tcg_gen_andi_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->riscv_cpu_fpr[rs1], ~min); + } else { + TCGv_i64 t0 = tcg_temp_new_i64(tcg_ctx); + tcg_gen_andi_i64(tcg_ctx, t0, tcg_ctx->riscv_cpu_fpr[rs2], min); + tcg_gen_xor_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->riscv_cpu_fpr[rs1], t0); + tcg_temp_free_i64(tcg_ctx, t0); + } + break; + default: + gen_exception_illegal(ctx); + } +} + +static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs1, + int rs2) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv source1, source2, cond1, cond2, zeroreg, resultopt1; + source1 = tcg_temp_new(tcg_ctx); + source2 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, source1, rs1); + gen_get_gpr(ctx, source2, rs2); + + switch (opc) { + CASE_OP_32_64(OPC_RISC_ADD): + tcg_gen_add_tl(tcg_ctx, source1, source1, source2); + break; + CASE_OP_32_64(OPC_RISC_SUB): + tcg_gen_sub_tl(tcg_ctx, source1, source1, source2); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_SLLW: + tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); + tcg_gen_shl_tl(tcg_ctx, source1, source1, source2); + break; +#endif + case OPC_RISC_SLL: + tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1); + tcg_gen_shl_tl(tcg_ctx, source1, source1, source2); + break; + case OPC_RISC_SLT: + tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LT, source1, source1, source2); + break; + case OPC_RISC_SLTU: + tcg_gen_setcond_tl(tcg_ctx, TCG_COND_LTU, source1, source1, source2); + break; + case OPC_RISC_XOR: + tcg_gen_xor_tl(tcg_ctx, source1, source1, source2); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_SRLW: + /* clear upper 32 */ + tcg_gen_ext32u_tl(tcg_ctx, source1, source1); + tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); + tcg_gen_shr_tl(tcg_ctx, source1, source1, source2); + break; +#endif + case OPC_RISC_SRL: + tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1); + tcg_gen_shr_tl(tcg_ctx, source1, source1, source2); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_SRAW: + /* first, trick to get it to act like working on 32 bits (get rid of + upper 32, sign extend to fill space) */ + tcg_gen_ext32s_tl(tcg_ctx, source1, source1); + tcg_gen_andi_tl(tcg_ctx, source2, source2, 0x1F); + tcg_gen_sar_tl(tcg_ctx, source1, source1, source2); + break; +#endif + case OPC_RISC_SRA: + tcg_gen_andi_tl(tcg_ctx, source2, source2, TARGET_LONG_BITS - 1); + tcg_gen_sar_tl(tcg_ctx, source1, source1, source2); + break; + case OPC_RISC_OR: + tcg_gen_or_tl(tcg_ctx, source1, source1, source2); + break; + case OPC_RISC_AND: + tcg_gen_and_tl(tcg_ctx, source1, source1, source2); + break; + CASE_OP_32_64(OPC_RISC_MUL): + tcg_gen_mul_tl(tcg_ctx, source1, source1, source2); + break; + case OPC_RISC_MULH: + tcg_gen_muls2_tl(tcg_ctx, source2, source1, source1, source2); + break; + case OPC_RISC_MULHSU: + gen_mulhsu(ctx, source1, source1, source2); + break; + case OPC_RISC_MULHU: + tcg_gen_mulu2_tl(tcg_ctx, source2, source1, source1, source2); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_DIVW: + tcg_gen_ext32s_tl(tcg_ctx, source1, source1); + tcg_gen_ext32s_tl(tcg_ctx, source2, source2); + /* fall through to DIV */ +#endif + case OPC_RISC_DIV: + /* Handle by altering args to tcg_gen_div to produce req'd results: + * For overflow: want source1 in source1 and 1 in source2 + * For div by zero: want -1 in source1 and 1 in source2 -> -1 result */ + cond1 = tcg_temp_new(tcg_ctx); + cond2 = tcg_temp_new(tcg_ctx); + zeroreg = tcg_const_tl(tcg_ctx, 0); + resultopt1 = tcg_temp_new(tcg_ctx); + + tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)-1); + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, (target_ulong)(~0L)); + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source1, + ((target_ulong)1) << (TARGET_LONG_BITS - 1)); + tcg_gen_and_tl(tcg_ctx, cond1, cond1, cond2); /* cond1 = overflow */ + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, 0); /* cond2 = div 0 */ + /* if div by zero, set source1 to -1, otherwise don't change */ + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond2, zeroreg, source1, + resultopt1); + /* if overflow or div by zero, set source2 to 1, else don't change */ + tcg_gen_or_tl(tcg_ctx, cond1, cond1, cond2); + tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_div_tl(tcg_ctx, source1, source1, source2); + + tcg_temp_free(tcg_ctx, cond1); + tcg_temp_free(tcg_ctx, cond2); + tcg_temp_free(tcg_ctx, zeroreg); + tcg_temp_free(tcg_ctx, resultopt1); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_DIVUW: + tcg_gen_ext32u_tl(tcg_ctx, source1, source1); + tcg_gen_ext32u_tl(tcg_ctx, source2, source2); + /* fall through to DIVU */ +#endif + case OPC_RISC_DIVU: + cond1 = tcg_temp_new(tcg_ctx); + zeroreg = tcg_const_tl(tcg_ctx, 0); + resultopt1 = tcg_temp_new(tcg_ctx); + + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0); + tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)-1); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond1, zeroreg, source1, + resultopt1); + tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_divu_tl(tcg_ctx, source1, source1, source2); + + tcg_temp_free(tcg_ctx, cond1); + tcg_temp_free(tcg_ctx, zeroreg); + tcg_temp_free(tcg_ctx, resultopt1); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_REMW: + tcg_gen_ext32s_tl(tcg_ctx, source1, source1); + tcg_gen_ext32s_tl(tcg_ctx, source2, source2); + /* fall through to REM */ +#endif + case OPC_RISC_REM: + cond1 = tcg_temp_new(tcg_ctx); + cond2 = tcg_temp_new(tcg_ctx); + zeroreg = tcg_const_tl(tcg_ctx, 0); + resultopt1 = tcg_temp_new(tcg_ctx); + + tcg_gen_movi_tl(tcg_ctx, resultopt1, 1L); + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond2, source2, (target_ulong)-1); + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source1, + (target_ulong)1 << (TARGET_LONG_BITS - 1)); + tcg_gen_and_tl(tcg_ctx, cond2, cond1, cond2); /* cond1 = overflow */ + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0); /* cond2 = div 0 */ + /* if overflow or div by zero, set source2 to 1, else don't change */ + tcg_gen_or_tl(tcg_ctx, cond2, cond1, cond2); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond2, zeroreg, source2, + resultopt1); + tcg_gen_rem_tl(tcg_ctx, resultopt1, source1, source2); + /* if div by zero, just return the original dividend */ + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond1, zeroreg, resultopt1, + source1); + + tcg_temp_free(tcg_ctx, cond1); + tcg_temp_free(tcg_ctx, cond2); + tcg_temp_free(tcg_ctx, zeroreg); + tcg_temp_free(tcg_ctx, resultopt1); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_REMUW: + tcg_gen_ext32u_tl(tcg_ctx, source1, source1); + tcg_gen_ext32u_tl(tcg_ctx, source2, source2); + /* fall through to REMU */ +#endif + case OPC_RISC_REMU: + cond1 = tcg_temp_new(tcg_ctx); + zeroreg = tcg_const_tl(tcg_ctx, 0); + resultopt1 = tcg_temp_new(tcg_ctx); + + tcg_gen_movi_tl(tcg_ctx, resultopt1, (target_ulong)1); + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_EQ, cond1, source2, 0); + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source2, cond1, zeroreg, source2, + resultopt1); + tcg_gen_remu_tl(tcg_ctx, resultopt1, source1, source2); + /* if div by zero, just return the original dividend */ + tcg_gen_movcond_tl(tcg_ctx, TCG_COND_EQ, source1, cond1, zeroreg, resultopt1, + source1); + + tcg_temp_free(tcg_ctx, cond1); + tcg_temp_free(tcg_ctx, zeroreg); + tcg_temp_free(tcg_ctx, resultopt1); + break; + default: + gen_exception_illegal(ctx); + return; + } + + if (opc & 0x8) { /* sign extend for W instructions */ + tcg_gen_ext32s_tl(tcg_ctx, source1, source1); + } + + gen_set_gpr(ctx, rd, source1); + tcg_temp_free(tcg_ctx, source1); + tcg_temp_free(tcg_ctx, source2); +} + +static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rd, + int rs1, target_long imm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv source1 = tcg_temp_new(tcg_ctx); + int shift_len = TARGET_LONG_BITS; + int shift_a; + + gen_get_gpr(ctx, source1, rs1); + + switch (opc) { + case OPC_RISC_ADDI: +#if defined(TARGET_RISCV64) + case OPC_RISC_ADDIW: +#endif + tcg_gen_addi_tl(tcg_ctx, source1, source1, imm); + break; + case OPC_RISC_SLTI: + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_LT, source1, source1, imm); + break; + case OPC_RISC_SLTIU: + tcg_gen_setcondi_tl(tcg_ctx, TCG_COND_LTU, source1, source1, imm); + break; + case OPC_RISC_XORI: + tcg_gen_xori_tl(tcg_ctx, source1, source1, imm); + break; + case OPC_RISC_ORI: + tcg_gen_ori_tl(tcg_ctx, source1, source1, imm); + break; + case OPC_RISC_ANDI: + tcg_gen_andi_tl(tcg_ctx, source1, source1, imm); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_SLLIW: + shift_len = 32; + /* FALLTHRU */ +#endif + case OPC_RISC_SLLI: + if (imm >= shift_len) { + goto do_illegal; + } + tcg_gen_shli_tl(tcg_ctx, source1, source1, imm); + break; +#if defined(TARGET_RISCV64) + case OPC_RISC_SHIFT_RIGHT_IW: + shift_len = 32; + /* FALLTHRU */ +#endif + case OPC_RISC_SHIFT_RIGHT_I: + /* differentiate on IMM */ + shift_a = imm & 0x400; + imm &= 0x3ff; + if (imm >= shift_len) { + goto do_illegal; + } + if (imm != 0) { + if (shift_a) { + /* SRAI[W] */ + tcg_gen_sextract_tl(tcg_ctx, source1, source1, imm, shift_len - imm); + } else { + /* SRLI[W] */ + tcg_gen_extract_tl(tcg_ctx, source1, source1, imm, shift_len - imm); + } + /* No further sign-extension needed for W instructions. */ + opc &= ~0x8; + } + break; + default: + do_illegal: + gen_exception_illegal(ctx); + return; + } + + if (opc & 0x8) { /* sign-extend for W instructions */ + tcg_gen_ext32s_tl(tcg_ctx, source1, source1); + } + + gen_set_gpr(ctx, rd, source1); + tcg_temp_free(tcg_ctx, source1); +} + +static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd, + target_ulong imm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + target_ulong next_pc; + + /* check misaligned: */ + next_pc = ctx->base.pc_next + imm; + if (!riscv_has_ext(env, RVC)) { + if ((next_pc & 0x3) != 0) { + gen_exception_inst_addr_mis(ctx); + return; + } + } + if (rd != 0) { + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_gpr[rd], ctx->pc_succ_insn); + } + + gen_goto_tb(ctx, 0, ctx->base.pc_next + imm); /* must use this for safety */ + ctx->base.is_jmp = DISAS_NORETURN; +} + +static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs1, target_long imm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + /* no chaining with JALR */ + TCGLabel *misaligned = NULL; + TCGv t0 = tcg_temp_new(tcg_ctx); + + switch (opc) { + case OPC_RISC_JALR: + gen_get_gpr(ctx, tcg_ctx->riscv_cpu_pc, rs1); + tcg_gen_addi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, tcg_ctx->riscv_cpu_pc, imm); + tcg_gen_andi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, tcg_ctx->riscv_cpu_pc, (target_ulong)-2); + + if (!riscv_has_ext(env, RVC)) { + misaligned = gen_new_label(tcg_ctx); + tcg_gen_andi_tl(tcg_ctx, t0, tcg_ctx->riscv_cpu_pc, 0x2); + tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, 0x0, misaligned); + } + + if (rd != 0) { + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_gpr[rd], ctx->pc_succ_insn); + } + tcg_gen_lookup_and_goto_ptr(tcg_ctx); + + if (misaligned) { + gen_set_label(tcg_ctx, misaligned); + gen_exception_inst_addr_mis(ctx); + } + ctx->base.is_jmp = DISAS_NORETURN; + break; + + default: + gen_exception_illegal(ctx); + break; + } + tcg_temp_free(tcg_ctx, t0); +} + +static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc, + int rs1, int rs2, target_long bimm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGLabel *l = gen_new_label(tcg_ctx); + TCGv source1, source2; + source1 = tcg_temp_new(tcg_ctx); + source2 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, source1, rs1); + gen_get_gpr(ctx, source2, rs2); + + switch (opc) { + case OPC_RISC_BEQ: + tcg_gen_brcond_tl(tcg_ctx, TCG_COND_EQ, source1, source2, l); + break; + case OPC_RISC_BNE: + tcg_gen_brcond_tl(tcg_ctx, TCG_COND_NE, source1, source2, l); + break; + case OPC_RISC_BLT: + tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LT, source1, source2, l); + break; + case OPC_RISC_BGE: + tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GE, source1, source2, l); + break; + case OPC_RISC_BLTU: + tcg_gen_brcond_tl(tcg_ctx, TCG_COND_LTU, source1, source2, l); + break; + case OPC_RISC_BGEU: + tcg_gen_brcond_tl(tcg_ctx, TCG_COND_GEU, source1, source2, l); + break; + default: + gen_exception_illegal(ctx); + return; + } + tcg_temp_free(tcg_ctx, source1); + tcg_temp_free(tcg_ctx, source2); + + gen_goto_tb(ctx, 1, ctx->pc_succ_insn); + gen_set_label(tcg_ctx, l); /* branch taken */ + if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) { + /* misaligned */ + gen_exception_inst_addr_mis(ctx); + } else { + gen_goto_tb(ctx, 0, ctx->base.pc_next + bimm); + } + ctx->base.is_jmp = DISAS_NORETURN; +} + +static void gen_load(DisasContext *ctx, uint32_t opc, int rd, int rs1, + target_long imm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv t0 = tcg_temp_new(tcg_ctx); + TCGv t1 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, rs1); + tcg_gen_addi_tl(tcg_ctx, t0, t0, imm); + int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; + + if (memop < 0) { + gen_exception_illegal(ctx); + return; + } + + tcg_gen_qemu_ld_tl(ctx->uc, t1, t0, ctx->mem_idx, memop); + gen_set_gpr(ctx, rd, t1); + tcg_temp_free(tcg_ctx, t0); + tcg_temp_free(tcg_ctx, t1); +} + +static void gen_store(DisasContext *ctx, uint32_t opc, int rs1, int rs2, + target_long imm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv t0 = tcg_temp_new(tcg_ctx); + TCGv dat = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, rs1); + tcg_gen_addi_tl(tcg_ctx, t0, t0, imm); + gen_get_gpr(ctx, dat, rs2); + int memop = tcg_memop_lookup[(opc >> 12) & 0x7]; + + if (memop < 0) { + gen_exception_illegal(ctx); + return; + } + + tcg_gen_qemu_st_tl(ctx->uc, dat, t0, ctx->mem_idx, memop); + tcg_temp_free(tcg_ctx, t0); + tcg_temp_free(tcg_ctx, dat); +} + +static void gen_fp_load(DisasContext *ctx, uint32_t opc, int rd, + int rs1, target_long imm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv t0; + + if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + gen_exception_illegal(ctx); + return; + } + + t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, rs1); + tcg_gen_addi_tl(tcg_ctx, t0, t0, imm); + + switch (opc) { + case OPC_RISC_FLW: + tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->riscv_cpu_fpr[rd], t0, ctx->mem_idx, MO_TEUL); + /* RISC-V requires NaN-boxing of narrower width floating point values */ + tcg_gen_ori_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->riscv_cpu_fpr[rd], 0xffffffff00000000ULL); + break; + case OPC_RISC_FLD: + tcg_gen_qemu_ld_i64(ctx->uc, tcg_ctx->riscv_cpu_fpr[rd], t0, ctx->mem_idx, MO_TEQ); + break; + default: + gen_exception_illegal(ctx); + break; + } + tcg_temp_free(tcg_ctx, t0); +} + +static void gen_fp_store(DisasContext *ctx, uint32_t opc, int rs1, + int rs2, target_long imm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv t0; + + if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + gen_exception_illegal(ctx); + return; + } + + t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, rs1); + tcg_gen_addi_tl(tcg_ctx, t0, t0, imm); + + switch (opc) { + case OPC_RISC_FSW: + tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->riscv_cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEUL); + break; + case OPC_RISC_FSD: + tcg_gen_qemu_st_i64(ctx->uc, tcg_ctx->riscv_cpu_fpr[rs2], t0, ctx->mem_idx, MO_TEQ); + break; + default: + gen_exception_illegal(ctx); + break; + } + + tcg_temp_free(tcg_ctx, t0); +} + +static void gen_atomic(DisasContext *ctx, uint32_t opc, + int rd, int rs1, int rs2) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv src1, src2, dat; + TCGLabel *l1, *l2; + TCGMemOp mop; + bool aq, rl; + + /* Extract the size of the atomic operation. */ + switch (extract32(opc, 12, 3)) { + case 2: /* 32-bit */ + mop = MO_ALIGN | MO_TESL; + break; +#if defined(TARGET_RISCV64) + case 3: /* 64-bit */ + mop = MO_ALIGN | MO_TEQ; + break; +#endif + default: + gen_exception_illegal(ctx); + return; + } + rl = extract32(opc, 25, 1); + aq = extract32(opc, 26, 1); + + src1 = tcg_temp_new(tcg_ctx); + src2 = tcg_temp_new(tcg_ctx); + + switch (MASK_OP_ATOMIC_NO_AQ_RL_SZ(opc)) { + case OPC_RISC_LR: + /* Put addr in load_res, data in load_val. */ + gen_get_gpr(ctx, src1, rs1); + if (rl) { + tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_STRL); + } + tcg_gen_qemu_ld_tl(ctx->uc, tcg_ctx->load_val, src1, ctx->mem_idx, mop); + if (aq) { + tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_LDAQ); + } + tcg_gen_mov_tl(tcg_ctx, tcg_ctx->load_res, src1); + gen_set_gpr(ctx, rd, tcg_ctx->load_val); + break; + + case OPC_RISC_SC: + l1 = gen_new_label(tcg_ctx); + l2 = gen_new_label(tcg_ctx); + dat = tcg_temp_new(tcg_ctx); + + gen_get_gpr(ctx, src1, rs1); + tcg_gen_brcond_tl(tcg_ctx, TCG_COND_NE, tcg_ctx->load_res, src1, l1); + + gen_get_gpr(ctx, src2, rs2); + /* Note that the TCG atomic primitives are SC, + so we can ignore AQ/RL along this path. */ + tcg_gen_atomic_cmpxchg_tl(tcg_ctx, src1, tcg_ctx->load_res, tcg_ctx->load_val, src2, + ctx->mem_idx, mop); + tcg_gen_setcond_tl(tcg_ctx, TCG_COND_NE, dat, src1, tcg_ctx->load_val); + gen_set_gpr(ctx, rd, dat); + tcg_gen_br(tcg_ctx, l2); + + gen_set_label(tcg_ctx, l1); + /* Address comparion failure. However, we still need to + provide the memory barrier implied by AQ/RL. */ + tcg_gen_mb(tcg_ctx, TCG_MO_ALL + aq * TCG_BAR_LDAQ + rl * TCG_BAR_STRL); + tcg_gen_movi_tl(tcg_ctx, dat, 1); + gen_set_gpr(ctx, rd, dat); + + gen_set_label(tcg_ctx, l2); + tcg_temp_free(tcg_ctx, dat); + break; + + case OPC_RISC_AMOSWAP: + /* Note that the TCG atomic primitives are SC, + so we can ignore AQ/RL along this path. */ + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_xchg_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + case OPC_RISC_AMOADD: + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_fetch_add_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + case OPC_RISC_AMOXOR: + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_fetch_xor_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + case OPC_RISC_AMOAND: + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_fetch_and_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + case OPC_RISC_AMOOR: + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_fetch_or_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + case OPC_RISC_AMOMIN: + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_fetch_smin_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + case OPC_RISC_AMOMAX: + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_fetch_smax_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + case OPC_RISC_AMOMINU: + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_fetch_umin_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + case OPC_RISC_AMOMAXU: + gen_get_gpr(ctx, src1, rs1); + gen_get_gpr(ctx, src2, rs2); + tcg_gen_atomic_fetch_umax_tl(tcg_ctx, src2, src1, src2, ctx->mem_idx, mop); + gen_set_gpr(ctx, rd, src2); + break; + + default: + gen_exception_illegal(ctx); + break; + } + + tcg_temp_free(tcg_ctx, src1); + tcg_temp_free(tcg_ctx, src2); +} + +static void gen_set_rm(DisasContext *ctx, int rm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv_i32 t0; + + if (ctx->frm == rm) { + return; + } + ctx->frm = rm; + t0 = tcg_const_i32(tcg_ctx, rm); + gen_helper_set_rounding_mode(tcg_ctx, tcg_ctx->cpu_env, t0); + tcg_temp_free_i32(tcg_ctx, t0); +} + +static void gen_fp_fmadd(DisasContext *ctx, uint32_t opc, int rd, + int rs1, int rs2, int rs3, int rm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + switch (opc) { + case OPC_RISC_FMADD_S: + gen_set_rm(ctx, rm); + gen_helper_fmadd_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], + tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs3]); + break; + case OPC_RISC_FMADD_D: + gen_set_rm(ctx, rm); + gen_helper_fmadd_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], + tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs3]); + break; + default: + gen_exception_illegal(ctx); + break; + } +} + +static void gen_fp_fmsub(DisasContext *ctx, uint32_t opc, int rd, + int rs1, int rs2, int rs3, int rm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + switch (opc) { + case OPC_RISC_FMSUB_S: + gen_set_rm(ctx, rm); + gen_helper_fmsub_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], + tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs3]); + break; + case OPC_RISC_FMSUB_D: + gen_set_rm(ctx, rm); + gen_helper_fmsub_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], + tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs3]); + break; + default: + gen_exception_illegal(ctx); + break; + } +} + +static void gen_fp_fnmsub(DisasContext *ctx, uint32_t opc, int rd, + int rs1, int rs2, int rs3, int rm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + switch (opc) { + case OPC_RISC_FNMSUB_S: + gen_set_rm(ctx, rm); + gen_helper_fnmsub_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], + tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs3]); + break; + case OPC_RISC_FNMSUB_D: + gen_set_rm(ctx, rm); + gen_helper_fnmsub_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], + tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs3]); + break; + default: + gen_exception_illegal(ctx); + break; + } +} + +static void gen_fp_fnmadd(DisasContext *ctx, uint32_t opc, int rd, + int rs1, int rs2, int rs3, int rm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + switch (opc) { + case OPC_RISC_FNMADD_S: + gen_set_rm(ctx, rm); + gen_helper_fnmadd_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], + tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs3]); + break; + case OPC_RISC_FNMADD_D: + gen_set_rm(ctx, rm); + gen_helper_fnmadd_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], + tcg_ctx->riscv_cpu_fpr[rs2], tcg_ctx->riscv_cpu_fpr[rs3]); + break; + default: + gen_exception_illegal(ctx); + break; + } +} + +static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, + int rs1, int rs2, int rm) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv t0 = NULL; + + if (!(ctx->flags & TB_FLAGS_FP_ENABLE)) { + goto do_illegal; + } + + switch (opc) { + case OPC_RISC_FADD_S: + gen_set_rm(ctx, rm); + gen_helper_fadd_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case OPC_RISC_FSUB_S: + gen_set_rm(ctx, rm); + gen_helper_fsub_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case OPC_RISC_FMUL_S: + gen_set_rm(ctx, rm); + gen_helper_fmul_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case OPC_RISC_FDIV_S: + gen_set_rm(ctx, rm); + gen_helper_fdiv_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case OPC_RISC_FSQRT_S: + gen_set_rm(ctx, rm); + gen_helper_fsqrt_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + case OPC_RISC_FSGNJ_S: + gen_fsgnj(ctx, rd, rs1, rs2, rm, INT32_MIN); + break; + + case OPC_RISC_FMIN_S: + /* also handles: OPC_RISC_FMAX_S */ + switch (rm) { + case 0x0: + gen_helper_fmin_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case 0x1: + gen_helper_fmax_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + default: + goto do_illegal; + } + break; + + case OPC_RISC_FEQ_S: + /* also handles: OPC_RISC_FLT_S, OPC_RISC_FLE_S */ + t0 = tcg_temp_new(tcg_ctx); + switch (rm) { + case 0x0: + gen_helper_fle_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case 0x1: + gen_helper_flt_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case 0x2: + gen_helper_feq_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + default: + goto do_illegal; + } + gen_set_gpr(ctx, rd, t0); + tcg_temp_free(tcg_ctx, t0); + break; + + case OPC_RISC_FCVT_W_S: + /* also OPC_RISC_FCVT_WU_S, OPC_RISC_FCVT_L_S, OPC_RISC_FCVT_LU_S */ + t0 = tcg_temp_new(tcg_ctx); + switch (rs2) { + case 0: /* FCVT_W_S */ + gen_set_rm(ctx, rm); + gen_helper_fcvt_w_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + case 1: /* FCVT_WU_S */ + gen_set_rm(ctx, rm); + gen_helper_fcvt_wu_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; +#if defined(TARGET_RISCV64) + case 2: /* FCVT_L_S */ + gen_set_rm(ctx, rm); + gen_helper_fcvt_l_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + case 3: /* FCVT_LU_S */ + gen_set_rm(ctx, rm); + gen_helper_fcvt_lu_s(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; +#endif + default: + goto do_illegal; + } + gen_set_gpr(ctx, rd, t0); + tcg_temp_free(tcg_ctx, t0); + break; + + case OPC_RISC_FCVT_S_W: + /* also OPC_RISC_FCVT_S_WU, OPC_RISC_FCVT_S_L, OPC_RISC_FCVT_S_LU */ + t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, rs1); + switch (rs2) { + case 0: /* FCVT_S_W */ + gen_set_rm(ctx, rm); + gen_helper_fcvt_s_w(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, t0); + break; + case 1: /* FCVT_S_WU */ + gen_set_rm(ctx, rm); + gen_helper_fcvt_s_wu(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, t0); + break; +#if defined(TARGET_RISCV64) + case 2: /* FCVT_S_L */ + gen_set_rm(ctx, rm); + gen_helper_fcvt_s_l(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, t0); + break; + case 3: /* FCVT_S_LU */ + gen_set_rm(ctx, rm); + gen_helper_fcvt_s_lu(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, t0); + break; +#endif + default: + goto do_illegal; + } + tcg_temp_free(tcg_ctx, t0); + break; + + case OPC_RISC_FMV_X_S: + /* also OPC_RISC_FCLASS_S */ + t0 = tcg_temp_new(tcg_ctx); + switch (rm) { + case 0: /* FMV */ +#if defined(TARGET_RISCV64) + tcg_gen_ext32s_tl(tcg_ctx, t0, tcg_ctx->riscv_cpu_fpr[rs1]); +#else + tcg_gen_extrl_i64_i32(tcg_ctx, t0, tcg_ctx->riscv_cpu_fpr[rs1]); +#endif + break; + case 1: + gen_helper_fclass_s(tcg_ctx, t0, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + default: + goto do_illegal; + } + gen_set_gpr(ctx, rd, t0); + tcg_temp_free(tcg_ctx, t0); + break; + + case OPC_RISC_FMV_S_X: + t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, rs1); +#if defined(TARGET_RISCV64) + tcg_gen_mov_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], t0); +#else + tcg_gen_extu_i32_i64(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], t0); +#endif + tcg_temp_free(tcg_ctx, t0); + break; + + /* double */ + case OPC_RISC_FADD_D: + gen_set_rm(ctx, rm); + gen_helper_fadd_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case OPC_RISC_FSUB_D: + gen_set_rm(ctx, rm); + gen_helper_fsub_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case OPC_RISC_FMUL_D: + gen_set_rm(ctx, rm); + gen_helper_fmul_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case OPC_RISC_FDIV_D: + gen_set_rm(ctx, rm); + gen_helper_fdiv_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case OPC_RISC_FSQRT_D: + gen_set_rm(ctx, rm); + gen_helper_fsqrt_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + case OPC_RISC_FSGNJ_D: + gen_fsgnj(ctx, rd, rs1, rs2, rm, INT64_MIN); + break; + + case OPC_RISC_FMIN_D: + /* also OPC_RISC_FMAX_D */ + switch (rm) { + case 0: + gen_helper_fmin_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case 1: + gen_helper_fmax_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + default: + goto do_illegal; + } + break; + + case OPC_RISC_FCVT_S_D: + switch (rs2) { + case 1: + gen_set_rm(ctx, rm); + gen_helper_fcvt_s_d(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + default: + goto do_illegal; + } + break; + + case OPC_RISC_FCVT_D_S: + switch (rs2) { + case 0: + gen_set_rm(ctx, rm); + gen_helper_fcvt_d_s(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + default: + goto do_illegal; + } + break; + + case OPC_RISC_FEQ_D: + /* also OPC_RISC_FLT_D, OPC_RISC_FLE_D */ + t0 = tcg_temp_new(tcg_ctx); + switch (rm) { + case 0: + gen_helper_fle_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case 1: + gen_helper_flt_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + case 2: + gen_helper_feq_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1], tcg_ctx->riscv_cpu_fpr[rs2]); + break; + default: + goto do_illegal; + } + gen_set_gpr(ctx, rd, t0); + tcg_temp_free(tcg_ctx, t0); + break; + + case OPC_RISC_FCVT_W_D: + /* also OPC_RISC_FCVT_WU_D, OPC_RISC_FCVT_L_D, OPC_RISC_FCVT_LU_D */ + t0 = tcg_temp_new(tcg_ctx); + switch (rs2) { + case 0: + gen_set_rm(ctx, rm); + gen_helper_fcvt_w_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + case 1: + gen_set_rm(ctx, rm); + gen_helper_fcvt_wu_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; +#if defined(TARGET_RISCV64) + case 2: + gen_set_rm(ctx, rm); + gen_helper_fcvt_l_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + case 3: + gen_set_rm(ctx, rm); + gen_helper_fcvt_lu_d(tcg_ctx, t0, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_fpr[rs1]); + break; +#endif + default: + goto do_illegal; + } + gen_set_gpr(ctx, rd, t0); + tcg_temp_free(tcg_ctx, t0); + break; + + case OPC_RISC_FCVT_D_W: + /* also OPC_RISC_FCVT_D_WU, OPC_RISC_FCVT_D_L, OPC_RISC_FCVT_D_LU */ + t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, rs1); + switch (rs2) { + case 0: + gen_set_rm(ctx, rm); + gen_helper_fcvt_d_w(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, t0); + break; + case 1: + gen_set_rm(ctx, rm); + gen_helper_fcvt_d_wu(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, t0); + break; +#if defined(TARGET_RISCV64) + case 2: + gen_set_rm(ctx, rm); + gen_helper_fcvt_d_l(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, t0); + break; + case 3: + gen_set_rm(ctx, rm); + gen_helper_fcvt_d_lu(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], tcg_ctx->cpu_env, t0); + break; +#endif + default: + goto do_illegal; + } + tcg_temp_free(tcg_ctx, t0); + break; + +#if defined(TARGET_RISCV64) + case OPC_RISC_FMV_X_D: + /* also OPC_RISC_FCLASS_D */ + switch (rm) { + case 0: /* FMV */ + gen_set_gpr(ctx, rd, tcg_ctx->riscv_cpu_fpr[rs1]); + break; + case 1: + t0 = tcg_temp_new(tcg_ctx); + gen_helper_fclass_d(tcg_ctx, t0, tcg_ctx->riscv_cpu_fpr[rs1]); + gen_set_gpr(ctx, rd, t0); + tcg_temp_free(tcg_ctx, t0); + break; + default: + goto do_illegal; + } + break; + + case OPC_RISC_FMV_D_X: + t0 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, t0, rs1); + tcg_gen_mov_tl(tcg_ctx, tcg_ctx->riscv_cpu_fpr[rd], t0); + tcg_temp_free(tcg_ctx, t0); + break; +#endif + + default: + do_illegal: + if (t0) { + tcg_temp_free(tcg_ctx, t0); + } + gen_exception_illegal(ctx); + break; + } +} + +static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, + int rd, int rs1, int csr) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + TCGv source1, csr_store, dest, rs1_pass, imm_rs1; + source1 = tcg_temp_new(tcg_ctx); + csr_store = tcg_temp_new(tcg_ctx); + dest = tcg_temp_new(tcg_ctx); + rs1_pass = tcg_temp_new(tcg_ctx); + imm_rs1 = tcg_temp_new(tcg_ctx); + gen_get_gpr(ctx, source1, rs1); + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, ctx->base.pc_next); + tcg_gen_movi_tl(tcg_ctx, rs1_pass, rs1); + tcg_gen_movi_tl(tcg_ctx, csr_store, csr); /* copy into temp reg to feed to helper */ + +#ifndef CONFIG_USER_ONLY + /* Extract funct7 value and check whether it matches SFENCE.VMA */ + if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) { + /* sfence.vma */ + /* TODO: handle ASID specific fences */ + gen_helper_riscv_tlb_flush(tcg_ctx, tcg_ctx->cpu_env); + return; + } +#endif + + switch (opc) { + case OPC_RISC_ECALL: + switch (csr) { + case 0x0: /* ECALL */ + /* always generates U-level ECALL, fixed in do_interrupt handler */ + generate_exception(ctx, RISCV_EXCP_U_ECALL); + tcg_gen_exit_tb(tcg_ctx, NULL, 0); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + break; + case 0x1: /* EBREAK */ + generate_exception(ctx, RISCV_EXCP_BREAKPOINT); + tcg_gen_exit_tb(tcg_ctx, NULL, 0); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + break; +#ifndef CONFIG_USER_ONLY + case 0x002: /* URET */ + gen_exception_illegal(ctx); + break; + case 0x102: /* SRET */ + if (riscv_has_ext(env, RVS)) { + gen_helper_sret(tcg_ctx, tcg_ctx->riscv_cpu_pc, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_pc); + tcg_gen_exit_tb(tcg_ctx, NULL, 0); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + } else { + gen_exception_illegal(ctx); + } + break; + case 0x202: /* HRET */ + gen_exception_illegal(ctx); + break; + case 0x302: /* MRET */ + gen_helper_mret(tcg_ctx, tcg_ctx->riscv_cpu_pc, tcg_ctx->cpu_env, tcg_ctx->riscv_cpu_pc); + tcg_gen_exit_tb(tcg_ctx, NULL, 0); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + break; + case 0x7b2: /* DRET */ + gen_exception_illegal(ctx); + break; + case 0x105: /* WFI */ + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, ctx->pc_succ_insn); + gen_helper_wfi(tcg_ctx, tcg_ctx->cpu_env); + break; + case 0x104: /* SFENCE.VM */ + gen_helper_riscv_tlb_flush(tcg_ctx, tcg_ctx->cpu_env); + break; +#endif + default: + gen_exception_illegal(ctx); + break; + } + break; + default: + tcg_gen_movi_tl(tcg_ctx, imm_rs1, rs1); + // Unicorn commented out + //gen_io_start(); + switch (opc) { + case OPC_RISC_CSRRW: + gen_helper_csrrw(tcg_ctx, dest, tcg_ctx->cpu_env, source1, csr_store); + break; + case OPC_RISC_CSRRS: + gen_helper_csrrs(tcg_ctx, dest, tcg_ctx->cpu_env, source1, csr_store, rs1_pass); + break; + case OPC_RISC_CSRRC: + gen_helper_csrrc(tcg_ctx, dest, tcg_ctx->cpu_env, source1, csr_store, rs1_pass); + break; + case OPC_RISC_CSRRWI: + gen_helper_csrrw(tcg_ctx, dest, tcg_ctx->cpu_env, imm_rs1, csr_store); + break; + case OPC_RISC_CSRRSI: + gen_helper_csrrs(tcg_ctx, dest, tcg_ctx->cpu_env, imm_rs1, csr_store, rs1_pass); + break; + case OPC_RISC_CSRRCI: + gen_helper_csrrc(tcg_ctx, dest, tcg_ctx->cpu_env, imm_rs1, csr_store, rs1_pass); + break; + default: + gen_exception_illegal(ctx); + return; + } + // Unicorn commented out + //gen_io_end(); + gen_set_gpr(ctx, rd, dest); + /* end tb since we may be changing priv modes, to get mmu_index right */ + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, ctx->pc_succ_insn); + tcg_gen_exit_tb(tcg_ctx, NULL, 0); /* no chaining */ + ctx->base.is_jmp = DISAS_NORETURN; + break; + } + tcg_temp_free(tcg_ctx, source1); + tcg_temp_free(tcg_ctx, csr_store); + tcg_temp_free(tcg_ctx, dest); + tcg_temp_free(tcg_ctx, rs1_pass); + tcg_temp_free(tcg_ctx, imm_rs1); +} + +static void decode_RV32_64C0(DisasContext *ctx) +{ + uint8_t funct3 = extract32(ctx->opcode, 13, 3); + uint8_t rd_rs2 = GET_C_RS2S(ctx->opcode); + uint8_t rs1s = GET_C_RS1S(ctx->opcode); + + switch (funct3) { + case 0: + /* illegal */ + if (ctx->opcode == 0) { + gen_exception_illegal(ctx); + } else { + /* C.ADDI4SPN -> addi rd', x2, zimm[9:2]*/ + gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs2, 2, + GET_C_ADDI4SPN_IMM(ctx->opcode)); + } + break; + case 1: + /* C.FLD -> fld rd', offset[7:3](rs1')*/ + gen_fp_load(ctx, OPC_RISC_FLD, rd_rs2, rs1s, + GET_C_LD_IMM(ctx->opcode)); + /* C.LQ(RV128) */ + break; + case 2: + /* C.LW -> lw rd', offset[6:2](rs1') */ + gen_load(ctx, OPC_RISC_LW, rd_rs2, rs1s, + GET_C_LW_IMM(ctx->opcode)); + break; + case 3: +#if defined(TARGET_RISCV64) + /* C.LD(RV64/128) -> ld rd', offset[7:3](rs1')*/ + gen_load(ctx, OPC_RISC_LD, rd_rs2, rs1s, + GET_C_LD_IMM(ctx->opcode)); +#else + /* C.FLW (RV32) -> flw rd', offset[6:2](rs1')*/ + gen_fp_load(ctx, OPC_RISC_FLW, rd_rs2, rs1s, + GET_C_LW_IMM(ctx->opcode)); +#endif + break; + case 4: + /* reserved */ + gen_exception_illegal(ctx); + break; + case 5: + /* C.FSD(RV32/64) -> fsd rs2', offset[7:3](rs1') */ + gen_fp_store(ctx, OPC_RISC_FSD, rs1s, rd_rs2, + GET_C_LD_IMM(ctx->opcode)); + /* C.SQ (RV128) */ + break; + case 6: + /* C.SW -> sw rs2', offset[6:2](rs1')*/ + gen_store(ctx, OPC_RISC_SW, rs1s, rd_rs2, + GET_C_LW_IMM(ctx->opcode)); + break; + case 7: +#if defined(TARGET_RISCV64) + /* C.SD (RV64/128) -> sd rs2', offset[7:3](rs1')*/ + gen_store(ctx, OPC_RISC_SD, rs1s, rd_rs2, + GET_C_LD_IMM(ctx->opcode)); +#else + /* C.FSW (RV32) -> fsw rs2', offset[6:2](rs1')*/ + gen_fp_store(ctx, OPC_RISC_FSW, rs1s, rd_rs2, + GET_C_LW_IMM(ctx->opcode)); +#endif + break; + } +} + +static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + uint8_t funct3 = extract32(ctx->opcode, 13, 3); + uint8_t rd_rs1 = GET_C_RS1(ctx->opcode); + uint8_t rs1s, rs2s; + uint8_t funct2; + + switch (funct3) { + case 0: + /* C.ADDI -> addi rd, rd, nzimm[5:0] */ + gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, rd_rs1, + GET_C_IMM(ctx->opcode)); + break; + case 1: +#if defined(TARGET_RISCV64) + /* C.ADDIW (RV64/128) -> addiw rd, rd, imm[5:0]*/ + gen_arith_imm(ctx, OPC_RISC_ADDIW, rd_rs1, rd_rs1, + GET_C_IMM(ctx->opcode)); +#else + /* C.JAL(RV32) -> jal x1, offset[11:1] */ + gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode)); +#endif + break; + case 2: + /* C.LI -> addi rd, x0, imm[5:0]*/ + gen_arith_imm(ctx, OPC_RISC_ADDI, rd_rs1, 0, GET_C_IMM(ctx->opcode)); + break; + case 3: + if (rd_rs1 == 2) { + /* C.ADDI16SP -> addi x2, x2, nzimm[9:4]*/ + gen_arith_imm(ctx, OPC_RISC_ADDI, 2, 2, + GET_C_ADDI16SP_IMM(ctx->opcode)); + } else if (rd_rs1 != 0) { + /* C.LUI (rs1/rd =/= {0,2}) -> lui rd, nzimm[17:12]*/ + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_gpr[rd_rs1], + GET_C_IMM(ctx->opcode) << 12); + } + break; + case 4: + funct2 = extract32(ctx->opcode, 10, 2); + rs1s = GET_C_RS1S(ctx->opcode); + switch (funct2) { + case 0: /* C.SRLI(RV32) -> srli rd', rd', shamt[5:0] */ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s, + GET_C_ZIMM(ctx->opcode)); + /* C.SRLI64(RV128) */ + break; + case 1: + /* C.SRAI -> srai rd', rd', shamt[5:0]*/ + gen_arith_imm(ctx, OPC_RISC_SHIFT_RIGHT_I, rs1s, rs1s, + GET_C_ZIMM(ctx->opcode) | 0x400); + /* C.SRAI64(RV128) */ + break; + case 2: + /* C.ANDI -> andi rd', rd', imm[5:0]*/ + gen_arith_imm(ctx, OPC_RISC_ANDI, rs1s, rs1s, + GET_C_IMM(ctx->opcode)); + break; + case 3: + funct2 = extract32(ctx->opcode, 5, 2); + rs2s = GET_C_RS2S(ctx->opcode); + switch (funct2) { + case 0: + /* C.SUB -> sub rd', rd', rs2' */ + if (extract32(ctx->opcode, 12, 1) == 0) { + gen_arith(ctx, OPC_RISC_SUB, rs1s, rs1s, rs2s); + } +#if defined(TARGET_RISCV64) + else { + gen_arith(ctx, OPC_RISC_SUBW, rs1s, rs1s, rs2s); + } +#endif + break; + case 1: + /* C.XOR -> xor rs1', rs1', rs2' */ + if (extract32(ctx->opcode, 12, 1) == 0) { + gen_arith(ctx, OPC_RISC_XOR, rs1s, rs1s, rs2s); + } +#if defined(TARGET_RISCV64) + else { + /* C.ADDW (RV64/128) */ + gen_arith(ctx, OPC_RISC_ADDW, rs1s, rs1s, rs2s); + } +#endif + break; + case 2: + /* C.OR -> or rs1', rs1', rs2' */ + gen_arith(ctx, OPC_RISC_OR, rs1s, rs1s, rs2s); + break; + case 3: + /* C.AND -> and rs1', rs1', rs2' */ + gen_arith(ctx, OPC_RISC_AND, rs1s, rs1s, rs2s); + break; + } + break; + } + break; + case 5: + /* C.J -> jal x0, offset[11:1]*/ + gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode)); + break; + case 6: + /* C.BEQZ -> beq rs1', x0, offset[8:1]*/ + rs1s = GET_C_RS1S(ctx->opcode); + gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode)); + break; + case 7: + /* C.BNEZ -> bne rs1', x0, offset[8:1]*/ + rs1s = GET_C_RS1S(ctx->opcode); + gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode)); + break; + } +} + +static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx) +{ + uint8_t rd, rs2; + uint8_t funct3 = extract32(ctx->opcode, 13, 3); + + + rd = GET_RD(ctx->opcode); + + switch (funct3) { + case 0: /* C.SLLI -> slli rd, rd, shamt[5:0] + C.SLLI64 -> */ + gen_arith_imm(ctx, OPC_RISC_SLLI, rd, rd, GET_C_ZIMM(ctx->opcode)); + break; + case 1: /* C.FLDSP(RV32/64DC) -> fld rd, offset[8:3](x2) */ + gen_fp_load(ctx, OPC_RISC_FLD, rd, 2, GET_C_LDSP_IMM(ctx->opcode)); + break; + case 2: /* C.LWSP -> lw rd, offset[7:2](x2) */ + gen_load(ctx, OPC_RISC_LW, rd, 2, GET_C_LWSP_IMM(ctx->opcode)); + break; + case 3: +#if defined(TARGET_RISCV64) + /* C.LDSP(RVC64) -> ld rd, offset[8:3](x2) */ + gen_load(ctx, OPC_RISC_LD, rd, 2, GET_C_LDSP_IMM(ctx->opcode)); +#else + /* C.FLWSP(RV32FC) -> flw rd, offset[7:2](x2) */ + gen_fp_load(ctx, OPC_RISC_FLW, rd, 2, GET_C_LWSP_IMM(ctx->opcode)); +#endif + break; + case 4: + rs2 = GET_C_RS2(ctx->opcode); + + if (extract32(ctx->opcode, 12, 1) == 0) { + if (rs2 == 0) { + /* C.JR -> jalr x0, rs1, 0*/ + gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0); + } else { + /* C.MV -> add rd, x0, rs2 */ + gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2); + } + } else { + if (rd == 0) { + /* C.EBREAK -> ebreak*/ + gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1); + } else { + if (rs2 == 0) { + /* C.JALR -> jalr x1, rs1, 0*/ + gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0); + } else { + /* C.ADD -> add rd, rd, rs2 */ + gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2); + } + } + } + break; + case 5: + /* C.FSDSP -> fsd rs2, offset[8:3](x2)*/ + gen_fp_store(ctx, OPC_RISC_FSD, 2, GET_C_RS2(ctx->opcode), + GET_C_SDSP_IMM(ctx->opcode)); + /* C.SQSP */ + break; + case 6: /* C.SWSP -> sw rs2, offset[7:2](x2)*/ + gen_store(ctx, OPC_RISC_SW, 2, GET_C_RS2(ctx->opcode), + GET_C_SWSP_IMM(ctx->opcode)); + break; + case 7: +#if defined(TARGET_RISCV64) + /* C.SDSP(Rv64/128) -> sd rs2, offset[8:3](x2)*/ + gen_store(ctx, OPC_RISC_SD, 2, GET_C_RS2(ctx->opcode), + GET_C_SDSP_IMM(ctx->opcode)); +#else + /* C.FSWSP(RV32) -> fsw rs2, offset[7:2](x2) */ + gen_fp_store(ctx, OPC_RISC_FSW, 2, GET_C_RS2(ctx->opcode), + GET_C_SWSP_IMM(ctx->opcode)); +#endif + break; + } +} + +static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx) +{ + uint8_t op = extract32(ctx->opcode, 0, 2); + + switch (op) { + case 0: + decode_RV32_64C0(ctx); + break; + case 1: + decode_RV32_64C1(env, ctx); + break; + case 2: + decode_RV32_64C2(env, ctx); + break; + } +} + +static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) +{ + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + int rs1; + int rs2; + int rd; + uint32_t op; + target_long imm; + + /* We do not do misaligned address check here: the address should never be + * misaligned at this point. Instructions that set PC must do the check, + * since epc must be the address of the instruction that caused us to + * perform the misaligned instruction fetch */ + + op = MASK_OP_MAJOR(ctx->opcode); + rs1 = GET_RS1(ctx->opcode); + rs2 = GET_RS2(ctx->opcode); + rd = GET_RD(ctx->opcode); + imm = GET_IMM(ctx->opcode); + + switch (op) { + case OPC_RISC_LUI: + if (rd == 0) { + break; /* NOP */ + } + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_gpr[rd], sextract64(ctx->opcode, 12, 20) << 12); + break; + case OPC_RISC_AUIPC: + if (rd == 0) { + break; /* NOP */ + } + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_gpr[rd], (sextract64(ctx->opcode, 12, 20) << 12) + + ctx->base.pc_next); + break; + case OPC_RISC_JAL: + imm = GET_JAL_IMM(ctx->opcode); + gen_jal(env, ctx, rd, imm); + break; + case OPC_RISC_JALR: + gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm); + break; + case OPC_RISC_BRANCH: + gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2, + GET_B_IMM(ctx->opcode)); + break; + case OPC_RISC_LOAD: + gen_load(ctx, MASK_OP_LOAD(ctx->opcode), rd, rs1, imm); + break; + case OPC_RISC_STORE: + gen_store(ctx, MASK_OP_STORE(ctx->opcode), rs1, rs2, + GET_STORE_IMM(ctx->opcode)); + break; + case OPC_RISC_ARITH_IMM: +#if defined(TARGET_RISCV64) + case OPC_RISC_ARITH_IMM_W: +#endif + if (rd == 0) { + break; /* NOP */ + } + gen_arith_imm(ctx, MASK_OP_ARITH_IMM(ctx->opcode), rd, rs1, imm); + break; + case OPC_RISC_ARITH: +#if defined(TARGET_RISCV64) + case OPC_RISC_ARITH_W: +#endif + if (rd == 0) { + break; /* NOP */ + } + gen_arith(ctx, MASK_OP_ARITH(ctx->opcode), rd, rs1, rs2); + break; + case OPC_RISC_FP_LOAD: + gen_fp_load(ctx, MASK_OP_FP_LOAD(ctx->opcode), rd, rs1, imm); + break; + case OPC_RISC_FP_STORE: + gen_fp_store(ctx, MASK_OP_FP_STORE(ctx->opcode), rs1, rs2, + GET_STORE_IMM(ctx->opcode)); + break; + case OPC_RISC_ATOMIC: + gen_atomic(ctx, MASK_OP_ATOMIC(ctx->opcode), rd, rs1, rs2); + break; + case OPC_RISC_FMADD: + gen_fp_fmadd(ctx, MASK_OP_FP_FMADD(ctx->opcode), rd, rs1, rs2, + GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); + break; + case OPC_RISC_FMSUB: + gen_fp_fmsub(ctx, MASK_OP_FP_FMSUB(ctx->opcode), rd, rs1, rs2, + GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); + break; + case OPC_RISC_FNMSUB: + gen_fp_fnmsub(ctx, MASK_OP_FP_FNMSUB(ctx->opcode), rd, rs1, rs2, + GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); + break; + case OPC_RISC_FNMADD: + gen_fp_fnmadd(ctx, MASK_OP_FP_FNMADD(ctx->opcode), rd, rs1, rs2, + GET_RS3(ctx->opcode), GET_RM(ctx->opcode)); + break; + case OPC_RISC_FP_ARITH: + gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2, + GET_RM(ctx->opcode)); + break; + case OPC_RISC_FENCE: +#ifndef CONFIG_USER_ONLY + if (ctx->opcode & 0x1000) { + /* FENCE_I is a no-op in QEMU, + * however we need to end the translation block */ + tcg_gen_movi_tl(tcg_ctx, tcg_ctx->riscv_cpu_pc, ctx->pc_succ_insn); + tcg_gen_exit_tb(tcg_ctx, NULL, 0); + ctx->base.is_jmp = DISAS_NORETURN; + } else { + /* FENCE is a full memory barrier. */ + tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_SC); + } +#endif + break; + case OPC_RISC_SYSTEM: + gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, + (ctx->opcode & 0xFFF00000) >> 20); + break; + default: + gen_exception_illegal(ctx); + break; + } +} + +static void decode_opc(CPURISCVState *env, DisasContext *ctx) +{ + /* check for compressed insn */ + if (extract32(ctx->opcode, 0, 2) != 3) { + if (!riscv_has_ext(env, RVC)) { + gen_exception_illegal(ctx); + } else { + ctx->pc_succ_insn = ctx->base.pc_next + 2; + decode_RV32_64C(env, ctx); + } + } else { + ctx->pc_succ_insn = ctx->base.pc_next + 4; + decode_RV32_64G(env, ctx); + } +} + +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + ctx->pc_succ_insn = ctx->base.pc_first; + ctx->flags = ctx->base.tb->flags; + ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK; + ctx->frm = -1; /* unknown rounding mode */ + + // Unicorn: Store uc context + ctx->uc = cs->uc; +} + +static void riscv_tr_tb_start(DisasContextBase *db, CPUState *cpu) +{ +} + +static void riscv_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + tcg_gen_insn_start(tcg_ctx, ctx->base.pc_next); +} + +static bool riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu, + const CPUBreakpoint *bp) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + TCGContext *tcg_ctx = ctx->uc->tcg_ctx; + + tcg_gen_movi_tl(ctx->uc->tcg_ctx, tcg_ctx->riscv_cpu_pc, ctx->base.pc_next); + ctx->base.is_jmp = DISAS_NORETURN; + gen_exception_debug(ctx); + /* The address covered by the breakpoint must be included in + [tb->pc, tb->pc + tb->size) in order to for it to be + properly cleared -- thus we increment the PC here so that + the logic setting tb->size below does the right thing. */ + ctx->base.pc_next += 4; + return true; +} + + +static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + CPURISCVState *env = cpu->env_ptr; + + ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next); + decode_opc(env, ctx); + ctx->base.pc_next = ctx->pc_succ_insn; + + if (ctx->base.is_jmp == DISAS_NEXT) { + target_ulong page_start; + + page_start = ctx->base.pc_first & TARGET_PAGE_MASK; + if (ctx->base.pc_next - page_start >= TARGET_PAGE_SIZE) { + ctx->base.is_jmp = DISAS_TOO_MANY; + } + } +} + +static void riscv_tr_tb_stop(DisasContextBase *dcbase, CPUState *cpu) +{ + DisasContext *ctx = container_of(dcbase, DisasContext, base); + + switch (ctx->base.is_jmp) { + case DISAS_TOO_MANY: + gen_goto_tb(ctx, 0, ctx->base.pc_next); + break; + case DISAS_NORETURN: + break; + default: + g_assert_not_reached(); + } +} + +static void riscv_tr_disas_log(const DisasContextBase *dcbase, CPUState *cpu) +{ + // Unicorn: Commented out + //qemu_log("IN: %s\n", lookup_symbol(dcbase->pc_first)); + //log_target_disas(cpu, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps riscv_tr_ops = { + .init_disas_context = riscv_tr_init_disas_context, + .tb_start = riscv_tr_tb_start, + .insn_start = riscv_tr_insn_start, + .breakpoint_check = riscv_tr_breakpoint_check, + .translate_insn = riscv_tr_translate_insn, + .tb_stop = riscv_tr_tb_stop, + .disas_log = riscv_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb) +{ + DisasContext ctx; + + translator_loop(&riscv_tr_ops, &ctx.base, cs, tb); +} + +void riscv_translate_init(struct uc_struct *uc) +{ + TCGContext *tcg_ctx = uc->tcg_ctx; + + tcg_ctx->cpu_env = tcg_global_reg_new_ptr(uc->tcg_ctx, TCG_AREG0, "env"); + tcg_ctx->tcg_env = tcg_ctx->cpu_env; + + /* cpu_gpr[0] is a placeholder for the zero register. Do not use it. */ + /* Use the gen_set_gpr and gen_get_gpr helper functions when accessing */ + /* registers, unless you specifically block reads/writes to reg 0 */ + tcg_ctx->riscv_cpu_gpr[0] = NULL; + + for (int i = 1; i < 32; i++) { + tcg_ctx->riscv_cpu_gpr[i] = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, + offsetof(CPURISCVState, gpr[i]), riscv_int_regnames[i]); + } + + for (int i = 0; i < 32; i++) { + tcg_ctx->riscv_cpu_fpr[i] = tcg_global_mem_new_i64(tcg_ctx, tcg_ctx->cpu_env, + offsetof(CPURISCVState, fpr[i]), riscv_fpr_regnames[i]); + } + + tcg_ctx->riscv_cpu_pc = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, pc), "pc"); + tcg_ctx->load_res = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, load_res), + "load_res"); + tcg_ctx->load_val = tcg_global_mem_new(tcg_ctx, tcg_ctx->cpu_env, offsetof(CPURISCVState, load_val), + "load_val"); +} diff --git a/qemu/target/riscv/unicorn.c b/qemu/target/riscv/unicorn.c new file mode 100644 index 00000000..c7cc3f3b --- /dev/null +++ b/qemu/target/riscv/unicorn.c @@ -0,0 +1,114 @@ +/* Unicorn Emulator Engine */ +/* By Nguyen Anh Quynh , 2015 */ + +#include + +#include "qemu/osdep.h" +#include "cpu.h" +#include "hw/boards.h" +#include "hw/riscv/spike.h" +#include "sysemu/cpus.h" +#include "unicorn.h" +#include "unicorn_common.h" +#include "uc_priv.h" + +#ifdef TARGET_RISCV32 +const int RISCV32_REGS_STORAGE_SIZE = offsetof(CPURISCVState, tlb_table); +#else +const int RISCV64_REGS_STORAGE_SIZE = offsetof(CPURISCVState, tlb_table); +#endif + +static void riscv_release(void *ctx) { + TCGContext *tcg_ctx = (TCGContext *) ctx; + + release_common(ctx); + g_free(tcg_ctx->tb_ctx.tbs); +} + +static void riscv_reg_reset(struct uc_struct *uc) { + CPUArchState *env = uc->cpu->env_ptr; + + memset(env->gpr, 0, sizeof(env->gpr)); + memset(env->fpr, 0, sizeof(env->fpr)); + + env->priv = PRV_M; + env->mstatus &= ~(MSTATUS_MIE | MSTATUS_MPRV); + env->mcause = 0; + env->pc = env->resetvec; + + set_default_nan_mode(1, &env->fp_status); +} + +static int riscv_reg_read(struct uc_struct *uc, unsigned int *regs, void **vals, int count) { + CPUState *const cs = uc->cpu; + CPURISCVState *const state = &RISCV_CPU(cs)->env; + + for (int i = 0; i < count; i++) { + const unsigned int reg_id = regs[i]; + void *const value = vals[i]; + + if (reg_id >= UC_RISCV_REG_X0 && reg_id <= UC_RISCV_REG_X31) { + memcpy(value, &state->gpr[i - UC_RISCV_REG_X0], sizeof(state->gpr[0])); + } else if (reg_id >= UC_RISCV_REG_F0 && reg_id <= UC_RISCV_REG_F31) { + memcpy(value, &state->gpr[i - UC_RISCV_REG_F0], sizeof(state->fpr[0])); + } else if (reg_id == UC_RISCV_REG_PC) { + memcpy(value, &state->pc, sizeof(state->pc)); + } + } + + return 0; +} + +static int riscv_reg_write(struct uc_struct *uc, unsigned int *regs, void *const *vals, int count) { + CPUState *const cs = uc->cpu; + CPURISCVState *const state = &RISCV_CPU(cs)->env; + + for (int i = 0; i < count; i++) { + const unsigned int reg_id = regs[i]; + const void *value = vals[i]; + + // Intentionally exclude the zero register (X0) in the lower-bound + if (reg_id > UC_RISCV_REG_X0 && reg_id <= UC_RISCV_REG_X31) { + memcpy(&state->gpr[i - UC_RISCV_REG_X0], value, sizeof(state->gpr[0])); + } else if (reg_id >= UC_RISCV_REG_F0 && reg_id <= UC_RISCV_REG_F31) { + memcpy(&state->gpr[i - UC_RISCV_REG_F0], value, sizeof(state->fpr[0])); + } else if (reg_id == UC_RISCV_REG_PC) { + memcpy(&state->pc, value, sizeof(state->pc)); + } + } + + return 0; +} + +static void riscv_set_pc(struct uc_struct *uc, uint64_t address) { + CPURISCVState *state = uc->cpu->env_ptr; + + state->pc = address; +} + +static bool riscv_stop_interrupt(int int_no) { + switch(int_no) { + default: + return false; + } +} + +DEFAULT_VISIBILITY +#ifdef TARGET_RISCV32 +void riscv32_uc_init(struct uc_struct *uc) { +#else +void riscv64_uc_init(struct uc_struct *uc) { +#endif + register_accel_types(uc); + riscv_cpu_register_types(uc); + spike_v1_10_0_machine_init_register_types(uc); + + uc->release = riscv_release; + uc->reg_read = riscv_reg_read; + uc->reg_write = riscv_reg_write; + uc->reg_reset = riscv_reg_reset; + uc->set_pc = riscv_set_pc; + uc->stop_interrupt = riscv_stop_interrupt; + + uc_common_init(uc); +} diff --git a/qemu/target/riscv/unicorn.h b/qemu/target/riscv/unicorn.h new file mode 100644 index 00000000..c5f74602 --- /dev/null +++ b/qemu/target/riscv/unicorn.h @@ -0,0 +1,13 @@ +/* Unicorn Emulator Engine */ +/* By Nguyen Anh Quynh , 2018 */ + +#ifndef UC_QEMU_TARGET_RISCV_H +#define UC_QEMU_TARGET_RISCV_H + +void riscv32_uc_init(struct uc_struct *uc); +void riscv64_uc_init(struct uc_struct *uc); + +extern const int RISCV32_REGS_STORAGE_SIZE_riscv32; +extern const int RISCV64_REGS_STORAGE_SIZE_riscv64; + +#endif /* UC_QEMU_TARGET_RISCV_H */ diff --git a/qemu/tcg/tcg.h b/qemu/tcg/tcg.h index 33fec428..07b5a460 100644 --- a/qemu/tcg/tcg.h +++ b/qemu/tcg/tcg.h @@ -844,7 +844,7 @@ struct TCGContext { struct tcg_temp_info temps2[TCG_MAX_TEMPS]; TCGTempSet temps2_used; - /* qemu/target-m68k/translate.c */ + /* qemu/target/m68k/translate.c */ TCGv_i32 cpu_halted; char cpu_reg_names[2 * 8 * 3 + 5 * 4]; TCGv cpu_dregs[8]; @@ -865,20 +865,20 @@ struct TCGContext { /* Used to distinguish stores from bad addressing modes. */ TCGv store_dummy; - /* qemu/target-arm/translate.c */ + /* qemu/target/arm/translate.c */ /* We reuse the same 64-bit temporaries for efficiency. */ TCGv_i32 cpu_R[16]; TCGv_i32 cpu_CF, cpu_NF, cpu_VF, cpu_ZF; TCGv_i64 cpu_exclusive_addr; TCGv_i64 cpu_exclusive_val; - /* qemu/target-arm/translate-a64.c */ + /* qemu/target/arm/translate-a64.c */ TCGv_i64 cpu_pc; /* Load/store exclusive handling */ TCGv_i64 cpu_exclusive_high; TCGv_i64 cpu_X[32]; - /* qemu/target-mips/translate.c */ + /* qemu/target/mips/translate.c */ /* global register indices */ TCGv cpu_gpr[32]; TCGv cpu_PC; @@ -891,7 +891,14 @@ struct TCGContext { TCGv_i64 fpu_f64[32]; TCGv_i64 msa_wr_d[64]; - /* qemu/target-sparc/translate.c */ + /* qemu/target/riscv/translate.c */ + TCGv riscv_cpu_gpr[32]; + TCGv riscv_cpu_pc; + TCGv_i64 riscv_cpu_fpr[32]; /* assume F and D extensions */ + TCGv load_res; + TCGv load_val; + + /* qemu/target/sparc/translate.c */ /* global register indexes */ TCGv_ptr cpu_regwptr; TCGv_i32 cpu_psr; diff --git a/qemu/x86_64.h b/qemu/x86_64.h index 7063a576..1dada9d6 100644 --- a/qemu/x86_64.h +++ b/qemu/x86_64.h @@ -217,7 +217,6 @@ #define clz32 clz32_x86_64 #define clz64 clz64_x86_64 #define cmp_flatrange_addr cmp_flatrange_addr_x86_64 -#define code_gen_alloc code_gen_alloc_x86_64 #define commonNaNToFloat128 commonNaNToFloat128_x86_64 #define commonNaNToFloat16 commonNaNToFloat16_x86_64 #define commonNaNToFloat32 commonNaNToFloat32_x86_64 @@ -281,7 +280,6 @@ #define cpu_exec_init_all cpu_exec_init_all_x86_64 #define cpu_exec_step_atomic cpu_exec_step_atomic_x86_64 #define cpu_flush_icache_range cpu_flush_icache_range_x86_64 -#define cpu_gen_init cpu_gen_init_x86_64 #define cpu_get_address_space cpu_get_address_space_x86_64 #define cpu_get_clock cpu_get_clock_x86_64 #define cpu_get_real_ticks cpu_get_real_ticks_x86_64 diff --git a/samples/Makefile b/samples/Makefile index 5b4b28de..22a3b213 100644 --- a/samples/Makefile +++ b/samples/Makefile @@ -76,6 +76,9 @@ endif #ifneq (,$(findstring ppc,$(UNICORN_ARCHS))) #SOURCES += sample_ppc.c #endif +ifneq (,$(findstring riscv,$(UNICORN_ARCHS))) +SOURCES += sample_riscv.c +endif ifneq (,$(findstring sparc,$(UNICORN_ARCHS))) SOURCES += sample_sparc.c endif diff --git a/samples/sample_riscv.c b/samples/sample_riscv.c new file mode 100644 index 00000000..ad5b2f2c --- /dev/null +++ b/samples/sample_riscv.c @@ -0,0 +1,146 @@ +/* Unicorn Emulator Engine */ +/* By Nguyen Anh Quynh, 2015 */ + +/* Sample code to demonstrate how to emulate Mips code (big endian) */ + +#include +#include + +// code to be emulated +#define RISCV_CODE "\x93\xE0\xF0\x7F" // ori $x1, $x1, 0xFF; + +// memory address where emulation starts +#define START_ADDRESS 0x10000 + +static void hook_block(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) +{ + printf(">>> Tracing basic block at 0x%" PRIx64 ", block size = 0x%x\n", address, size); +} + +static void hook_code(uc_engine *uc, uint64_t address, uint32_t size, void *user_data) +{ + printf(">>> Tracing instruction at 0x%" PRIx64 ", instruction size = 0x%x\n", address, size); +} + +static void test_riscv32(void) +{ + uc_engine *uc; + uc_err err; + uc_hook trace1, trace2; + + int x1 = 0x6789; // X1 register + + printf("Emulate 32-bit RISC-V code\n"); + + // Initialize emulator in RISC-V 32-bit mode + err = uc_open(UC_ARCH_RISCV, UC_MODE_RISCV32, &uc); + if (err) { + printf("Failed on uc_open() with error returned: %u (%s)\n", + err, uc_strerror(err)); + return; + } + + // map 2MB memory for this emulation + uc_mem_map(uc, START_ADDRESS, 2 * 1024 * 1024, UC_PROT_ALL); + + // write machine code to be emulated to memory + uc_mem_write(uc, START_ADDRESS, RISCV_CODE, sizeof(RISCV_CODE) - 1); + + // initialize machine registers + uc_reg_write(uc, UC_RISCV_REG_X1, &x1); + + // tracing all basic blocks with customized callback + uc_hook_add(uc, &trace1, UC_HOOK_BLOCK, hook_block, NULL, 1, 0); + + // tracing one instruction at START_ADDRESS with customized callback + uc_hook_add(uc, &trace2, UC_HOOK_CODE, hook_code, NULL, START_ADDRESS, START_ADDRESS); + + // emulate machine code in infinite time (last param = 0), or when + // finishing all the code. + err = uc_emu_start(uc, START_ADDRESS, START_ADDRESS + sizeof(RISCV_CODE) - 1, 0, 0); + if (err) { + printf("Failed on uc_emu_start() with error returned: %u (%s)\n", err, uc_strerror(err)); + } + + // now print out some registers + printf(">>> Emulation done. Below is the CPU context\n"); + + uc_reg_read(uc, UC_RISCV_REG_X1, &x1); + printf(">>> X1 = 0x%08X\n", x1); + + uc_close(uc); +} + +static void test_riscv64(void) +{ + uc_engine *uc; + uc_err err; + uc_hook trace1, trace2; + + int x1 = 0x6789; // X1 register + + printf("===========================\n"); + printf("Emulate 64-bit RISC-V code\n"); + + // Initialize emulator in RISC-V 64-bit mode + err = uc_open(UC_ARCH_RISCV, UC_MODE_RISCV64, &uc); + if (err) { + printf("Failed on uc_open() with error returned: %u (%s)\n", + err, uc_strerror(err)); + return; + } + + // map 2MB memory for this emulation + uc_mem_map(uc, START_ADDRESS, 2 * 1024 * 1024, UC_PROT_ALL); + + // write machine code to be emulated to memory + uc_mem_write(uc, START_ADDRESS, RISCV_CODE, sizeof(RISCV_CODE) - 1); + + // initialize machine registers + uc_reg_write(uc, UC_RISCV_REG_X1, &x1); + + // tracing all basic blocks with customized callback + uc_hook_add(uc, &trace1, UC_HOOK_BLOCK, hook_block, NULL, 1, 0); + + // tracing one instruction at START_ADDRESS with customized callback + uc_hook_add(uc, &trace2, UC_HOOK_CODE, hook_code, NULL, START_ADDRESS, START_ADDRESS); + + // emulate machine code in infinite time (last param = 0), or when + // finishing all the code. + err = uc_emu_start(uc, START_ADDRESS, START_ADDRESS + sizeof(RISCV_CODE) - 1, 0, 0); + if (err) { + printf("Failed on uc_emu_start() with error returned: %u (%s)\n", err, uc_strerror(err)); + } + + // now print out some registers + printf(">>> Emulation done. Below is the CPU context\n"); + + uc_reg_read(uc, UC_RISCV_REG_X1, &x1); + printf(">>> X1 = 0x%08X\n", x1); + + uc_close(uc); +} + +int main(int argc, char **argv, char **envp) +{ + // dynamically load shared library +#ifdef DYNLOAD + if (!uc_dyn_load(NULL, 0)) { + printf("Error dynamically loading shared library.\n"); + printf("Please check that unicorn.dll/unicorn.so is available as well as\n"); + printf("any other dependent dll/so files.\n"); + printf("The easiest way is to place them in the same directory as this app.\n"); + return 1; + } +#endif + + test_riscv32(); + test_riscv64(); + + // dynamically free shared library +#ifdef DYNLOAD + uc_dyn_free(); +#endif + + return 0; +} diff --git a/uc.c b/uc.c index cdbe4250..8b4499f9 100644 --- a/uc.c +++ b/uc.c @@ -20,6 +20,7 @@ #include "qemu/target/i386/unicorn.h" #include "qemu/target/m68k/unicorn.h" #include "qemu/target/mips/unicorn.h" +#include "qemu/target/riscv/unicorn.h" #include "qemu/target/sparc/unicorn.h" #include "qemu/include/hw/boards.h" @@ -125,6 +126,9 @@ bool uc_arch_supported(uc_arch arch) #ifdef UNICORN_HAS_PPC case UC_ARCH_PPC: return true; #endif +#ifdef UNICORN_HAS_RISCV + case UC_ARCH_RISCV: return true; +#endif #ifdef UNICORN_HAS_SPARC case UC_ARCH_SPARC: return true; #endif @@ -247,6 +251,24 @@ uc_err uc_open(uc_arch arch, uc_mode mode, uc_engine **result) break; #endif +#ifdef UNICORN_HAS_RISCV + case UC_ARCH_RISCV: + if (mode & ~UC_MODE_RISCV_MASK) { + free(uc); + return UC_ERR_MODE; + } + if (mode & UC_MODE_RISCV64) { +#ifdef UNICORN_HAS_RISCV64 + uc->init_arch = riscv64_uc_init; +#endif + } else { +#ifdef UNICORN_HAS_RISCV32 + uc->init_arch = riscv32_uc_init; +#endif + } + break; +#endif /* UNICORN_HAS_RISCV */ + #ifdef UNICORN_HAS_SPARC case UC_ARCH_SPARC: if ((mode & ~UC_MODE_SPARC_MASK) || @@ -585,6 +607,11 @@ uc_err uc_emu_start(uc_engine* uc, uint64_t begin, uint64_t until, uint64_t time uc_reg_write(uc, UC_MIPS_REG_PC, &begin); break; #endif +#ifdef UNICORN_HAS_RISCV + case UC_ARCH_RISCV: + uc_reg_write(uc, UC_RISCV_REG_PC, &begin); + break; +#endif #ifdef UNICORN_HAS_SPARC case UC_ARCH_SPARC: // TODO: Sparc/Sparc64 @@ -1211,16 +1238,20 @@ static size_t cpu_context_size(uc_arch arch, uc_mode mode) // of the interesting CPU registers switch (arch) { #ifdef UNICORN_HAS_M68K - case UC_ARCH_M68K: return M68K_REGS_STORAGE_SIZE; + case UC_ARCH_M68K: + return M68K_REGS_STORAGE_SIZE; #endif #ifdef UNICORN_HAS_X86 - case UC_ARCH_X86: return X86_REGS_STORAGE_SIZE; + case UC_ARCH_X86: + return X86_REGS_STORAGE_SIZE; #endif #ifdef UNICORN_HAS_ARM - case UC_ARCH_ARM: return mode & UC_MODE_BIG_ENDIAN ? ARM_REGS_STORAGE_SIZE_armeb : ARM_REGS_STORAGE_SIZE_arm; + case UC_ARCH_ARM: + return mode & UC_MODE_BIG_ENDIAN ? ARM_REGS_STORAGE_SIZE_armeb : ARM_REGS_STORAGE_SIZE_arm; #endif #ifdef UNICORN_HAS_ARM64 - case UC_ARCH_ARM64: return mode & UC_MODE_BIG_ENDIAN ? ARM64_REGS_STORAGE_SIZE_aarch64eb : ARM64_REGS_STORAGE_SIZE_aarch64; + case UC_ARCH_ARM64: + return mode & UC_MODE_BIG_ENDIAN ? ARM64_REGS_STORAGE_SIZE_aarch64eb : ARM64_REGS_STORAGE_SIZE_aarch64; #endif #ifdef UNICORN_HAS_MIPS case UC_ARCH_MIPS: @@ -1238,10 +1269,19 @@ static size_t cpu_context_size(uc_arch arch, uc_mode mode) } } #endif -#ifdef UNICORN_HAS_SPARC - case UC_ARCH_SPARC: return mode & UC_MODE_SPARC64 ? SPARC64_REGS_STORAGE_SIZE : SPARC_REGS_STORAGE_SIZE; +#ifdef UNICORN_HAS_RISCV + case UC_ARCH_RISCV: + if (mode & UC_MODE_RISCV64) { + return RISCV64_REGS_STORAGE_SIZE_riscv64; + } + return RISCV32_REGS_STORAGE_SIZE_riscv32; #endif - default: return 0; +#ifdef UNICORN_HAS_SPARC + case UC_ARCH_SPARC: + return mode & UC_MODE_SPARC64 ? SPARC64_REGS_STORAGE_SIZE : SPARC_REGS_STORAGE_SIZE; +#endif + default: + return 0; } }