From 955661ad7be8dbbb443f61ea90c8ec085bd12ab3 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Thu, 8 Aug 2019 19:23:01 -0400 Subject: [PATCH] tcg: Fix expansion of INDEX_op_not_vec This operation can always be emitted, even if we need to fall back to xor. Adjust the assertions to match. Backports commit 11978f6f58f1d3d66429f7ff897524f693d823ce from qemu --- qemu/tcg/tcg-op-vec.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/qemu/tcg/tcg-op-vec.c b/qemu/tcg/tcg-op-vec.c index 8613f525..7d56e13c 100644 --- a/qemu/tcg/tcg-op-vec.c +++ b/qemu/tcg/tcg-op-vec.c @@ -92,6 +92,9 @@ bool tcg_can_emit_vecop_list(const TCGOpcode *list, case INDEX_op_bitsel_vec: /* These opcodes are mandatory and should not be listed. */ g_assert_not_reached(); + case INDEX_op_not_vec: + /* These opcodes have generic expansions using the above. */ + g_assert_not_reached(); default: break; } @@ -440,11 +443,14 @@ static bool do_op2(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, TCGOpco void tcg_gen_not_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a) { + const TCGOpcode *hold_list = tcg_swap_vecop_list(s, NULL); + if (!TCG_TARGET_HAS_not_vec || !do_op2(s, vece, r, a, INDEX_op_not_vec)) { TCGv_vec t = tcg_const_ones_vec_matching(s, r); tcg_gen_xor_vec(s, 0, r, a, t); tcg_temp_free_vec(s, t); } + tcg_swap_vecop_list(s, hold_list); } void tcg_gen_neg_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a)