From 95a6d78121b965492e9bed7d705bde3aadd365a0 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Sun, 7 Mar 2021 11:37:21 -0500 Subject: [PATCH] target/riscv: vector widening floating-point fused multiply-add instructions Backports 0dd509594fbd53fc9c3edc79bd7a575f079c3c87 --- qemu/header_gen.py | 16 ++++ qemu/riscv32.h | 16 ++++ qemu/riscv64.h | 16 ++++ qemu/target/riscv/helper.h | 17 ++++ qemu/target/riscv/insn32.decode | 8 ++ qemu/target/riscv/insn_trans/trans_rvv.inc.c | 10 +++ qemu/target/riscv/vector_helper.c | 91 ++++++++++++++++++++ 7 files changed, 174 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 117d844d..c18991fd 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -7075,6 +7075,22 @@ riscv_symbols = ( 'helper_vfnmsub_vf_h', 'helper_vfnmsub_vf_w', 'helper_vfnmsub_vf_d', + 'helper_vfwmacc_vv_h', + 'helper_vfwmacc_vv_w', + 'helper_vfwnmacc_vv_h', + 'helper_vfwnmacc_vv_w', + 'helper_vfwmsac_vv_h', + 'helper_vfwmsac_vv_w', + 'helper_vfwnmsac_vv_h', + 'helper_vfwnmsac_vv_w', + 'helper_vfwmacc_vf_h', + 'helper_vfwmacc_vf_w', + 'helper_vfwnmacc_vf_h', + 'helper_vfwnmacc_vf_w', + 'helper_vfwmsac_vf_h', + 'helper_vfwmsac_vf_w', + 'helper_vfwnmsac_vf_h', + 'helper_vfwnmsac_vf_w', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 03092f92..7ddddc5e 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4511,6 +4511,22 @@ #define helper_vfnmsub_vf_h helper_vfnmsub_vf_h_riscv32 #define helper_vfnmsub_vf_w helper_vfnmsub_vf_w_riscv32 #define helper_vfnmsub_vf_d helper_vfnmsub_vf_d_riscv32 +#define helper_vfwmacc_vv_h helper_vfwmacc_vv_h_riscv32 +#define helper_vfwmacc_vv_w helper_vfwmacc_vv_w_riscv32 +#define helper_vfwnmacc_vv_h helper_vfwnmacc_vv_h_riscv32 +#define helper_vfwnmacc_vv_w helper_vfwnmacc_vv_w_riscv32 +#define helper_vfwmsac_vv_h helper_vfwmsac_vv_h_riscv32 +#define helper_vfwmsac_vv_w helper_vfwmsac_vv_w_riscv32 +#define helper_vfwnmsac_vv_h helper_vfwnmsac_vv_h_riscv32 +#define helper_vfwnmsac_vv_w helper_vfwnmsac_vv_w_riscv32 +#define helper_vfwmacc_vf_h helper_vfwmacc_vf_h_riscv32 +#define helper_vfwmacc_vf_w helper_vfwmacc_vf_w_riscv32 +#define helper_vfwnmacc_vf_h helper_vfwnmacc_vf_h_riscv32 +#define helper_vfwnmacc_vf_w helper_vfwnmacc_vf_w_riscv32 +#define helper_vfwmsac_vf_h helper_vfwmsac_vf_h_riscv32 +#define helper_vfwmsac_vf_w helper_vfwmsac_vf_w_riscv32 +#define helper_vfwnmsac_vf_h helper_vfwnmsac_vf_h_riscv32 +#define helper_vfwnmsac_vf_w helper_vfwnmsac_vf_w_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index e1238fe8..3c97ef56 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4511,6 +4511,22 @@ #define helper_vfnmsub_vf_h helper_vfnmsub_vf_h_riscv64 #define helper_vfnmsub_vf_w helper_vfnmsub_vf_w_riscv64 #define helper_vfnmsub_vf_d helper_vfnmsub_vf_d_riscv64 +#define helper_vfwmacc_vv_h helper_vfwmacc_vv_h_riscv64 +#define helper_vfwmacc_vv_w helper_vfwmacc_vv_w_riscv64 +#define helper_vfwnmacc_vv_h helper_vfwnmacc_vv_h_riscv64 +#define helper_vfwnmacc_vv_w helper_vfwnmacc_vv_w_riscv64 +#define helper_vfwmsac_vv_h helper_vfwmsac_vv_h_riscv64 +#define helper_vfwmsac_vv_w helper_vfwmsac_vv_w_riscv64 +#define helper_vfwnmsac_vv_h helper_vfwnmsac_vv_h_riscv64 +#define helper_vfwnmsac_vv_w helper_vfwnmsac_vv_w_riscv64 +#define helper_vfwmacc_vf_h helper_vfwmacc_vf_h_riscv64 +#define helper_vfwmacc_vf_w helper_vfwmacc_vf_w_riscv64 +#define helper_vfwnmacc_vf_h helper_vfwnmacc_vf_h_riscv64 +#define helper_vfwnmacc_vf_w helper_vfwnmacc_vf_w_riscv64 +#define helper_vfwmsac_vf_h helper_vfwmsac_vf_h_riscv64 +#define helper_vfwmsac_vf_w helper_vfwmsac_vf_w_riscv64 +#define helper_vfwnmsac_vf_h helper_vfwnmsac_vf_h_riscv64 +#define helper_vfwnmsac_vf_w helper_vfwnmsac_vf_w_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index 661fc2c2..312c58e2 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -909,3 +909,20 @@ DEF_HELPER_6(vfmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsub_vf_h, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsub_vf_w, void, ptr, ptr, i64, ptr, env, i32) DEF_HELPER_6(vfnmsub_vf_d, void, ptr, ptr, i64, ptr, env, i32) + +DEF_HELPER_6(vfwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwnmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwnmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwnmsac_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwnmsac_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vfwmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwnmacc_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwnmacc_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwnmsac_vf_h, void, ptr, ptr, i64, ptr, env, i32) +DEF_HELPER_6(vfwnmsac_vf_w, void, ptr, ptr, i64, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index 9ca765d3..c9d50783 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -481,6 +481,14 @@ vfmsub_vv 101010 . ..... ..... 001 ..... 1010111 @r_vm vfmsub_vf 101010 . ..... ..... 101 ..... 1010111 @r_vm vfnmsub_vv 101011 . ..... ..... 001 ..... 1010111 @r_vm vfnmsub_vf 101011 . ..... ..... 101 ..... 1010111 @r_vm +vfwmacc_vv 111100 . ..... ..... 001 ..... 1010111 @r_vm +vfwmacc_vf 111100 . ..... ..... 101 ..... 1010111 @r_vm +vfwnmacc_vv 111101 . ..... ..... 001 ..... 1010111 @r_vm +vfwnmacc_vf 111101 . ..... ..... 101 ..... 1010111 @r_vm +vfwmsac_vv 111110 . ..... ..... 001 ..... 1010111 @r_vm +vfwmsac_vf 111110 . ..... ..... 101 ..... 1010111 @r_vm +vfwnmsac_vv 111111 . ..... ..... 001 ..... 1010111 @r_vm +vfwnmsac_vf 111111 . ..... ..... 101 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index e2ded4f6..d78e2285 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -2111,3 +2111,13 @@ GEN_OPFVF_TRANS(vfmadd_vf, opfvf_check) GEN_OPFVF_TRANS(vfnmadd_vf, opfvf_check) GEN_OPFVF_TRANS(vfmsub_vf, opfvf_check) GEN_OPFVF_TRANS(vfnmsub_vf, opfvf_check) + +/* Vector Widening Floating-Point Fused Multiply-Add Instructions */ +GEN_OPFVV_WIDEN_TRANS(vfwmacc_vv, opfvv_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwnmacc_vv, opfvv_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwmsac_vv, opfvv_widen_check) +GEN_OPFVV_WIDEN_TRANS(vfwnmsac_vv, opfvv_widen_check) +GEN_OPFVF_WIDEN_TRANS(vfwmacc_vf) +GEN_OPFVF_WIDEN_TRANS(vfwnmacc_vf) +GEN_OPFVF_WIDEN_TRANS(vfwmsac_vf) +GEN_OPFVF_WIDEN_TRANS(vfwnmsac_vf) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 368db457..d3165e07 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -3684,3 +3684,94 @@ RVVCALL(OPFVF3, vfnmsub_vf_d, OP_UUU_D, H8, H8, fnmsub64) GEN_VEXT_VF(vfnmsub_vf_h, 2, 2, clearh) GEN_VEXT_VF(vfnmsub_vf_w, 4, 4, clearl) GEN_VEXT_VF(vfnmsub_vf_d, 8, 8, clearq) + +/* Vector Widening Floating-Point Fused Multiply-Add Instructions */ +static uint32_t fwmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) +{ + return float32_muladd(float16_to_float32(a, true, s), + float16_to_float32(b, true, s), d, 0, s); +} + +static uint64_t fwmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) +{ + return float64_muladd(float32_to_float64(a, s), + float32_to_float64(b, s), d, 0, s); +} + +RVVCALL(OPFVV3, vfwmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwmacc16) +RVVCALL(OPFVV3, vfwmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwmacc32) +GEN_VEXT_VV_ENV(vfwmacc_vv_h, 2, 4, clearl) +GEN_VEXT_VV_ENV(vfwmacc_vv_w, 4, 8, clearq) +RVVCALL(OPFVF3, vfwmacc_vf_h, WOP_UUU_H, H4, H2, fwmacc16) +RVVCALL(OPFVF3, vfwmacc_vf_w, WOP_UUU_W, H8, H4, fwmacc32) +GEN_VEXT_VF(vfwmacc_vf_h, 2, 4, clearl) +GEN_VEXT_VF(vfwmacc_vf_w, 4, 8, clearq) + +static uint32_t fwnmacc16(uint16_t a, uint16_t b, uint32_t d, float_status *s) +{ + return float32_muladd(float16_to_float32(a, true, s), + float16_to_float32(b, true, s), d, + float_muladd_negate_c | float_muladd_negate_product, s); +} + +static uint64_t fwnmacc32(uint32_t a, uint32_t b, uint64_t d, float_status *s) +{ + return float64_muladd(float32_to_float64(a, s), + float32_to_float64(b, s), d, + float_muladd_negate_c | float_muladd_negate_product, s); +} + +RVVCALL(OPFVV3, vfwnmacc_vv_h, WOP_UUU_H, H4, H2, H2, fwnmacc16) +RVVCALL(OPFVV3, vfwnmacc_vv_w, WOP_UUU_W, H8, H4, H4, fwnmacc32) +GEN_VEXT_VV_ENV(vfwnmacc_vv_h, 2, 4, clearl) +GEN_VEXT_VV_ENV(vfwnmacc_vv_w, 4, 8, clearq) +RVVCALL(OPFVF3, vfwnmacc_vf_h, WOP_UUU_H, H4, H2, fwnmacc16) +RVVCALL(OPFVF3, vfwnmacc_vf_w, WOP_UUU_W, H8, H4, fwnmacc32) +GEN_VEXT_VF(vfwnmacc_vf_h, 2, 4, clearl) +GEN_VEXT_VF(vfwnmacc_vf_w, 4, 8, clearq) + +static uint32_t fwmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s) +{ + return float32_muladd(float16_to_float32(a, true, s), + float16_to_float32(b, true, s), d, + float_muladd_negate_c, s); +} + +static uint64_t fwmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s) +{ + return float64_muladd(float32_to_float64(a, s), + float32_to_float64(b, s), d, + float_muladd_negate_c, s); +} + +RVVCALL(OPFVV3, vfwmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwmsac16) +RVVCALL(OPFVV3, vfwmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwmsac32) +GEN_VEXT_VV_ENV(vfwmsac_vv_h, 2, 4, clearl) +GEN_VEXT_VV_ENV(vfwmsac_vv_w, 4, 8, clearq) +RVVCALL(OPFVF3, vfwmsac_vf_h, WOP_UUU_H, H4, H2, fwmsac16) +RVVCALL(OPFVF3, vfwmsac_vf_w, WOP_UUU_W, H8, H4, fwmsac32) +GEN_VEXT_VF(vfwmsac_vf_h, 2, 4, clearl) +GEN_VEXT_VF(vfwmsac_vf_w, 4, 8, clearq) + +static uint32_t fwnmsac16(uint16_t a, uint16_t b, uint32_t d, float_status *s) +{ + return float32_muladd(float16_to_float32(a, true, s), + float16_to_float32(b, true, s), d, + float_muladd_negate_product, s); +} + +static uint64_t fwnmsac32(uint32_t a, uint32_t b, uint64_t d, float_status *s) +{ + return float64_muladd(float32_to_float64(a, s), + float32_to_float64(b, s), d, + float_muladd_negate_product, s); +} + +RVVCALL(OPFVV3, vfwnmsac_vv_h, WOP_UUU_H, H4, H2, H2, fwnmsac16) +RVVCALL(OPFVV3, vfwnmsac_vv_w, WOP_UUU_W, H8, H4, H4, fwnmsac32) +GEN_VEXT_VV_ENV(vfwnmsac_vv_h, 2, 4, clearl) +GEN_VEXT_VV_ENV(vfwnmsac_vv_w, 4, 8, clearq) +RVVCALL(OPFVF3, vfwnmsac_vf_h, WOP_UUU_H, H4, H2, fwnmsac16) +RVVCALL(OPFVF3, vfwnmsac_vf_w, WOP_UUU_W, H8, H4, fwnmsac32) +GEN_VEXT_VF(vfwnmsac_vf_h, 2, 4, clearl) +GEN_VEXT_VF(vfwnmsac_vf_w, 4, 8, clearq)