From 96d299bd6f533d50574201d3cdad3640b8b3c283 Mon Sep 17 00:00:00 2001 From: Aleksandar Markovic Date: Tue, 23 Oct 2018 13:12:33 -0400 Subject: [PATCH] target/mips: Add basic description of MXU ASE Add a comment that contains a basic description of MXU ASE. Backports commit b158d449bbfe71bb203fdce978a4a33c38a4e821 from qemu --- qemu/target/mips/translate.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c index 20311747..2e066b10 100644 --- a/qemu/target/mips/translate.c +++ b/qemu/target/mips/translate.c @@ -1385,6 +1385,23 @@ enum { OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09, }; +/* + * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET + * ============================================ + * + * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32 + * instructions set. It is designed to fit the needs of signal, graphical and + * video processing applications. MXU instruction set is used in Xburst family + * of microprocessors by Ingenic. + * + * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is + * the control register. + * + * Compiled after: + * + * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit + * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017 + */ #define gen_helper_0e0i(tcg_ctx, name, arg) do { \ TCGv_i32 helper_tmp = tcg_const_i32(tcg_ctx, arg); \