From 97b7155db17214702d6962aa2d5ab701f7ccf829 Mon Sep 17 00:00:00 2001
From: Craig Janeczek <jancraig@amazon.com>
Date: Sun, 11 Nov 2018 07:04:56 -0500
Subject: [PATCH] target/mips: Add emulation of MXU instruction D16MAC

Backports commit e67915b4277932def37b15cf8434323d096edeaa from qemu
---
 qemu/target/mips/translate.c | 97 ++++++++++++++++++++++++++++++++++--
 1 file changed, 94 insertions(+), 3 deletions(-)

diff --git a/qemu/target/mips/translate.c b/qemu/target/mips/translate.c
index fe8f37fe..67e7fe40 100644
--- a/qemu/target/mips/translate.c
+++ b/qemu/target/mips/translate.c
@@ -24166,6 +24166,12 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
 #define MXU_APTN1_A    0
 #define MXU_APTN1_S    1
 
+/* MXU accumulate add/subtract 2-bit pattern 'aptn2' */
+#define MXU_APTN2_AA    0
+#define MXU_APTN2_AS    1
+#define MXU_APTN2_SA    2
+#define MXU_APTN2_SS    3
+
 /* MXU execute add/subtract 2-bit pattern 'eptn2' */
 #define MXU_EPTN2_AA    0
 #define MXU_EPTN2_AS    1
@@ -24388,6 +24394,93 @@ static void gen_mxu_d16mul(DisasContext *ctx)
     tcg_temp_free(tcg_ctx, t3);
 }
 
+/*
+ * D16MAC XRa, XRb, XRc, XRd, aptn2, optn2 - Signed 16 bit pattern multiply
+ *                                           and accumulate
+ */
+static void gen_mxu_d16mac(DisasContext *ctx)
+{
+    TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
+    TCGv t0, t1, t2, t3;
+    TCGLabel *l0;
+    uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;
+
+    t0 = tcg_temp_new(tcg_ctx);
+    t1 = tcg_temp_new(tcg_ctx);
+    t2 = tcg_temp_new(tcg_ctx);
+    t3 = tcg_temp_new(tcg_ctx);
+
+    l0 = gen_new_label(tcg_ctx);
+
+    XRa = extract32(ctx->opcode, 6, 4);
+    XRb = extract32(ctx->opcode, 10, 4);
+    XRc = extract32(ctx->opcode, 14, 4);
+    XRd = extract32(ctx->opcode, 18, 4);
+    optn2 = extract32(ctx->opcode, 22, 2);
+    aptn2 = extract32(ctx->opcode, 24, 2);
+
+    gen_load_mxu_cr(ctx, t0);
+    tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
+    tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
+
+    gen_load_mxu_gpr(ctx, t1, XRb);
+    tcg_gen_sextract_tl(tcg_ctx, t0, t1, 0, 16);
+    tcg_gen_sextract_tl(tcg_ctx, t1, t1, 16, 16);
+
+    gen_load_mxu_gpr(ctx, t3, XRc);
+    tcg_gen_sextract_tl(tcg_ctx, t2, t3, 0, 16);
+    tcg_gen_sextract_tl(tcg_ctx, t3, t3, 16, 16);
+
+    switch (optn2) {
+    case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
+        tcg_gen_mul_tl(tcg_ctx, t3, t1, t3);
+        tcg_gen_mul_tl(tcg_ctx, t2, t0, t2);
+        break;
+    case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
+        tcg_gen_mul_tl(tcg_ctx, t3, t0, t3);
+        tcg_gen_mul_tl(tcg_ctx, t2, t0, t2);
+        break;
+    case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
+        tcg_gen_mul_tl(tcg_ctx, t3, t1, t3);
+        tcg_gen_mul_tl(tcg_ctx, t2, t1, t2);
+        break;
+    case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
+        tcg_gen_mul_tl(tcg_ctx, t3, t0, t3);
+        tcg_gen_mul_tl(tcg_ctx, t2, t1, t2);
+        break;
+    }
+    gen_load_mxu_gpr(ctx, t0, XRa);
+    gen_load_mxu_gpr(ctx, t1, XRd);
+
+    switch (aptn2) {
+    case MXU_APTN2_AA:
+        tcg_gen_add_tl(tcg_ctx, t3, t0, t3);
+        tcg_gen_add_tl(tcg_ctx, t2, t1, t2);
+        break;
+    case MXU_APTN2_AS:
+        tcg_gen_add_tl(tcg_ctx, t3, t0, t3);
+        tcg_gen_sub_tl(tcg_ctx, t2, t1, t2);
+        break;
+    case MXU_APTN2_SA:
+        tcg_gen_sub_tl(tcg_ctx, t3, t0, t3);
+        tcg_gen_add_tl(tcg_ctx, t2, t1, t2);
+        break;
+    case MXU_APTN2_SS:
+        tcg_gen_sub_tl(tcg_ctx, t3, t0, t3);
+        tcg_gen_sub_tl(tcg_ctx, t2, t1, t2);
+        break;
+    }
+    gen_store_mxu_gpr(ctx, t3, XRa);
+    gen_store_mxu_gpr(ctx, t2, XRd);
+
+    gen_set_label(tcg_ctx, l0);
+
+    tcg_temp_free(tcg_ctx, t0);
+    tcg_temp_free(tcg_ctx, t1);
+    tcg_temp_free(tcg_ctx, t2);
+    tcg_temp_free(tcg_ctx, t3);
+}
+
 
 /*
  * Decoding engine for MXU
@@ -25358,9 +25451,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
         decode_opc_mxu__pool03(env, ctx);
         break;
     case OPC_MXU_D16MAC:
-        /* TODO: Implement emulation of D16MAC instruction. */
-        MIPS_INVAL("OPC_MXU_D16MAC");
-        generate_exception_end(ctx, EXCP_RI);
+        gen_mxu_d16mac(ctx);
         break;
     case OPC_MXU_D16MACF:
         /* TODO: Implement emulation of D16MACF instruction. */