diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c
index 9460b758..04521f3a 100644
--- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c
+++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c
@@ -950,7 +950,7 @@ static void gen_vec_rsub8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
 
 static void gen_vec_rsub16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b)
 {
-    tcg_gen_vec_sub8_i64(s, d, b, a);
+    tcg_gen_vec_sub16_i64(s, d, b, a);
 }
 
 static void gen_rsub_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)