From 98982dbe492fd46977adb9d2cf8c6123f8109008 Mon Sep 17 00:00:00 2001 From: Frank Chang Date: Mon, 8 Mar 2021 12:12:34 -0500 Subject: [PATCH] target/riscv: correct the gvec IR called in gen_vec_rsub16_i64() Backports 1989205c4e973bc7f9fac0ce0700993f30582538 --- qemu/target/riscv/insn_trans/trans_rvv.inc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 9460b758..04521f3a 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -950,7 +950,7 @@ static void gen_vec_rsub8_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) static void gen_vec_rsub16_i64(TCGContext *s, TCGv_i64 d, TCGv_i64 a, TCGv_i64 b) { - tcg_gen_vec_sub8_i64(s, d, b, a); + tcg_gen_vec_sub16_i64(s, d, b, a); } static void gen_rsub_i32(TCGContext *s, TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)