From 996f38056fa9b85a13600731f35b25d8a0aebc6e Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 8 Mar 2018 12:30:59 -0500 Subject: [PATCH] target/arm/cpu.h: add additional float_status flags Half-precision flush to zero behaviour is controlled by a separate FZ16 bit in the FPCR. To handle this we pass a pointer to fp_status_fp16 when working on half-precision operations. The value of the presented FPCR is calculated from an amalgam of the two when read. Backports commit d81ce0ef2c4f1052fcdef891a12499eca3084db7 from qemu --- qemu/target/arm/cpu.h | 32 +++++++++++++++----- qemu/target/arm/helper.c | 26 ++++++++++++---- qemu/target/arm/translate-a64.c | 53 ++++++++++++++++++--------------- 3 files changed, 75 insertions(+), 36 deletions(-) diff --git a/qemu/target/arm/cpu.h b/qemu/target/arm/cpu.h index cd334da3..c5909971 100644 --- a/qemu/target/arm/cpu.h +++ b/qemu/target/arm/cpu.h @@ -542,19 +542,29 @@ typedef struct CPUARMState { /* scratch space when Tn are not sufficient. */ uint32_t scratch[8]; - /* fp_status is the "normal" fp status. standard_fp_status retains - * values corresponding to the ARM "Standard FPSCR Value", ie - * default-NaN, flush-to-zero, round-to-nearest and is used by - * any operations (generally Neon) which the architecture defines - * as controlled by the standard FPSCR value rather than the FPSCR. + /* There are a number of distinct float control structures: + * + * fp_status: is the "normal" fp status. + * fp_status_fp16: used for half-precision calculations + * standard_fp_status : the ARM "Standard FPSCR Value" + * + * Half-precision operations are governed by a separate + * flush-to-zero control bit in FPSCR:FZ16. We pass a separate + * status structure to control this. + * + * The "Standard FPSCR", ie default-NaN, flush-to-zero, + * round-to-nearest and is used by any operations (generally + * Neon) which the architecture defines as controlled by the + * standard FPSCR value rather than the FPSCR. * * To avoid having to transfer exception bits around, we simply * say that the FPSCR cumulative exception flags are the logical - * OR of the flags in the two fp statuses. This relies on the + * OR of the flags in the three fp statuses. This relies on the * only thing which needs to read the exception flags being * an explicit FPSCR read. */ float_status fp_status; + float_status fp_status_f16; float_status standard_fp_status; /* ZCR_EL[1-3] */ @@ -1165,12 +1175,20 @@ static inline void xpsr_write(CPUARMState *env, uint32_t val, uint32_t mask) uint32_t vfp_get_fpscr(CPUARMState *env); void vfp_set_fpscr(CPUARMState *env, uint32_t val); -/* For A64 the FPSCR is split into two logically distinct registers, +/* FPCR, Floating Point Control Register + * FPSR, Floating Poiht Status Register + * + * For A64 the FPSCR is split into two logically distinct registers, * FPCR and FPSR. However since they still use non-overlapping bits * we store the underlying state in fpscr and just mask on read/write. */ #define FPSR_MASK 0xf800009f #define FPCR_MASK 0x07f79f00 + +#define FPCR_FZ16 (1 << 19) /* ARMv8.2+, FP16 flush-to-zero */ +#define FPCR_FZ (1 << 24) /* Flush-to-zero enable bit */ +#define FPCR_DN (1 << 25) /* Default NaN enable bit */ + static inline uint32_t vfp_get_fpsr(CPUARMState *env) { return vfp_get_fpscr(env) & FPSR_MASK; diff --git a/qemu/target/arm/helper.c b/qemu/target/arm/helper.c index e294c2e9..eb3e0de6 100644 --- a/qemu/target/arm/helper.c +++ b/qemu/target/arm/helper.c @@ -10295,6 +10295,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env) | (env->vfp.vec_stride << 20); i = get_float_exception_flags(&env->vfp.fp_status); i |= get_float_exception_flags(&env->vfp.standard_fp_status); + i |= get_float_exception_flags(&env->vfp.fp_status_f16); fpscr |= vfp_exceptbits_from_host(i); return fpscr; } @@ -10352,16 +10353,31 @@ void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val) break; } set_float_rounding_mode(i, &env->vfp.fp_status); + set_float_rounding_mode(i, &env->vfp.fp_status_f16); } - if (changed & (1 << 24)) { - set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); - set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status); + if (changed & FPCR_FZ16) { + bool ftz_enabled = val & FPCR_FZ16; + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status_f16); + } + if (changed & FPCR_FZ) { + bool ftz_enabled = val & FPCR_FZ; + set_flush_to_zero(ftz_enabled, &env->vfp.fp_status); + set_flush_inputs_to_zero(ftz_enabled, &env->vfp.fp_status); + } + if (changed & FPCR_DN) { + bool dnan_enabled = val & FPCR_DN; + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status); + set_default_nan_mode(dnan_enabled, &env->vfp.fp_status_f16); } - if (changed & (1 << 25)) - set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status); + /* The exception flags are ORed together when we read fpscr so we + * only need to preserve the current state in one of our + * float_status values. + */ i = vfp_exceptbits_to_host(val); set_float_exception_flags(i, &env->vfp.fp_status); + set_float_exception_flags(0, &env->vfp.fp_status_f16); set_float_exception_flags(0, &env->vfp.standard_fp_status); } diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 1c75e4da..fe2a7606 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -671,16 +671,21 @@ static void write_fp_sreg(DisasContext *s, int reg, TCGv_i32 v) tcg_temp_free_i64(tcg_ctx, tmp); } -static TCGv_ptr get_fpstatus_ptr(TCGContext *tcg_ctx) +static TCGv_ptr get_fpstatus_ptr(TCGContext *tcg_ctx, bool is_f16) { TCGv_ptr statusptr = tcg_temp_new_ptr(tcg_ctx); int offset; - /* In A64 all instructions (both FP and Neon) use the FPCR; - * there is no equivalent of the A32 Neon "standard FPSCR value" - * and all operations use vfp.fp_status. + /* In A64 all instructions (both FP and Neon) use the FPCR; there + * is no equivalent of the A32 Neon "standard FPSCR value". + * However half-precision operations operate under a different + * FZ16 flag and use vfp.fp_status_f16 instead of vfp.fp_status. */ - offset = offsetof(CPUARMState, vfp.fp_status); + if (is_f16) { + offset = offsetof(CPUARMState, vfp.fp_status_f16); + } else { + offset = offsetof(CPUARMState, vfp.fp_status); + } tcg_gen_addi_ptr(tcg_ctx, statusptr, tcg_ctx->cpu_env, offset); return statusptr; } @@ -4515,7 +4520,7 @@ static void handle_fp_compare(DisasContext *s, bool is_double, { TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i64 tcg_flags = tcg_temp_new_i64(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); if (is_double) { TCGv_i64 tcg_vn, tcg_vm; @@ -4693,7 +4698,7 @@ static void handle_fp_1src_single(DisasContext *s, int opcode, int rd, int rn) TCGv_i32 tcg_op; TCGv_i32 tcg_res; - fpst = get_fpstatus_ptr(tcg_ctx); + fpst = get_fpstatus_ptr(tcg_ctx, false); tcg_op = read_fp_sreg(s, rn); tcg_res = tcg_temp_new_i32(tcg_ctx); @@ -4756,7 +4761,7 @@ static void handle_fp_1src_double(DisasContext *s, int opcode, int rd, int rn) return; } - fpst = get_fpstatus_ptr(tcg_ctx); + fpst = get_fpstatus_ptr(tcg_ctx, false); tcg_op = read_fp_dreg(s, rn); tcg_res = tcg_temp_new_i64(tcg_ctx); @@ -4938,7 +4943,7 @@ static void handle_fp_2src_single(DisasContext *s, int opcode, TCGv_ptr fpst; tcg_res = tcg_temp_new_i32(tcg_ctx); - fpst = get_fpstatus_ptr(tcg_ctx); + fpst = get_fpstatus_ptr(tcg_ctx, false); tcg_op1 = read_fp_sreg(s, rn); tcg_op2 = read_fp_sreg(s, rm); @@ -4992,7 +4997,7 @@ static void handle_fp_2src_double(DisasContext *s, int opcode, TCGv_ptr fpst; tcg_res = tcg_temp_new_i64(tcg_ctx); - fpst = get_fpstatus_ptr(tcg_ctx); + fpst = get_fpstatus_ptr(tcg_ctx, false); tcg_op1 = read_fp_dreg(s, rn); tcg_op2 = read_fp_dreg(s, rm); @@ -5079,7 +5084,7 @@ static void handle_fp_3src_single(DisasContext *s, bool o0, bool o1, TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i32 tcg_op1, tcg_op2, tcg_op3; TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); tcg_op1 = read_fp_sreg(s, rn); tcg_op2 = read_fp_sreg(s, rm); @@ -5118,7 +5123,7 @@ static void handle_fp_3src_double(DisasContext *s, bool o0, bool o1, TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGv_i64 tcg_op1, tcg_op2, tcg_op3; TCGv_i64 tcg_res = tcg_temp_new_i64(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); tcg_op1 = read_fp_dreg(s, rn); tcg_op2 = read_fp_dreg(s, rm); @@ -5261,7 +5266,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, int rn, int opcode, TCGv_ptr tcg_fpstatus; TCGv_i32 tcg_shift; - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx); + tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, false); tcg_shift = tcg_const_i32(tcg_ctx, 64 - scale); @@ -5980,7 +5985,7 @@ static void disas_simd_across_lanes(DisasContext *s, uint32_t insn) TCGv_i32 tcg_elt1 = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_elt2 = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_elt3 = tcg_temp_new_i32(tcg_ctx); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); assert(esize == 32); assert(elements == 4); @@ -6489,7 +6494,7 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn) } size = extract32(size, 0, 1) ? 3 : 2; - fpst = get_fpstatus_ptr(tcg_ctx); + fpst = get_fpstatus_ptr(tcg_ctx, false); break; default: unallocated_encoding(s); @@ -6988,7 +6993,7 @@ static void handle_simd_intfp_conv(DisasContext *s, int rd, int rn, { TCGContext *tcg_ctx = s->uc->tcg_ctx; bool is_double = size == 3 ? true : false; - TCGv_ptr tcg_fpst = get_fpstatus_ptr(tcg_ctx); + TCGv_ptr tcg_fpst = get_fpstatus_ptr(tcg_ctx, false); TCGv_i32 tcg_shift = tcg_const_i32(tcg_ctx, fracbits); TCGv_i64 tcg_int = tcg_temp_new_i64(tcg_ctx); TCGMemOp mop = size | (is_signed ? MO_SIGN : 0); @@ -7105,7 +7110,7 @@ static void handle_simd_shift_fpint_conv(DisasContext *s, bool is_scalar, tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(FPROUNDING_ZERO)); gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, tcg_ctx->cpu_env); - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx); + tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, false); tcg_shift = tcg_const_i32(tcg_ctx, fracbits); if (is_double) { @@ -7455,7 +7460,7 @@ static void handle_3same_float(DisasContext *s, int size, int elements, { TCGContext *tcg_ctx = s->uc->tcg_ctx; int pass; - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); for (pass = 0; pass < elements; pass++) { if (size) { @@ -7922,7 +7927,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, int opcode, return; } - fpst = get_fpstatus_ptr(tcg_ctx); + fpst = get_fpstatus_ptr(tcg_ctx, false); if (is_double) { TCGv_i64 tcg_op = tcg_temp_new_i64(tcg_ctx); @@ -8031,7 +8036,7 @@ static void handle_2misc_reciprocal(DisasContext *s, int opcode, { TCGContext *tcg_ctx = s->uc->tcg_ctx; bool is_double = (size == 3); - TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx); + TCGv_ptr fpst = get_fpstatus_ptr(tcg_ctx, false); if (is_double) { TCGv_i64 tcg_op = tcg_temp_new_i64(tcg_ctx); @@ -8434,7 +8439,7 @@ static void disas_simd_scalar_two_reg_misc(DisasContext *s, uint32_t insn) if (is_fcvt) { tcg_rmode = tcg_const_i32(tcg_ctx, arm_rmode_to_sf(rmode)); gen_helper_set_rmode(tcg_ctx, tcg_rmode, tcg_rmode, tcg_ctx->cpu_env); - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx); + tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, false); } else { tcg_rmode = NULL; tcg_fpstatus = NULL; @@ -9661,7 +9666,7 @@ static void handle_simd_3same_pair(DisasContext *s, int is_q, int u, int opcode, /* Floating point operations need fpst */ if (opcode >= 0x58) { - fpst = get_fpstatus_ptr(tcg_ctx); + fpst = get_fpstatus_ptr(tcg_ctx, false); } else { fpst = NULL; } @@ -10831,7 +10836,7 @@ static void disas_simd_two_reg_misc(DisasContext *s, uint32_t insn) } if (need_fpstatus) { - tcg_fpstatus = get_fpstatus_ptr(tcg_ctx); + tcg_fpstatus = get_fpstatus_ptr(tcg_ctx, false); } else { tcg_fpstatus = NULL; } @@ -11212,7 +11217,7 @@ static void disas_simd_indexed(DisasContext *s, uint32_t insn) } if (is_fp) { - fpst = get_fpstatus_ptr(tcg_ctx); + fpst = get_fpstatus_ptr(tcg_ctx, false); } else { fpst = NULL; }