From 9b3671e9ad5ddf7c36bf3919d33f2cdbe09ee8a4 Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Fri, 26 Feb 2021 14:12:23 -0500 Subject: [PATCH] target/arm: Use tcg_gen_gvec_bitsel for trans_SEL_pppp The gvec operation was added after the initial implementation of the SEL instruction and was missed in the conversion. Backports d4bc623254b55e2f9613c9450216fa7e50c03929 --- qemu/target/arm/translate-sve.c | 32 +++++++++----------------------- 1 file changed, 9 insertions(+), 23 deletions(-) diff --git a/qemu/target/arm/translate-sve.c b/qemu/target/arm/translate-sve.c index 01b46f0b..50d1cebd 100644 --- a/qemu/target/arm/translate-sve.c +++ b/qemu/target/arm/translate-sve.c @@ -1249,34 +1249,20 @@ static bool trans_EOR_pppp(DisasContext *s, arg_rprr_s *a) return do_pppp_flags(s, a, &op); } -static void gen_sel_pg_i64(TCGContext *s, TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg) -{ - tcg_gen_and_i64(s, pn, pn, pg); - tcg_gen_andc_i64(s, pm, pm, pg); - tcg_gen_or_i64(s, pd, pn, pm); -} - -static void gen_sel_pg_vec(TCGContext *s, unsigned vece, TCGv_vec pd, TCGv_vec pn, - TCGv_vec pm, TCGv_vec pg) -{ - tcg_gen_and_vec(s, vece, pn, pn, pg); - tcg_gen_andc_vec(s, vece, pm, pm, pg); - tcg_gen_or_vec(s, vece, pd, pn, pm); -} - static bool trans_SEL_pppp(DisasContext *s, arg_rprr_s *a) { - static const GVecGen4 op = { - .fni8 = gen_sel_pg_i64, - .fniv = gen_sel_pg_vec, - .fno = gen_helper_sve_sel_pppp, - .prefer_i64 = TCG_TARGET_REG_BITS == 64, - }; - if (a->s) { return false; } - return do_pppp_flags(s, a, &op); + if (sve_access_check(s)) { + TCGContext *tcg_ctx = s->uc->tcg_ctx; + unsigned psz = pred_gvec_reg_size(s); + tcg_gen_gvec_bitsel(tcg_ctx, MO_8, pred_full_reg_offset(s, a->rd), + pred_full_reg_offset(s, a->pg), + pred_full_reg_offset(s, a->rn), + pred_full_reg_offset(s, a->rm), psz, psz); + } + return true; } static void gen_orr_pg_i64(TCGContext *s, TCGv_i64 pd, TCGv_i64 pn, TCGv_i64 pm, TCGv_i64 pg)