From 9c2a5963d0a8ea9d037c3e9b99a34b7db8fb621d Mon Sep 17 00:00:00 2001 From: Richard Henderson Date: Tue, 5 Feb 2019 17:00:53 -0500 Subject: [PATCH] exec: Add target-specific tlb bits to MemTxAttrs These bits can be used to cache target-specific data in cputlb read from the page tables. Backports commit d3765835ed02f91f0c6cbb452874209a6af4a730 from qemu --- qemu/include/exec/memattrs.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/qemu/include/exec/memattrs.h b/qemu/include/exec/memattrs.h index ad4e18e9..651299a4 100644 --- a/qemu/include/exec/memattrs.h +++ b/qemu/include/exec/memattrs.h @@ -35,6 +35,18 @@ typedef struct MemTxAttrs { unsigned int secure:1; /* Memory access is usermode (unprivileged) */ unsigned int user:1; + /* Requester ID (for MSI for example) */ + unsigned int requester_id:16; + /* + * The following are target-specific page-table bits. These are not + * related to actual memory transactions at all. However, this structure + * is part of the tlb_fill interface, cached in the cputlb structure, + * and has unused bits. These fields will be read by target-specific + * helpers using env->iotlb[mmu_idx][tlb_index()].attrs.target_tlb_bitN. + */ + unsigned int target_tlb_bit0 : 1; + unsigned int target_tlb_bit1 : 1; + unsigned int target_tlb_bit2 : 1; } MemTxAttrs; /* Bus masters which don't specify any attributes will get this,