From 9d14cc8d35e092b9e51cb461335692e368ff6924 Mon Sep 17 00:00:00 2001 From: LIU Zhiwei Date: Fri, 5 Mar 2021 09:13:01 -0500 Subject: [PATCH] target/riscv: vector widening integer multiply-add instructions Backports 2b587b335050dbc0cb3823758341f145c0375312 --- qemu/header_gen.py | 21 +++++++++ qemu/riscv32.h | 21 +++++++++ qemu/riscv64.h | 21 +++++++++ qemu/target/riscv/helper.h | 22 ++++++++++ qemu/target/riscv/insn32.decode | 7 +++ qemu/target/riscv/insn_trans/trans_rvv.inc.c | 9 ++++ qemu/target/riscv/vector_helper.c | 45 ++++++++++++++++++++ 7 files changed, 146 insertions(+) diff --git a/qemu/header_gen.py b/qemu/header_gen.py index 6791e0bb..95e061ef 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -6805,6 +6805,27 @@ riscv_symbols = ( 'helper_vnmsub_vx_h', 'helper_vnmsub_vx_w', 'helper_vnmsub_vx_d', + 'helper_vwmaccu_vv_b', + 'helper_vwmaccu_vv_h', + 'helper_vwmaccu_vv_w', + 'helper_vwmacc_vv_b', + 'helper_vwmacc_vv_h', + 'helper_vwmacc_vv_w', + 'helper_vwmaccsu_vv_b', + 'helper_vwmaccsu_vv_h', + 'helper_vwmaccsu_vv_w', + 'helper_vwmaccu_vx_b', + 'helper_vwmaccu_vx_h', + 'helper_vwmaccu_vx_w', + 'helper_vwmacc_vx_b', + 'helper_vwmacc_vx_h', + 'helper_vwmacc_vx_w', + 'helper_vwmaccsu_vx_b', + 'helper_vwmaccsu_vx_h', + 'helper_vwmaccsu_vx_w', + 'helper_vwmaccus_vx_b', + 'helper_vwmaccus_vx_h', + 'helper_vwmaccus_vx_w', 'pmp_hart_has_privs', 'pmpaddr_csr_read', 'pmpaddr_csr_write', diff --git a/qemu/riscv32.h b/qemu/riscv32.h index 0947fe09..f9879a9c 100644 --- a/qemu/riscv32.h +++ b/qemu/riscv32.h @@ -4241,6 +4241,27 @@ #define helper_vnmsub_vx_h helper_vnmsub_vx_h_riscv32 #define helper_vnmsub_vx_w helper_vnmsub_vx_w_riscv32 #define helper_vnmsub_vx_d helper_vnmsub_vx_d_riscv32 +#define helper_vwmaccu_vv_b helper_vwmaccu_vv_b_riscv32 +#define helper_vwmaccu_vv_h helper_vwmaccu_vv_h_riscv32 +#define helper_vwmaccu_vv_w helper_vwmaccu_vv_w_riscv32 +#define helper_vwmacc_vv_b helper_vwmacc_vv_b_riscv32 +#define helper_vwmacc_vv_h helper_vwmacc_vv_h_riscv32 +#define helper_vwmacc_vv_w helper_vwmacc_vv_w_riscv32 +#define helper_vwmaccsu_vv_b helper_vwmaccsu_vv_b_riscv32 +#define helper_vwmaccsu_vv_h helper_vwmaccsu_vv_h_riscv32 +#define helper_vwmaccsu_vv_w helper_vwmaccsu_vv_w_riscv32 +#define helper_vwmaccu_vx_b helper_vwmaccu_vx_b_riscv32 +#define helper_vwmaccu_vx_h helper_vwmaccu_vx_h_riscv32 +#define helper_vwmaccu_vx_w helper_vwmaccu_vx_w_riscv32 +#define helper_vwmacc_vx_b helper_vwmacc_vx_b_riscv32 +#define helper_vwmacc_vx_h helper_vwmacc_vx_h_riscv32 +#define helper_vwmacc_vx_w helper_vwmacc_vx_w_riscv32 +#define helper_vwmaccsu_vx_b helper_vwmaccsu_vx_b_riscv32 +#define helper_vwmaccsu_vx_h helper_vwmaccsu_vx_h_riscv32 +#define helper_vwmaccsu_vx_w helper_vwmaccsu_vx_w_riscv32 +#define helper_vwmaccus_vx_b helper_vwmaccus_vx_b_riscv32 +#define helper_vwmaccus_vx_h helper_vwmaccus_vx_h_riscv32 +#define helper_vwmaccus_vx_w helper_vwmaccus_vx_w_riscv32 #define pmp_hart_has_privs pmp_hart_has_privs_riscv32 #define pmpaddr_csr_read pmpaddr_csr_read_riscv32 #define pmpaddr_csr_write pmpaddr_csr_write_riscv32 diff --git a/qemu/riscv64.h b/qemu/riscv64.h index c1b5a67a..be92365e 100644 --- a/qemu/riscv64.h +++ b/qemu/riscv64.h @@ -4241,6 +4241,27 @@ #define helper_vnmsub_vx_h helper_vnmsub_vx_h_riscv64 #define helper_vnmsub_vx_w helper_vnmsub_vx_w_riscv64 #define helper_vnmsub_vx_d helper_vnmsub_vx_d_riscv64 +#define helper_vwmaccu_vv_b helper_vwmaccu_vv_b_riscv64 +#define helper_vwmaccu_vv_h helper_vwmaccu_vv_h_riscv64 +#define helper_vwmaccu_vv_w helper_vwmaccu_vv_w_riscv64 +#define helper_vwmacc_vv_b helper_vwmacc_vv_b_riscv64 +#define helper_vwmacc_vv_h helper_vwmacc_vv_h_riscv64 +#define helper_vwmacc_vv_w helper_vwmacc_vv_w_riscv64 +#define helper_vwmaccsu_vv_b helper_vwmaccsu_vv_b_riscv64 +#define helper_vwmaccsu_vv_h helper_vwmaccsu_vv_h_riscv64 +#define helper_vwmaccsu_vv_w helper_vwmaccsu_vv_w_riscv64 +#define helper_vwmaccu_vx_b helper_vwmaccu_vx_b_riscv64 +#define helper_vwmaccu_vx_h helper_vwmaccu_vx_h_riscv64 +#define helper_vwmaccu_vx_w helper_vwmaccu_vx_w_riscv64 +#define helper_vwmacc_vx_b helper_vwmacc_vx_b_riscv64 +#define helper_vwmacc_vx_h helper_vwmacc_vx_h_riscv64 +#define helper_vwmacc_vx_w helper_vwmacc_vx_w_riscv64 +#define helper_vwmaccsu_vx_b helper_vwmaccsu_vx_b_riscv64 +#define helper_vwmaccsu_vx_h helper_vwmaccsu_vx_h_riscv64 +#define helper_vwmaccsu_vx_w helper_vwmaccsu_vx_w_riscv64 +#define helper_vwmaccus_vx_b helper_vwmaccus_vx_b_riscv64 +#define helper_vwmaccus_vx_h helper_vwmaccus_vx_h_riscv64 +#define helper_vwmaccus_vx_w helper_vwmaccus_vx_w_riscv64 #define pmp_hart_has_privs pmp_hart_has_privs_riscv64 #define pmpaddr_csr_read pmpaddr_csr_read_riscv64 #define pmpaddr_csr_write pmpaddr_csr_write_riscv64 diff --git a/qemu/target/riscv/helper.h b/qemu/target/riscv/helper.h index bef58b69..64816bd2 100644 --- a/qemu/target/riscv/helper.h +++ b/qemu/target/riscv/helper.h @@ -643,3 +643,25 @@ DEF_HELPER_6(vnmsub_vx_b, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnmsub_vx_h, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnmsub_vx_w, void, ptr, ptr, tl, ptr, env, i32) DEF_HELPER_6(vnmsub_vx_d, void, ptr, ptr, tl, ptr, env, i32) + +DEF_HELPER_6(vwmaccu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmacc_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmacc_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmacc_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vv_b, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vv_h, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vv_w, void, ptr, ptr, ptr, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmacc_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmacc_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmacc_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccsu_vx_w, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccus_vx_b, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccus_vx_h, void, ptr, ptr, tl, ptr, env, i32) +DEF_HELPER_6(vwmaccus_vx_w, void, ptr, ptr, tl, ptr, env, i32) diff --git a/qemu/target/riscv/insn32.decode b/qemu/target/riscv/insn32.decode index 3332c467..acb5b0fc 100644 --- a/qemu/target/riscv/insn32.decode +++ b/qemu/target/riscv/insn32.decode @@ -389,6 +389,13 @@ vmadd_vv 101001 . ..... ..... 010 ..... 1010111 @r_vm vmadd_vx 101001 . ..... ..... 110 ..... 1010111 @r_vm vnmsub_vv 101011 . ..... ..... 010 ..... 1010111 @r_vm vnmsub_vx 101011 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccu_vv 111100 . ..... ..... 010 ..... 1010111 @r_vm +vwmaccu_vx 111100 . ..... ..... 110 ..... 1010111 @r_vm +vwmacc_vv 111101 . ..... ..... 010 ..... 1010111 @r_vm +vwmacc_vx 111101 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccsu_vv 111110 . ..... ..... 010 ..... 1010111 @r_vm +vwmaccsu_vx 111110 . ..... ..... 110 ..... 1010111 @r_vm +vwmaccus_vx 111111 . ..... ..... 110 ..... 1010111 @r_vm vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm vsetvl 1000000 ..... ..... 111 ..... 1010111 @r diff --git a/qemu/target/riscv/insn_trans/trans_rvv.inc.c b/qemu/target/riscv/insn_trans/trans_rvv.inc.c index 81231a91..63a127ff 100644 --- a/qemu/target/riscv/insn_trans/trans_rvv.inc.c +++ b/qemu/target/riscv/insn_trans/trans_rvv.inc.c @@ -1540,3 +1540,12 @@ GEN_OPIVX_TRANS(vmacc_vx, opivx_check) GEN_OPIVX_TRANS(vnmsac_vx, opivx_check) GEN_OPIVX_TRANS(vmadd_vx, opivx_check) GEN_OPIVX_TRANS(vnmsub_vx, opivx_check) + +/* Vector Widening Integer Multiply-Add Instructions */ +GEN_OPIVV_WIDEN_TRANS(vwmaccu_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmacc_vv, opivv_widen_check) +GEN_OPIVV_WIDEN_TRANS(vwmaccsu_vv, opivv_widen_check) +GEN_OPIVX_WIDEN_TRANS(vwmaccu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmacc_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccsu_vx) +GEN_OPIVX_WIDEN_TRANS(vwmaccus_vx) diff --git a/qemu/target/riscv/vector_helper.c b/qemu/target/riscv/vector_helper.c index 9322824a..6fad9f0e 100644 --- a/qemu/target/riscv/vector_helper.c +++ b/qemu/target/riscv/vector_helper.c @@ -1966,3 +1966,48 @@ GEN_VEXT_VX(vnmsub_vx_b, 1, 1, clearb) GEN_VEXT_VX(vnmsub_vx_h, 2, 2, clearh) GEN_VEXT_VX(vnmsub_vx_w, 4, 4, clearl) GEN_VEXT_VX(vnmsub_vx_d, 8, 8, clearq) + +/* Vector Widening Integer Multiply-Add Instructions */ +RVVCALL(OPIVV3, vwmaccu_vv_b, WOP_UUU_B, H2, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vwmaccu_vv_h, WOP_UUU_H, H4, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vwmaccu_vv_w, WOP_UUU_W, H8, H4, H4, DO_MACC) +RVVCALL(OPIVV3, vwmacc_vv_b, WOP_SSS_B, H2, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vwmacc_vv_h, WOP_SSS_H, H4, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vwmacc_vv_w, WOP_SSS_W, H8, H4, H4, DO_MACC) +RVVCALL(OPIVV3, vwmaccsu_vv_b, WOP_SSU_B, H2, H1, H1, DO_MACC) +RVVCALL(OPIVV3, vwmaccsu_vv_h, WOP_SSU_H, H4, H2, H2, DO_MACC) +RVVCALL(OPIVV3, vwmaccsu_vv_w, WOP_SSU_W, H8, H4, H4, DO_MACC) +GEN_VEXT_VV(vwmaccu_vv_b, 1, 2, clearh) +GEN_VEXT_VV(vwmaccu_vv_h, 2, 4, clearl) +GEN_VEXT_VV(vwmaccu_vv_w, 4, 8, clearq) +GEN_VEXT_VV(vwmacc_vv_b, 1, 2, clearh) +GEN_VEXT_VV(vwmacc_vv_h, 2, 4, clearl) +GEN_VEXT_VV(vwmacc_vv_w, 4, 8, clearq) +GEN_VEXT_VV(vwmaccsu_vv_b, 1, 2, clearh) +GEN_VEXT_VV(vwmaccsu_vv_h, 2, 4, clearl) +GEN_VEXT_VV(vwmaccsu_vv_w, 4, 8, clearq) + +RVVCALL(OPIVX3, vwmaccu_vx_b, WOP_UUU_B, H2, H1, DO_MACC) +RVVCALL(OPIVX3, vwmaccu_vx_h, WOP_UUU_H, H4, H2, DO_MACC) +RVVCALL(OPIVX3, vwmaccu_vx_w, WOP_UUU_W, H8, H4, DO_MACC) +RVVCALL(OPIVX3, vwmacc_vx_b, WOP_SSS_B, H2, H1, DO_MACC) +RVVCALL(OPIVX3, vwmacc_vx_h, WOP_SSS_H, H4, H2, DO_MACC) +RVVCALL(OPIVX3, vwmacc_vx_w, WOP_SSS_W, H8, H4, DO_MACC) +RVVCALL(OPIVX3, vwmaccsu_vx_b, WOP_SSU_B, H2, H1, DO_MACC) +RVVCALL(OPIVX3, vwmaccsu_vx_h, WOP_SSU_H, H4, H2, DO_MACC) +RVVCALL(OPIVX3, vwmaccsu_vx_w, WOP_SSU_W, H8, H4, DO_MACC) +RVVCALL(OPIVX3, vwmaccus_vx_b, WOP_SUS_B, H2, H1, DO_MACC) +RVVCALL(OPIVX3, vwmaccus_vx_h, WOP_SUS_H, H4, H2, DO_MACC) +RVVCALL(OPIVX3, vwmaccus_vx_w, WOP_SUS_W, H8, H4, DO_MACC) +GEN_VEXT_VX(vwmaccu_vx_b, 1, 2, clearh) +GEN_VEXT_VX(vwmaccu_vx_h, 2, 4, clearl) +GEN_VEXT_VX(vwmaccu_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmacc_vx_b, 1, 2, clearh) +GEN_VEXT_VX(vwmacc_vx_h, 2, 4, clearl) +GEN_VEXT_VX(vwmacc_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmaccsu_vx_b, 1, 2, clearh) +GEN_VEXT_VX(vwmaccsu_vx_h, 2, 4, clearl) +GEN_VEXT_VX(vwmaccsu_vx_w, 4, 8, clearq) +GEN_VEXT_VX(vwmaccus_vx_b, 1, 2, clearh) +GEN_VEXT_VX(vwmaccus_vx_h, 2, 4, clearl) +GEN_VEXT_VX(vwmaccus_vx_w, 4, 8, clearq)