From a02b9b81a9d84f30a5d3feea5a07dee5cb8a0450 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Alex=20Benn=C3=A9e?= Date: Thu, 8 Mar 2018 15:36:50 -0500 Subject: [PATCH] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16 Backports commit 2deb992b767d28035fac3b374c7730494ff0b43d from qemu Also backports the fp16 changes introduced in commit f566c0474a9b9bbd9ed248607e4007e24d3358c0 --- qemu/aarch64.h | 2 ++ qemu/aarch64eb.h | 2 ++ qemu/header_gen.py | 2 ++ qemu/include/fpu/softfloat.h | 20 ++++++++++++++++++++ qemu/target/arm/helper-a64.c | 24 ++++++++++++++++++++++++ qemu/target/arm/helper-a64.h | 2 ++ qemu/target/arm/translate-a64.c | 15 +++++++++++++++ 7 files changed, 67 insertions(+) diff --git a/qemu/aarch64.h b/qemu/aarch64.h index 9a1a2295..18a4c418 100644 --- a/qemu/aarch64.h +++ b/qemu/aarch64.h @@ -3731,7 +3731,9 @@ #define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64 #define helper_advsimd_minh helper_advsimd_minh_aarch64 #define helper_advsimd_minnumh helper_advsimd_minnumh_aarch64 +#define helper_advsimd_muladdh helper_advsimd_muladdh_aarch64 #define helper_advsimd_mulh helper_advsimd_mulh_aarch64 +#define helper_advsimd_mulxh helper_advsimd_mulxh_aarch64 #define helper_advsimd_subh helper_advsimd_subh_aarch64 #define helper_crc32_64 helper_crc32_64_aarch64 #define helper_crc32c_64 helper_crc32c_64_aarch64 diff --git a/qemu/aarch64eb.h b/qemu/aarch64eb.h index e2738489..459658bd 100644 --- a/qemu/aarch64eb.h +++ b/qemu/aarch64eb.h @@ -3731,7 +3731,9 @@ #define helper_advsimd_maxnumh helper_advsimd_maxnumh_aarch64eb #define helper_advsimd_minh helper_advsimd_minh_aarch64eb #define helper_advsimd_minnumh helper_advsimd_minnumh_aarch64eb +#define helper_advsimd_muladdh helper_advsimd_muladdh_aarch64eb #define helper_advsimd_mulh helper_advsimd_mulh_aarch64eb +#define helper_advsimd_mulxh helper_advsimd_mulxh_aarch64eb #define helper_advsimd_subh helper_advsimd_subh_aarch64eb #define helper_crc32_64 helper_crc32_64_aarch64eb #define helper_crc32c_64 helper_crc32c_64_aarch64eb diff --git a/qemu/header_gen.py b/qemu/header_gen.py index faea172e..792a28cd 100644 --- a/qemu/header_gen.py +++ b/qemu/header_gen.py @@ -3751,7 +3751,9 @@ aarch64_symbols = ( 'helper_advsimd_maxnumh', 'helper_advsimd_minh', 'helper_advsimd_minnumh', + 'helper_advsimd_muladdh', 'helper_advsimd_mulh', + 'helper_advsimd_mulxh', 'helper_advsimd_subh', 'helper_crc32_64', 'helper_crc32c_64', diff --git a/qemu/include/fpu/softfloat.h b/qemu/include/fpu/softfloat.h index 73b3dcf3..4dc4a5e1 100644 --- a/qemu/include/fpu/softfloat.h +++ b/qemu/include/fpu/softfloat.h @@ -271,6 +271,26 @@ static inline int float16_is_any_nan(float16 a) return ((float16_val(a) & ~0x8000) > 0x7c00); } +static inline int float16_is_neg(float16 a) +{ + return float16_val(a) >> 15; +} + +static inline int float16_is_infinity(float16 a) +{ + return (float16_val(a) & 0x7fff) == 0x7c00; +} + +static inline int float16_is_zero(float16 a) +{ + return (float16_val(a) & 0x7fff) == 0; +} + +static inline int float16_is_zero_or_denormal(float16 a) +{ + return (float16_val(a) & 0x7c00) == 0; +} + static inline float16 float16_abs(float16 a) { /* Note that abs does *not* handle NaN specially, nor does diff --git a/qemu/target/arm/helper-a64.c b/qemu/target/arm/helper-a64.c index f2ab52b4..ebc60965 100644 --- a/qemu/target/arm/helper-a64.c +++ b/qemu/target/arm/helper-a64.c @@ -641,6 +641,30 @@ ADVSIMD_HALFOP(max) ADVSIMD_HALFOP(minnum) ADVSIMD_HALFOP(maxnum) +/* Data processing - scalar floating-point and advanced SIMD */ +float16 HELPER(advsimd_mulxh)(float16 a, float16 b, void *fpstp) +{ + float_status *fpst = fpstp; + + a = float16_squash_input_denormal(a, fpst); + b = float16_squash_input_denormal(b, fpst); + + if ((float16_is_zero(a) && float16_is_infinity(b)) || + (float16_is_infinity(a) && float16_is_zero(b))) { + /* 2.0 with the sign bit set to sign(A) XOR sign(B) */ + return make_float16((1U << 14) | + ((float16_val(a) ^ float16_val(b)) & (1U << 15))); + } + return float16_mul(a, b, fpst); +} + +/* fused multiply-accumulate */ +float16 HELPER(advsimd_muladdh)(float16 a, float16 b, float16 c, void *fpstp) +{ + float_status *fpst = fpstp; + return float16_muladd(a, b, c, 0, fpst); +} + /* * Floating point comparisons produce an integer result. Softfloat * routines return float_relation types which we convert to the 0/-1 diff --git a/qemu/target/arm/helper-a64.h b/qemu/target/arm/helper-a64.h index c5c4b390..655a4354 100644 --- a/qemu/target/arm/helper-a64.h +++ b/qemu/target/arm/helper-a64.h @@ -57,3 +57,5 @@ DEF_HELPER_3(advsimd_cge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_cgt_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acge_f16, i32, f16, f16, ptr) DEF_HELPER_3(advsimd_acgt_f16, i32, f16, f16, ptr) +DEF_HELPER_3(advsimd_mulxh, f16, f16, f16, ptr) +DEF_HELPER_4(advsimd_muladdh, f16, f16, f16, f16, ptr) diff --git a/qemu/target/arm/translate-a64.c b/qemu/target/arm/translate-a64.c index 531d435e..35103066 100644 --- a/qemu/target/arm/translate-a64.c +++ b/qemu/target/arm/translate-a64.c @@ -10438,9 +10438,17 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x0: /* FMAXNM */ gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x1: /* FMLA */ + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, tcg_res, + fpst); + break; case 0x2: /* FADD */ gen_helper_advsimd_addh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x3: /* FMULX */ + gen_helper_advsimd_mulxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); + break; case 0x4: /* FCMEQ */ gen_helper_advsimd_ceq_f16(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break; @@ -10450,6 +10458,13 @@ static void disas_simd_three_reg_same_fp16(DisasContext *s, uint32_t insn) case 0x8: /* FMINNM */ gen_helper_advsimd_minnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break; + case 0x9: /* FMLS */ + /* As usual for ARM, separate negation for fused multiply-add */ + tcg_gen_xori_i32(tcg_ctx, tcg_op1, tcg_op1, 0x8000); + read_vec_element_i32(s, tcg_res, rd, pass, MO_16); + gen_helper_advsimd_muladdh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, tcg_res, + fpst); + break; case 0xa: /* FSUB */ gen_helper_advsimd_subh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst); break;