diff --git a/qemu/target-arm/helper.c b/qemu/target-arm/helper.c
index c1383b82..8b0e74d3 100644
--- a/qemu/target-arm/helper.c
+++ b/qemu/target-arm/helper.c
@@ -1156,7 +1156,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       gt_ptimer_access, gt_tval_read, gt_tval_write, },
     { "CNTP_TVAL_EL0", 0,14,2, 3,3,0, ARM_CP_STATE_AA64,
       ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
-      NULL, gt_tval_read, gt_tval_write, },
+      gt_ptimer_access, gt_tval_read, gt_tval_write, },
     { "CNTV_TVAL", 15,14,3, 0,0,0, 0,
       ARM_CP_NO_RAW | ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, 0, {0, 0},
       gt_vtimer_access, gt_tval_read, gt_tval_write, },
@@ -1182,7 +1182,7 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
       gt_ptimer_access, NULL, gt_cval_write, NULL, raw_write, arm_cp_reset_ignore, },
     { "CNTP_CVAL_EL0", 0,14,2, 3,3,2, ARM_CP_STATE_AA64,
       ARM_CP_IO, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval), {0, 0},
-      gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, },
+      gt_ptimer_access, NULL, gt_cval_write, NULL, raw_write, },
     { "CNTV_CVAL", 15, 0,14, 0,3,0, 0,
       ARM_CP_64BIT | ARM_CP_IO | ARM_CP_ALIAS, PL1_RW | PL0_R, 0, NULL, 0, offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval), {0, 0},
       gt_vtimer_access, NULL, gt_cval_write, NULL, raw_write, arm_cp_reset_ignore, },