From a338e9c8555fb5f8cf6ca8a26689e46c7bf5163a Mon Sep 17 00:00:00 2001 From: Leon Alrae Date: Sun, 4 Mar 2018 00:24:03 -0500 Subject: [PATCH] target-mips: enable CM GCR in MIPS64R6-generic CPU --- qemu/target/mips/translate_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/qemu/target/mips/translate_init.c b/qemu/target/mips/translate_init.c index 5b7d76d5..7bbcea8e 100644 --- a/qemu/target/mips/translate_init.c +++ b/qemu/target/mips/translate_init.c @@ -583,7 +583,7 @@ static const mips_def_t mips_defs[] = (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_FP), MIPS_CONFIG2, - MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP) | + MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_CMGCR) | (1 << CP0C3_MSAP) | (1 << CP0C3_BP) | (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1 << CP0C3_RXI) | (1 << CP0C3_LPA) | (1 << CP0C3_VInt), MIPS_CONFIG4 | (1U << CP0C4_M) | (2 << CP0C4_IE) |